Diff: si5351a.cpp

Revision:

1:a2309757c450

Parent:

0:47b9bfa03730

Child:

2:8fe745836ea6

--- a/si5351a.cpp	Sun Jan 01 01:21:34 2017 +0000
+++ b/si5351a.cpp	Thu Jan 05 12:28:27 2017 +0000
@@ -24,7 +24,7 @@
  *      http://mbed.org/users/kenjiArai/
  *
  *      Started:  December 24th, 2016
- *      Revised:  January   1st, 2017
+ *      Revised:  January   5th, 2017
  *
  */
 
@@ -213,7 +213,6 @@
         return f_err; // return current frequency
     }
     uint32_t P1, P2, P3;
-    uint32_t multisynth_vale;
     double   multisynth_double;
     const uint8_t msreg_base[] = {
         SI5351_REG_42_MULTISYNTH0,
@@ -222,9 +221,8 @@
     };
     uint8_t baseaddr = msreg_base[channel];
     // Fractional mode
-    multisynth_vale = (floor)((double)num /(double)denom);
-    P1 = 128 * div + 128 * multisynth_vale - 512;
-    P2 = 128 * num - denom * 128 * multisynth_vale;
+    P1 = (uint32_t)(128 * div + floor(128 * ((float)num/(float)denom)) - 512);
+    P2 = (uint32_t)(128 * num - denom * floor(128 * ((float)num/(float)denom)));
     P3 = denom;
     multisynth_double = div + (double)num /(double)denom;
     // a + b/c between 6..1800
@@ -366,7 +364,7 @@
     si5351_write(SI5351_REG_177_PLL_RESET, 0xa0);
 }
 
-/**************************************************************************/
+/******************************************************************************/
 /*!
     @brief  Sets the multiplier for the specified PLL
 
@@ -389,7 +387,7 @@
     (only use the a part, setting b to '0' and c to '1').
     See: http://www.silabs.com/Support%20Documents/TechnicalDocs/AN619.pdf
 */
-/**************************************************************************/
+/******************************************************************************/
 void SI5351A::si5351_setupPLL(
                 uint8_t     pll,
                 uint8_t     mult,
@@ -481,6 +479,7 @@
     DBG("DBG: Use 26(PLLA) or 34(PLLB)) ->%u and write data\r\n", baseaddr);
     double f = base_freq * (mult + ((double)num / (double)denom));
     DBG("DBG: PLL f=%u\r\n", (uint32_t)f);
+    DBG("DBG: PLL f(pll_freq)=%u\r\n", (uint32_t)pll_freq);
     if (pll == SI5351_PLL_A){
         plla_freq = f;
     } else { // SI5351_PLL_B
@@ -488,7 +487,7 @@
     }
 }
 
-/**************************************************************************/
+/******************************************************************************/
 /*!
     @brief  Configures the Multisynth divider, which determines the
             output clock frequency based on the specified PLL input.
@@ -537,7 +536,7 @@
     @note   For frequencies below 500kHz (down to 8kHz) Rx_DIV must be
             used, but this isn't currently implemented in the driver.
 */
-/**************************************************************************/
+/******************************************************************************/
 double SI5351A::si5351_setupMultisynth( 
                 uint8_t     output,
                 uint8_t     pllSource,
@@ -550,7 +549,6 @@
     uint32_t P2;       /* Multisynth config register P2 */
     uint32_t P3;       /* Multisynth config register P3 */
     uint32_t div4 = 0;
-    uint32_t multisynth_vale;
     double   multisynth_double;
 
     DBG("DBG: Enter si5351_setupMultisynth\r\n");
@@ -609,9 +607,10 @@
     } else {
         /* Fractional mode */
         DBG("DBG: enter Fractional mode\r\n");
-        multisynth_vale = (floor)((double)num /(double)denom);
-        P1 = 128 * div + 128 * multisynth_vale - 512;
-        P2 = 128 * num - denom * 128 * multisynth_vale;
+        P1 = (uint32_t)
+            (128 * div + floor(128 * ((float)num/(float)denom)) - 512);
+        P2 = (uint32_t)
+            (128 * num - denom * floor(128 * ((float)num/(float)denom)));
         P3 = denom;
         multisynth_double = div + (double)num /(double)denom;
         /* a + b/c between 6..1800 */
@@ -961,7 +960,7 @@
     printf("%umA\r\n", 2 + 2 * (dt & 0x03));     
 }
 
-/**************************************************************************/
+/******************************************************************************/
 /*!
     @brief  Configures the Si5351 with config settings generated in
             ClockBuilder. You can use this function to make sure that
@@ -974,7 +973,7 @@
             * Channel 2: 13.56  MHz
     @note   This will overwrite all of the config registers!
 */
-/**************************************************************************/
+/******************************************************************************/
 /* Test setup from SI5351 ClockBuilder
  * -----------------------------------
  * XTAL:      25     MHz