Kenji Arai
Barometer program : Data Logger function includes Barometer & temperature (BMP180), Humidity & temp. (RHT03), Sunshine (Cds), RTC(M41T62) data. : Logging data saves into EEPROM (AT24C1024) using ring buffer function.
Dependencies: AT24C1024 RHT03 TextLCD BMP180 M41T62
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mon_hw.cpp
00001 #if 0 00002 //?????????????????????????????????????????????????????????????????????????????? 00003 // Due to ROM & RAM size limitation 00004 //?????????????????????????????????????????????????????????????????????????????? 00005 00006 /* 00007 * mbed Application program for the mbed LPC1114FN28 00008 * Monitor program Ver.2 for only LPC1114FN28 00009 * 00010 * Copyright (c) 2014,'20 Kenji Arai / JH1PJL 00011 * http://www7b.biglobe.ne.jp/~kenjia/ 00012 * https://os.mbed.com/users/kenjiArai/ 00013 * Created: June 1st, 2014 00014 * Revised: August 8th, 2020 00015 */ 00016 /* 00017 * Function 00018 * Show Memory contents, Digital port, Analog input port, CPU clock and others in the mbed board 00019 * Connection 00020 * uart USB Vertual com 00021 */ 00022 00023 // Include --------------------------------------------------------------------------------------- 00024 #include "mbed.h" 00025 #include "AT24C1024.h" // Own lib. / EEPROM control 00026 #include "mon_hw_config.h" 00027 #include "redirect_stdio.h" 00028 00029 // Object ---------------------------------------------------------------------------------------- 00030 extern I2C xxi2c; // SDA, SCL 00031 extern AT24C1024 xat24c1024; // Atmel 1Mbit EE-PROM 00032 00033 // Definition ------------------------------------------------------------------------------------ 00034 // Define clocks 00035 #define __XTAL (12000000UL) // Oscillator frequency 00036 #define __SYS_OSC_CLK ( __XTAL) // Main oscillator frequency 00037 #define __IRC_OSC_CLK (12000000UL) // Internal RC oscillator frequency 00038 00039 // Range check status 00040 #define ERR_NOTHING 0 00041 #define ERR_MODIFY_SIZ 1 00042 #define ERR_OUT_OF_RANGE 2 00043 00044 // Reg. Size 00045 #define SIZE8 32 00046 #define SIZE16 16 00047 #define SIZE_FULL 32 00048 #define SIZE_X 32 00049 00050 // IO Cinfig 00051 #define IO_ALL 0 00052 #define IO_I2C 1 00053 00054 #define GETC(x) getc(x) 00055 #define PUTC(x) putc(x) 00056 #define PRINTF(...) printf(__VA_ARGS__) 00057 #define READABLE(x) readable(x) 00058 00059 typedef struct { 00060 unsigned long mstr; 00061 unsigned long msiz; 00062 unsigned long mtmp; 00063 unsigned long mold; 00064 unsigned char mflg; 00065 unsigned char mbhw; 00066 } MEMO; 00067 00068 #define DW_CHAR sizeof(char) 00069 #define DW_SHORT sizeof(short) 00070 #define DW_LONG sizeof(long) 00071 00072 typedef unsigned long DWORD; 00073 typedef unsigned short WORD; 00074 typedef unsigned char BYTE; 00075 typedef unsigned int UINT; 00076 00077 // RAM ------------------------------------------------------------------------------------------- 00078 // Memory management 00079 unsigned long SystemFrequency; 00080 00081 #if USE_MEM 00082 // RAM ------------------------------------------------------------------------------------------- 00083 static MEMO mem; 00084 00085 // ROM / Constant data --------------------------------------------------------------------------- 00086 // Memory range data 00087 const uint32_t mem_range[][2] = { // Memory access range 00088 { 0x00000000, 0x00007fff }, // On-chip non-volatile memory //32KB Flash memory 00089 { 0x10000000, 0x10000fff }, // On-chip SRAM //4KB local RAM 00090 { 0x1fff0000, 0x1fff3fff }, // Boot ROM //16KB Boot ROM 00091 { 0x40000000, 0x4007ffff }, // IO area 00092 { 0x50000000, 0x501fffff } // IO area 00093 }; 00094 00095 static const char *const rmsg0 = "FLASH "; 00096 static const char *const rmsg1 = "SRAM "; 00097 static const char *const rmsg2 = "BOOT ROM "; 00098 static const char *const rmsg3 = "IO "; 00099 static const char *const rmsg4 = "IO "; 00100 #endif // USE_MEM 00101 00102 #if USE_EEP 00103 // RAM ------------------------------------------------------------------------------------------- 00104 static MEMO eepmem; 00105 00106 // ROM / Constant data --------------------------------------------------------------------------- 00107 const uint32_t eepmem_range[2] = { /* Memory access range */ 00108 0x00000, 0x1ffff /* EEPROM 1Mbits 128Kbytes */ 00109 }; 00110 #endif 00111 00112 // ROM / Constant data --------------------------------------------------------------------------- 00113 static const char *const mon_msg_hw = "HW monitor only for mbed LPC1114FN28"; 00114 00115 // Function prototypes --------------------------------------------------------------------------- 00116 extern char linebuf[]; 00117 extern int buf_size; 00118 00119 extern void put_rn ( void ); 00120 extern void put_r ( void ); 00121 extern void put_lin ( void ); 00122 extern void put_spc( uint8_t n); 00123 extern void get_line (char *buff, int len); 00124 extern int xatoi (char **str, unsigned long *res); 00125 00126 //------------------------------------------------------------------------------------------------- 00127 // Control Program 00128 //------------------------------------------------------------------------------------------------- 00129 // Help Massage 00130 void msg_hlp_hw (void){ 00131 PRINTF(mon_msg_hw); 00132 put_rn(); 00133 #if USE_MEM 00134 PRINTF("m - Entry Memory Mode"); 00135 put_rn(); 00136 PRINTF("m>? -> Help "); 00137 put_rn(); 00138 #endif // USE_MEM 00139 #if USE_EEP 00140 PRINTF("e -Enter EEPROM Memory Mode "); 00141 put_rn(); 00142 PRINTF("e>? -> Help "); 00143 put_rn(); 00144 #endif // USE_EEP 00145 #if USE_REG_SPI_UART 00146 PRINTF("r - Show SPI & UART Reg."); 00147 put_rn(); 00148 PRINTF("r>? -> Help "); 00149 put_rn(); 00150 #endif // USE_REG_SPI_UART 00151 #if USE_PORT 00152 PRINTF("p - Show port configration"); 00153 put_rn(); 00154 #endif // USE_PORT 00155 #if USE_REG_I2C 00156 PRINTF("i - Show I2C Reg."); 00157 put_rn(); 00158 #endif // USE_REG_I2C 00159 #if USE_SYS 00160 PRINTF("sf - System Clock"); 00161 put_rn(); 00162 PRINTF("sc - System / CPU information"); 00163 put_rn(); 00164 #endif // USE_SYS 00165 #if USE_RPT 00166 PRINTF("/ [a],[p] commands every 1 sec Exit =hit any key (not ENTER key) "); 00167 put_rn(); 00168 #endif 00169 #if DEBUG 00170 PRINTF("x Special command for Debug "); 00171 put_rn(); 00172 #endif // DEBUG 00173 PRINTF("q - Quit (back to called routine)"); 00174 put_rn(); 00175 } 00176 00177 // No function 00178 static void not_yet_impliment( void ){ 00179 PRINTF( "Not implimented yet" ); 00180 put_rn(); 00181 } 00182 00183 const char *const imsg2 = "-->Control Reg."; 00184 const char *const imsg3 = "-->Status Reg."; 00185 const char *const imsg4 = "-->Data Reg."; 00186 //static const char *const imsg5 = "-->Baud rate Reg."; 00187 //static const char *const imsg6 = "-->Own address Reg."; 00188 const char *const imsg7 = "-->Clock control Reg."; 00189 //static const char *const imsg8 = "-->TRISE Reg."; 00190 00191 static const char *const io_port_name0 = "PIO0_"; 00192 static const char *const io_port_name1 = "PIO1_"; 00193 static const char *const iomsg0 = "Func->select "; 00194 static const char *const iomsg1 = "IO"; 00195 static const char *const iomsg2 = "Reserved"; 00196 static const char *const iomsg30 = "B0_MAT"; 00197 static const char *const iomsg31 = "B1_MAT"; 00198 static const char *const iomsg4 = "Std/F-md I2C"; 00199 static const char *const iomsg5 = "func. R"; 00200 static const char *const iomsg6 = "D-Mode"; 00201 static const char *const iomsg7 = "A-Mode"; 00202 00203 // Show 16bit register contents 00204 void reg_print(uint16_t size, uint16_t reg){ 00205 uint16_t i, j, k, n; 00206 00207 if (size == 8){ 00208 PRINTF(" 7, 6, 5, 4, 3, 2, 1, 0"); 00209 put_rn(); 00210 i = 8; 00211 n = 0x80; 00212 } else if (size == 16){ 00213 PRINTF( "15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0" ); 00214 put_rn(); 00215 i = 16; 00216 n = 0x8000; 00217 } else { 00218 PRINTF("0x%08x", reg); 00219 return; 00220 } 00221 PUTC(' '); 00222 for (; i>0; i--){ 00223 k = n >> (size-i); 00224 j = reg & k; 00225 if (j){ 00226 PUTC('1'); 00227 } else { 00228 PUTC('0'); 00229 } 00230 PUTC(' '); 00231 PUTC(' '); 00232 } 00233 PRINTF(" (0x%04x)", reg); 00234 } 00235 00236 #if USE_PORT 00237 void io_mode(uint32_t reg){ 00238 PRINTF("MODE->"); 00239 switch (reg){ 00240 case 0: 00241 PRINTF("Inactive"); 00242 break; 00243 case 1: 00244 PRINTF("P-DWN"); 00245 break; 00246 case 2: 00247 PRINTF("P-UP"); 00248 break; 00249 case 3: 00250 PRINTF("Repeater"); 00251 break; 00252 } 00253 } 00254 00255 void io_hys(uint32_t reg){ 00256 PRINTF("HIS->"); 00257 switch (reg){ 00258 case 0: 00259 PRINTF("Dis"); 00260 break; 00261 case 1: 00262 PRINTF("Ena"); 00263 break; 00264 } 00265 } 00266 00267 void io_od(uint32_t reg){ 00268 PRINTF("OD->"); 00269 switch (reg){ 00270 case 0: 00271 PRINTF("no OD"); 00272 break; 00273 case 1: 00274 PRINTF("OD"); 00275 break; 00276 } 00277 } 00278 00279 void io_mode_hys_od(uint32_t reg){ 00280 io_mode ((reg >> 3) & 0x3); 00281 put_lin(); 00282 io_hys (( reg >> 5) & 0x1); 00283 put_lin(); 00284 io_od (( reg >> 10) & 0x1); 00285 } 00286 00287 // I/O Config IO0_x 00288 void io_config0(void){ 00289 uint32_t r0; 00290 00291 // P0_0 00292 r0 = LPC_IOCON->RESET_PIO0_0; 00293 PRINTF("RESET_%s0(dp23)", io_port_name0); 00294 put_spc(1); 00295 reg_print( SIZE_X, r0 ); 00296 put_spc(2); 00297 PRINTF( iomsg0 ); 00298 if ((r0 & 0x7) == 0){ PRINTF("RESET"); 00299 } else { PRINTF( iomsg1 ); } 00300 put_lin(); 00301 io_mode_hys_od( r0 ); 00302 put_rn(); 00303 // P0_1 00304 r0 = LPC_IOCON->PIO0_1; 00305 PRINTF("%s1(dp24)", io_port_name0); 00306 put_spc(3); 00307 reg_print( SIZE_X, r0 ); 00308 put_spc(2); 00309 PRINTF( iomsg0 ); 00310 switch (r0 & 0x7){ 00311 case 0: PRINTF(iomsg1); break; 00312 case 1: PRINTF("CLKOUT"); break; 00313 case 2: PRINTF("32%s2", iomsg30); break; 00314 } 00315 put_lin(); 00316 io_mode_hys_od(r0); 00317 put_rn(); 00318 // P0_2 00319 r0 = LPC_IOCON->PIO0_2; 00320 PRINTF("%s2(dp25)",io_port_name0); 00321 put_spc(3); 00322 reg_print(SIZE_X, r0); 00323 put_spc(2); 00324 PRINTF(iomsg0); 00325 switch (r0 & 0x7){ 00326 case 0: PRINTF(iomsg1); break; 00327 case 1: PRINTF("SSEL0"); break; 00328 case 2: PRINTF("16B0_CAP0"); break; 00329 } 00330 put_lin(); 00331 io_mode_hys_od(r0); 00332 put_rn(); 00333 // P0_3 00334 r0 = LPC_IOCON->PIO0_3; 00335 PRINTF("%s3(dp26)",io_port_name0); 00336 put_spc(3); 00337 reg_print(SIZE_X, r0); 00338 put_spc(2); 00339 PRINTF(iomsg0); 00340 switch (r0 & 0x7){ 00341 case 0: PRINTF(iomsg1); break; 00342 } 00343 put_lin(); 00344 io_mode_hys_od(r0); 00345 put_rn(); 00346 // P0_4 00347 r0 = LPC_IOCON->PIO0_4; 00348 PRINTF("%s4(dp27)",io_port_name0); 00349 put_spc(3); 00350 reg_print(SIZE_X, r0); 00351 put_spc(2); 00352 PRINTF(iomsg0); 00353 switch (r0 & 0x7){ 00354 case 0: PRINTF(iomsg1); break; 00355 case 1: PRINTF("SCL"); break; 00356 } 00357 put_lin(); 00358 switch (( r0 >> 8 ) & 0x3){ 00359 case 0: PRINTF(iomsg4); break; 00360 case 1: PRINTF(iomsg1); break; 00361 case 2: PRINTF("Fast md"); break; 00362 case 3: PRINTF(iomsg2 ; break; 00363 } 00364 put_rn(); 00365 // P0_5 00366 r0 = LPC_IOCON->PIO0_5; 00367 PRINTF("%s5(dp5)",io_port_name0); 00368 put_spc(4); 00369 reg_print(SIZE_X, r0); 00370 put_spc(2); 00371 PRINTF(iomsg0); 00372 switch (r0 & 0x7){ 00373 case 0: PRINTF(iomsg1); break; 00374 case 1: PRINTF("SDA"); break; 00375 } 00376 put_lin(); 00377 switch ( ( r0 >> 8 ) & 0x3 ){ 00378 case 0: PRINTF(iomsg4); break; 00379 case 1: PRINTF(iomsg1); break; 00380 case 2: PRINTF("Fast md"); break; 00381 case 3: PRINTF(iomsg2); break; 00382 } 00383 put_rn(); 00384 // P0_6 00385 r0 = LPC_IOCON->PIO0_6; 00386 PRINTF("%s6(dp6)", io_port_name0); 00387 put_spc(4); 00388 reg_print(SIZE_X, r0); 00389 put_spc(2); 00390 PRINTF(iomsg0); 00391 switch (r0 & 0x7){ 00392 case 0: PRINTF(iomsg1); break; 00393 case 1: PRINTF(iomsg2); break; 00394 case 2: PRINTF("SCK0"); break; 00395 } 00396 put_lin(); 00397 io_mode_hys_od(r0); 00398 put_rn(); 00399 // P0_7 00400 r0 = LPC_IOCON->PIO0_7; 00401 PRINTF("%s7(dp28)", io_port_name0); 00402 put_spc(3); 00403 reg_print(SIZE_X, r0); 00404 put_spc(2); 00405 PRINTF(iomsg0 ; 00406 switch (r0 & 0x7){ 00407 case 0: PRINTF(iomsg1); break; 00408 case 1: PRINTF("CTS"); break; 00409 } 00410 put_lin(); 00411 io_mode_hys_od(r0); 00412 put_rn(); 00413 // P0_8 00414 r0 = LPC_IOCON->PIO0_8; 00415 PRINTF("%s8(dp1)", io_port_name0); 00416 put_spc(4); 00417 reg_print(SIZE_X, r0); 00418 put_spc(2); 00419 PRINTF(iomsg0); 00420 switch (r0 & 0x7){ 00421 case 0: PRINTF(iomsg1); break; 00422 case 1: PRINTF("MISO0"); break; 00423 case 2: PRINTF("16%s0", iomsg30); break; 00424 } 00425 put_lin(); 00426 io_mode_hys_od(r0); 00427 put_rn(); 00428 // P0_9 00429 r0 = LPC_IOCON->PIO0_9; 00430 PRINTF("%s9(dp2)", io_port_name0); 00431 put_spc(4); 00432 reg_print(SIZE_X, r0); 00433 put_spc(2); 00434 PRINTF(iomsg0); 00435 switch (r0 & 0x7){ 00436 case 0: PRINTF(iomsg1); break; 00437 case 1: PRINTF("MOSI0"); break; 00438 case 2: PRINTF("16%s1", iomsg30); break; 00439 } 00440 put_lin(); 00441 io_mode_hys_od(r0); 00442 put_rn(); 00443 // P0_10 00444 r0 = LPC_IOCON->SWCLK_PIO0_10; 00445 PRINTF("SWCLK_%s10(dp3)", io_port_name0); 00446 put_spc(1); 00447 reg_print(SIZE_X, r0); 00448 put_spc(2); 00449 PRINTF(iomsg0); 00450 switch (r0 & 0x7 { 00451 case 0: PRINTF("SWCLK"); break; 00452 case 1: PRINTF(iomsg1); break; 00453 case 2: PRINTF("SCK0"); break; 00454 case 3: PRINTF("16%s2", iomsg30); break; 00455 } 00456 put_lin(); 00457 io_mode_hys_od(r0); 00458 put_rn(); 00459 // P0_11 00460 r0 = LPC_IOCON->R_PIO0_11; 00461 PRINTF("R_%s11(dp4)", io_port_name0); 00462 put_spc(1); 00463 reg_print(SIZE_X, r0); 00464 put_spc(2); 00465 PRINTF( iomsg0 ); 00466 switch ( r0 & 0x7 ){ 00467 case 0: PRINTF(iomsg5); break; 00468 case 1: PRINTF(iomsg1); break; 00469 case 2: PRINTF("AD0"); break; 00470 case 3: PRINTF("32%s3", iomsg30); break; 00471 } 00472 put_lin(); 00473 io_mode_hys_od(r0); 00474 if ( r0 & 0x80 ){ PRINTF(", %s", iomsg6); 00475 } else { PRINTF(", %s", iomsg7); 00476 } 00477 put_rn(); 00478 } 00479 00480 // I/O Config IO1_x 00481 void io_config1(void){ 00482 uint32_t r0; 00483 00484 // P1_0 00485 r0 = LPC_IOCON->R_PIO1_0; 00486 PRINTF("R_%s0(dp9)", io_port_name1); 00487 put_spc(2); 00488 reg_print(SIZE_X, r0); 00489 put_spc(2); 00490 PRINTF( iomsg0 ); 00491 switch ( r0 & 0x7 ){ 00492 case 0: PRINTF(iomsg5); break; 00493 case 1: PRINTF(iomsg1); break; 00494 case 2: PRINTF("AD1"); break; 00495 case 3: PRINTF("32B1_CAP0"); break; 00496 } 00497 io_mode_hys_od(r0); 00498 if (r0 & 0x80){ PRINTF(", %s", iomsg6); 00499 } else { PRINTF(", %s", iomsg7); 00500 } 00501 put_rn(); 00502 // P1_1 00503 r0 = LPC_IOCON->R_PIO1_1; 00504 PRINTF("R_%s1(dp10)", io_port_name1); 00505 put_spc(1); 00506 reg_print(SIZE_X, r0); 00507 put_spc(2); 00508 PRINTF(iomsg0); 00509 switch (r0 & 0x7){ 00510 case 0: PRINTF(iomsg5); break; 00511 case 1: PRINTF(iomsg1); break; 00512 case 2: PRINTF("AD2"); break; 00513 case 3: PRINTF("32%s0", iomsg31); break; 00514 } 00515 io_mode_hys_od(r0); 00516 if (r0 & 0x80){ PRINTF(", %s", iomsg6); 00517 } else { PRINTF(", %s", iomsg7); 00518 } 00519 put_rn(); 00520 // P1_2 00521 r0 = LPC_IOCON->R_PIO1_2; 00522 PRINTF("R_%s2(dp11)", io_port_name1); 00523 put_spc(1); 00524 reg_print(SIZE_X, r0); 00525 put_spc(2); 00526 PRINTF(iomsg0); 00527 switch (r0 & 0x7){ 00528 case 0: PRINTF(iomsg5); break; 00529 case 1: PRINTF(iomsg1); break; 00530 case 2: PRINTF("AD3"); break; 00531 case 3: PRINTF("32%s1", iomsg31); break; 00532 } 00533 io_mode_hys_od( r0 ); 00534 if (r0 & 0x80){ PRINTF(", %s", iomsg6); 00535 } else { PRINTF(", %s", iomsg7); 00536 } 00537 put_rn(); 00538 // P1_3 00539 r0 = LPC_IOCON->SWDIO_PIO1_3; 00540 PRINTF("SWDIO_%s3(dp12)",io_port_name1); 00541 put_spc(1); 00542 reg_print(SIZE_X, r0); 00543 put_spc(3); 00544 PRINTF(iomsg0); 00545 switch (r0 & 0x7){ 00546 case 0: PRINTF("SWDIO"); break; 00547 case 1: PRINTF(iomsg1); break; 00548 case 2: PRINTF("AD4"); break; 00549 case 3: PRINTF("32%s2", iomsg31); break; 00550 } 00551 io_mode_hys_od(r0); 00552 if (r0 & 0x80){ PRINTF(", %s", iomsg6); 00553 } else { PRINTF(", %s", iomsg7); 00554 } 00555 put_rn(); 00556 // P1_4 00557 r0 = LPC_IOCON->PIO1_4; 00558 PRINTF("%s4(dp13)",io_port_name1); 00559 put_spc(3); 00560 reg_print(SIZE_X, r0); 00561 put_spc(2); 00562 PRINTF( iomsg0 ); 00563 switch (r0 & 0x7){ 00564 case 0: PRINTF(iomsg1); break; 00565 case 1: PRINTF("AD5"); break; 00566 case 2: PRINTF("32%s3", iomsg31); break; 00567 } 00568 put_lin(); 00569 io_mode_hys_od(r0); 00570 put_rn(); 00571 // P1_5 00572 r0 = LPC_IOCON->PIO1_5; 00573 PRINTF("%s5(dp14)",io_port_name1); 00574 put_spc(3); 00575 reg_print(SIZE_X, r0); 00576 put_spc(2); 00577 PRINTF(iomsg0); 00578 switch (r0 & 0x7){ 00579 case 0: PRINTF(iomsg1); break; 00580 case 1: PRINTF("RTS"); break; 00581 case 2: PRINTF("32B0_CAP0"); break; 00582 } 00583 put_lin(); 00584 io_mode_hys_od(r0); 00585 put_rn(); 00586 // P1_6 00587 r0 = LPC_IOCON->PIO1_6; 00588 PRINTF("%s6(dp15)", io_port_name1); 00589 put_spc(3); 00590 reg_print(SIZE_X, r0); 00591 put_spc(2); 00592 PRINTF(iomsg0); 00593 switch (r0 & 0x7){ 00594 case 0: PRINTF(iomsg1); break; 00595 case 1: PRINTF("RXD"); break; 00596 case 2: PRINTF( "32%s0", iomsg30 ); break; 00597 } 00598 put_lin(); 00599 io_mode_hys_od( r0 ); 00600 put_rn(); 00601 // P1_7 00602 r0 = LPC_IOCON->PIO1_7; 00603 PRINTF("%s7(dp16)", io_port_name1); 00604 put_spc(3); 00605 reg_print(SIZE_X, r0); 00606 put_spc(2); 00607 PRINTF(iomsg0); 00608 switch (r0 & 0x7){ 00609 case 0: PRINTF(iomsg1); break; 00610 case 1: PRINTF("TXD"); break; 00611 case 2: PRINTF("32%s1", iomsg30); break; 00612 } 00613 put_lin(); 00614 io_mode_hys_od(r0); 00615 put_rn(); 00616 // P1_8 00617 r0 = LPC_IOCON->PIO1_8; 00618 PRINTF("%s8(dp17)", io_port_name1); 00619 put_spc(3); 00620 reg_print(SIZE_X, r0); 00621 put_spc(2); 00622 PRINTF(iomsg0); 00623 switch (r0 & 0x7){ 00624 case 0: PRINTF(iomsg1); break; 00625 case 1: PRINTF("32%s1", iomsg30); break; 00626 } 00627 put_lin(); 00628 io_mode_hys_od(r0); 00629 put_rn(); 00630 // P1_9 00631 r0 = LPC_IOCON->PIO1_9; 00632 PRINTF("%s9(dp18)", io_port_name1); 00633 put_spc(3); 00634 reg_print(SIZE_X, r0); 00635 put_spc(2); 00636 PRINTF(iomsg0); 00637 switch (r0 & 0x7){ 00638 case 0: PRINTF(iomsg1); break; 00639 case 1: PRINTF("16%s0", iomsg31); break; 00640 case 2: PRINTF("MOSI1"); break; 00641 } 00642 put_lin(); 00643 io_mode_hys_od(r0); 00644 put_rn(); 00645 } 00646 #endif // USE_PORT 00647 00648 #if USE_REG_SPI_UART 00649 void spi_reg(int no){ 00650 uint32_t n, r0, r1 ,r2, r3, r4, r5, r6, r7, r8; 00651 00652 if (no == SPI_0){ 00653 n = 0; 00654 r0 = LPC_SSP0->CR1; 00655 r1 = LPC_SSP0->DR; 00656 r2 = LPC_SSP0->SR; 00657 r3 = LPC_SSP0->CPSR; 00658 r4 = LPC_SSP0->IMSC; 00659 r5 = LPC_SSP0->RIS; 00660 r6 = LPC_SSP0->MIS; 00661 r7 = LPC_SSP0->ICR; 00662 r8 = LPC_SSP0->CR0; 00663 } else if (no == SPI_1){ 00664 n = 1; 00665 r0 = LPC_SSP1->CR1; 00666 r1 = LPC_SSP1->DR; 00667 r2 = LPC_SSP1->SR; 00668 r3 = LPC_SSP1->CPSR; 00669 r4 = LPC_SSP1->IMSC; 00670 r5 = LPC_SSP1->RIS; 00671 r6 = LPC_SSP1->MIS; 00672 r7 = LPC_SSP1->ICR; 00673 r8 = LPC_SSP1->CR0; 00674 } else { 00675 return; 00676 } 00677 PRINTF("Show SSP%1d(SPI%1d) Registers", n, n); 00678 put_rn(); 00679 PRINTF("CR0"); 00680 PRINTF(imsg2); 00681 reg_print(SIZE8, r8); 00682 put_rn(); 00683 PRINTF("CR1"); 00684 PRINTF(imsg2); 00685 reg_print(SIZE8, r0); 00686 put_rn(); 00687 PRINTF("DR"); 00688 PRINTF(imsg4); 00689 reg_print(SIZE8, r1); 00690 put_rn(); 00691 PRINTF("SR"); 00692 PRINTF(imsg3); 00693 reg_print(SIZE8, r2); 00694 put_rn(); 00695 PRINTF("CPSR"); 00696 PRINTF(imsg7); 00697 reg_print(SIZE8, r3); 00698 put_rn(); 00699 PRINTF("IMSC"); 00700 PRINTF(imsg2); 00701 reg_print(SIZE8, r4); 00702 put_rn(); 00703 PRINTF("RIS"); 00704 PRINTF(imsg3); 00705 reg_print(SIZE8, r5); 00706 put_rn(); 00707 PRINTF("MIS"); 00708 PRINTF(imsg3); 00709 reg_print(SIZE8, r6); 00710 put_rn(); 00711 PRINTF("ICR"); 00712 PRINTF(imsg2); 00713 reg_print(SIZE8, r7); 00714 put_rn(); 00715 } 00716 00717 void uart_reg(void){ 00718 uint32_t r0,r1,r2,r3,r4,r5,r6; 00719 00720 // clear LCR[DLAB] to read registers 00721 LPC_UART->LCR &= ~(1 << 7); 00722 r0 = LPC_UART->RBR; 00723 r1 = LPC_UART->IER; 00724 r2 = LPC_UART->IIR; 00725 r3 = LPC_UART->TER; 00726 // set LCR[DLAB] to enable writing to divider registers 00727 LPC_UART->LCR |= (1 << 7); 00728 r4 = LPC_UART->DLL; 00729 r5 = LPC_UART->DLM; 00730 r6 = LPC_UART->FDR; 00731 // clear LCR[DLAB] 00732 LPC_UART->LCR &= ~(1 << 7); 00733 // Print each register 00734 PRINTF("Show UART Registers"); 00735 put_rn(); 00736 PRINTF("RBR"); 00737 PRINTF(imsg4); 00738 reg_print(SIZE8, r0); 00739 put_rn(); 00740 PRINTF("THR--Write only"); 00741 PRINTF(imsg4); 00742 put_rn(); 00743 PRINTF("DLL"); 00744 PRINTF(imsg2); 00745 reg_print(SIZE8, r4); 00746 put_rn(); 00747 PRINTF("DLM"); 00748 PRINTF(imsg2); 00749 reg_print(SIZE8, r5); 00750 put_rn(); 00751 PRINTF("IER"); 00752 PRINTF(imsg2); 00753 reg_print(SIZE8, r1); 00754 put_rn(); 00755 PRINTF("IIR"); 00756 PRINTF(imsg2); 00757 reg_print(SIZE8, r2); 00758 put_rn(); 00759 PRINTF("FCR--Write only"); 00760 PRINTF(imsg2); 00761 put_rn(); 00762 PRINTF("LCR,MCR,MSR,SCR,ACR--Not support"); 00763 put_rn(); 00764 PRINTF("FDR"); 00765 PRINTF(imsg2); 00766 reg_print(SIZE8, r6); 00767 put_rn(); 00768 PRINTF("TER"); 00769 PRINTF(imsg3); 00770 reg_print(SIZE8, r3); 00771 put_rn(); 00772 PRINTF("RS485CTRL,485ADRMATCH,485DLY--Not support"); 00773 put_rn(); 00774 } 00775 #endif //USE_REG_SPI_UART 00776 00777 #if USE_SYS 00778 void cpu_inf (void){ 00779 unsigned long m1, m2; 00780 00781 m1 = SCB->CPUID; 00782 m2 = (m1 >> 24); 00783 if (m2 == 0x41) { 00784 put_r(); 00785 PRINTF("CPU = ARM "); 00786 } else { 00787 put_r(); 00788 PRINTF("CPU = NOT ARM "); 00789 } 00790 m2 = (m1 >> 4) & 0xfff; 00791 if (m2 == 0xc23) { 00792 PRINTF("Cortex-M3"); 00793 put_rn(); 00794 } else if (m2 == 0xc20){ 00795 PRINTF("Cortex-M0"); 00796 put_rn(); 00797 } else { 00798 PRINTF("NOT Cortex-M3,M0"); 00799 put_rn(); 00800 } 00801 m2 = (m1 >> 20) & 0x0f; 00802 PRINTF("Variant:%x", (int)m2); 00803 put_rn(); 00804 m2 = m1 & 0x7; 00805 PRINTF("Revision:%x", (int)m2); 00806 put_rn(); 00807 } 00808 00809 // Calculate CPU System Clock Frequency /refrence: system_LPCxx.c 00810 static const char *const fmsg0 = "Internal RC Oscillator"; 00811 static const char *const fmsg1 = "Xtal Osc Clock"; 00812 static const char *const fmsg2 = "Watch dog Osc Clock"; 00813 static const char *const fmsg3 = "with PLL"; 00814 static const char *const fmsg4 = "System Clock ="; 00815 static const char *const fmsg5 = "PLL Post divider ratio ="; 00816 static const char *const fmsg6 = "feedback devider ="; 00817 static const char *const fmsg7 = "NO Clock ?!"; 00818 00819 void get_freq_w_print (void){ // Get Core Clock Frequency 00820 uint32_t wdt_osc = 0, pll_fct0 = 0, pll_fct1 = 0; 00821 00822 // Determine clock frequency according to clock register values 00823 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { 00824 case 0: wdt_osc = 400000; break; 00825 case 1: wdt_osc = 500000; break; 00826 case 2: wdt_osc = 800000; break; 00827 case 3: wdt_osc = 1100000; break; 00828 case 4: wdt_osc = 1400000; break; 00829 case 5: wdt_osc = 1600000; break; 00830 case 6: wdt_osc = 1800000; break; 00831 case 7: wdt_osc = 2000000; break; 00832 case 8: wdt_osc = 2200000; break; 00833 case 9: wdt_osc = 2400000; break; 00834 case 10: wdt_osc = 2600000; break; 00835 case 11: wdt_osc = 2700000; break; 00836 case 12: wdt_osc = 2900000; break; 00837 case 13: wdt_osc = 3100000; break; 00838 case 14: wdt_osc = 3200000; break; 00839 case 15: wdt_osc = 3400000; break; 00840 } 00841 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; 00842 put_r(); 00843 switch (LPC_SYSCON->MAINCLKSEL & 0x03) { 00844 case 0: // Internal RC oscillator 00845 SystemCoreClock = __IRC_OSC_CLK; 00846 PRINTF("%s = %dHz", fmsg0, SystemCoreClock); 00847 break; 00848 case 1: // Input Clock to System PLL 00849 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { 00850 case 0: // Internal RC oscillator 00851 SystemCoreClock = __IRC_OSC_CLK; 00852 PRINTF("%s = %dHz", fmsg0, SystemCoreClock); 00853 break; 00854 case 1: // System oscillator 00855 SystemCoreClock = __SYS_OSC_CLK; 00856 PRINTF("%s = %dHz", fmsg1, SystemCoreClock ); 00857 break; 00858 case 2: // WDT Oscillator 00859 SystemCoreClock = wdt_osc; 00860 PRINTF("%s = %dHz", fmsg2, wdt_osc ); 00861 break; 00862 case 3: // Reserved 00863 SystemCoreClock = 0; 00864 PRINTF(fmsg7); 00865 break; 00866 } 00867 break; 00868 case 2: // WDT Oscillator 00869 SystemCoreClock = wdt_osc; 00870 PRINTF("%s = %dHz", fmsg2, wdt_osc ); 00871 break; 00872 case 3: // System PLL Clock Out 00873 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { 00874 case 0: // Internal RC oscillator 00875 if (LPC_SYSCON->SYSPLLCTRL & 0x180) { 00876 SystemCoreClock = __IRC_OSC_CLK; 00877 PRINTF("%s = %dHz", fmsg0, SystemCoreClock); 00878 } else { 00879 pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1; 00880 pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL; 00881 SystemCoreClock = __IRC_OSC_CLK * pll_fct0; 00882 PRINTF("Use Internal RC = %dHz", (int)__IRC_OSC_CLK); 00883 put_rn(); 00884 PRINTF("%s %s = %dHz", fmsg0, fmsg3, SystemCoreClock); 00885 put_rn(); 00886 PRINTF("%s %d, %s %d", fmsg5, pll_fct1, fmsg6, pll_fct0); 00887 } 00888 break; 00889 case 1: // System oscillator 00890 if (LPC_SYSCON->SYSPLLCTRL & 0x180) { 00891 SystemCoreClock = __SYS_OSC_CLK; 00892 PRINTF("%s = %dHz", fmsg1, SystemCoreClock ); 00893 } else { 00894 pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1; 00895 pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL; 00896 SystemCoreClock = __SYS_OSC_CLK * pll_fct0; 00897 PRINTF("Use XTAL = %dHz", (int)__XTAL); 00898 put_rn(); 00899 PRINTF("%s %s = %dHz", fmsg1, fmsg3, SystemCoreClock); 00900 put_rn(); 00901 PRINTF("%s %d, %s %d", fmsg5, pll_fct1, fmsg6, pll_fct0); 00902 } 00903 break; 00904 case 2: // WDT Oscillator 00905 if (LPC_SYSCON->SYSPLLCTRL & 0x180) { 00906 SystemCoreClock = wdt_osc; 00907 PRINTF("%s = %dHz", fmsg2, wdt_osc ); 00908 } else { 00909 pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1; 00910 pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL; 00911 SystemCoreClock = wdt_osc * pll_fct0; 00912 PRINTF("Use WDT OSC = %dHz", wdt_osc); 00913 put_rn(); 00914 PRINTF("%s %s = %dHz", fmsg2, fmsg3, SystemCoreClock); 00915 put_rn(); 00916 PRINTF("%s %d, %s %d", fmsg5, pll_fct1, fmsg6, pll_fct0); 00917 } 00918 break; 00919 case 3: // Reserved 00920 SystemCoreClock = 0; 00921 PRINTF("fmsg7"); 00922 break; 00923 } 00924 break; 00925 } 00926 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; 00927 put_rn(); 00928 PRINTF("%s %dHz", fmsg4, SystemCoreClock); 00929 put_rn(); 00930 } 00931 #endif //USE_SYS 00932 00933 void get_freq (void){ // Get Core Clock Frequency 00934 uint32_t wdt_osc = 0, pll_fct0 = 0, pll_fct1 = 0; 00935 00936 // Determine clock frequency according to clock register values 00937 switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { 00938 case 0: wdt_osc = 400000; break; 00939 case 1: wdt_osc = 500000; break; 00940 case 2: wdt_osc = 800000; break; 00941 case 3: wdt_osc = 1100000; break; 00942 case 4: wdt_osc = 1400000; break; 00943 case 5: wdt_osc = 1600000; break; 00944 case 6: wdt_osc = 1800000; break; 00945 case 7: wdt_osc = 2000000; break; 00946 case 8: wdt_osc = 2200000; break; 00947 case 9: wdt_osc = 2400000; break; 00948 case 10: wdt_osc = 2600000; break; 00949 case 11: wdt_osc = 2700000; break; 00950 case 12: wdt_osc = 2900000; break; 00951 case 13: wdt_osc = 3100000; break; 00952 case 14: wdt_osc = 3200000; break; 00953 case 15: wdt_osc = 3400000; break; 00954 } 00955 wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; 00956 switch (LPC_SYSCON->MAINCLKSEL & 0x03) { 00957 case 0: // Internal RC oscillator 00958 SystemCoreClock = __IRC_OSC_CLK; 00959 break; 00960 case 1: // Input Clock to System PLL 00961 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { 00962 case 0: // Internal RC oscillator 00963 SystemCoreClock = __IRC_OSC_CLK; 00964 break; 00965 case 1: // System oscillator 00966 SystemCoreClock = __SYS_OSC_CLK; 00967 break; 00968 case 2: // WDT Oscillator 00969 SystemCoreClock = wdt_osc; 00970 break; 00971 case 3: // Reserved 00972 SystemCoreClock = 0; 00973 break; 00974 } 00975 break; 00976 case 2: // WDT Oscillator 00977 SystemCoreClock = wdt_osc; 00978 break; 00979 case 3: // System PLL Clock Out 00980 switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { 00981 case 0: // Internal RC oscillator 00982 if (LPC_SYSCON->SYSPLLCTRL & 0x180) { 00983 SystemCoreClock = __IRC_OSC_CLK; 00984 } else { 00985 pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1; 00986 pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL; 00987 SystemCoreClock = __IRC_OSC_CLK * pll_fct0; 00988 } 00989 break; 00990 case 1: // System oscillator 00991 if (LPC_SYSCON->SYSPLLCTRL & 0x180) { 00992 SystemCoreClock = __SYS_OSC_CLK; 00993 } else { 00994 pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1; 00995 pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL; 00996 SystemCoreClock = __SYS_OSC_CLK * pll_fct0; 00997 } 00998 break; 00999 case 2: // WDT Oscillator 01000 if (LPC_SYSCON->SYSPLLCTRL & 0x180) { 01001 SystemCoreClock = wdt_osc; 01002 } else { 01003 pll_fct0 = (LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1; 01004 pll_fct1 = (LPC_SYSCON->SYSPLLCTRL & 0x060) >> 5UL; 01005 SystemCoreClock = wdt_osc * pll_fct0; 01006 } 01007 break; 01008 case 3: // Reserved 01009 SystemCoreClock = 0; 01010 break; 01011 } 01012 break; 01013 } 01014 SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; 01015 } 01016 01017 #if USE_REG_I2C 01018 void i2c_io_reg (void){ 01019 uint32_t r0; 01020 01021 PRINTF("<Show IO Pin>"); 01022 put_rn(); 01023 // P0_4 01024 r0 = LPC_IOCON->PIO0_4; 01025 reg_print(SIZE_X, r0); 01026 put_spc(2); 01027 PRINTF("%s4(dp27)",io_port_name0); 01028 put_spc(2); 01029 PRINTF(iomsg0); 01030 switch (r0 & 0x7){ 01031 case 0: 01032 PRINTF(iomsg1); 01033 break; 01034 case 1: 01035 PRINTF("SCL"); 01036 break; 01037 } 01038 put_lin(); 01039 switch (( r0 >> 8 ) & 0x3){ 01040 case 0: 01041 PRINTF(iomsg4); 01042 break; 01043 case 1: 01044 PRINTF(iomsg1); 01045 break; 01046 case 2: 01047 PRINTF("Fast md"); 01048 break; 01049 case 3: 01050 PRINTF(iomsg2); 01051 break; 01052 } 01053 put_rn(); 01054 // P0_5 01055 r0 = LPC_IOCON->PIO0_5; 01056 reg_print( SIZE_X, r0 ); 01057 put_spc(2); 01058 PRINTF("%s5(dp5)",io_port_name0); 01059 put_spc(3); 01060 PRINTF(iomsg0); 01061 switch (r0 & 0x7){ 01062 case 0: 01063 PRINTF(iomsg1); 01064 break; 01065 case 1: 01066 PRINTF("SDA"); 01067 break; 01068 } 01069 put_lin(); 01070 switch ((r0 >> 8 ) & 0x3){ 01071 case 0: 01072 PRINTF(iomsg4); 01073 break; 01074 case 1: 01075 PRINTF(iomsg1); 01076 break; 01077 case 2: 01078 PRINTF("Fast md"); 01079 break; 01080 case 3: 01081 PRINTF(iomsg2); 01082 break; 01083 } 01084 put_rn(); 01085 } 01086 01087 void i2c_reg (void){ 01088 uint32_t r0,r1,r2,r3,r4,r5,r6,r7; 01089 01090 r0 = LPC_I2C->CONSET; 01091 r1 = LPC_I2C->STAT; 01092 r2 = LPC_I2C->DAT; 01093 r3 = LPC_I2C->SCLH; 01094 r4 = LPC_I2C->SCLL; 01095 r5 = LPC_I2C->CONCLR; 01096 r6 = LPC_I2C->MMCTRL; 01097 r7 = LPC_I2C->DATA_BUFFER; 01098 01099 PRINTF("<Show I2C Registers>"); 01100 put_rn(); 01101 reg_print(SIZE8, r0); 01102 put_spc(2); 01103 PRINTF("CONSET"); 01104 PRINTF(imsg2); 01105 put_rn(); 01106 reg_print(SIZE8, r1); 01107 put_spc(2); 01108 PRINTF("STAT"); 01109 PRINTF(imsg3); 01110 put_rn(); 01111 reg_print(SIZE8, r2); 01112 put_spc(2); 01113 PRINTF("DAT"); 01114 PRINTF(imsg4); 01115 put_rn(); 01116 put_spc(2); 01117 PRINTF("ADR0--Not support"); 01118 put_rn(); 01119 reg_print(SIZE8, r3); 01120 put_spc(2); 01121 PRINTF("SCLH"); 01122 PRINTF(imsg2); 01123 put_rn(); 01124 reg_print(SIZE8, r4); 01125 put_spc(2); 01126 PRINTF("SCLL"); 01127 PRINTF(imsg2); 01128 put_rn(); 01129 reg_print(SIZE8, r5); 01130 put_spc(2); 01131 PRINTF("CONCLR"); 01132 PRINTF(imsg2); 01133 put_rn(); 01134 reg_print(SIZE8, r6); 01135 put_spc(2); 01136 PRINTF("MMCTRL"); 01137 PRINTF(imsg2); 01138 put_rn(); 01139 put_spc(2); 01140 PRINTF("ADR1,2,3--Not support"); 01141 put_rn(); 01142 reg_print(SIZE8, r7); 01143 put_spc(2); 01144 PRINTF("DATA_BUFFER"); 01145 PRINTF(imsg7); 01146 put_rn(); 01147 put_spc(2); 01148 PRINTF("MASK0,1,2,3--Not support"); 01149 put_rn(); 01150 } 01151 01152 void i2c_freq (void){ 01153 uint32_t r0,r1; 01154 01155 r0 = LPC_I2C->SCLH; 01156 r1 = LPC_I2C->SCLL; 01157 get_freq(); 01158 PRINTF("<I2C Status>"); 01159 put_rn(); 01160 PRINTF("Freq. = I2CPCLK/(SCLH+SCLL) = %d/(%d+%d) = %d Hz", 01161 SystemCoreClock, r0, r1, SystemCoreClock/(r0+r1)); 01162 put_rn(); 01163 r0 = LPC_I2C->CONSET; 01164 PRINTF("I2C I/F "); 01165 if ( r0 & 0x40 ) { 01166 PRINTF("Enabled"); 01167 } else { 01168 PRINTF("disabled"); 01169 } 01170 put_rn(); 01171 } 01172 #endif 01173 01174 #if USE_MEM 01175 // Range check for Memory dump 01176 static void check_range (MEMO * mem){ 01177 uint8_t i; 01178 uint32_t m; 01179 01180 mem->mflg = ERR_NOTHING; 01181 for (i = 0 ; i < 5 ; i++) { 01182 if (mem->mstr >= mem_range[i][0]) { 01183 if (mem->mstr < mem_range[i][1]) { 01184 m = mem->mstr + mem->msiz; 01185 if (m < mem_range[i][1]) { 01186 return; // no modification 01187 } else { 01188 m = mem_range[i][1]; 01189 mem->msiz = m - mem->mstr + 1; 01190 mem->mflg = ERR_MODIFY_SIZ; 01191 return; // modified size 01192 } 01193 } 01194 } 01195 } 01196 mem->mflg = ERR_OUT_OF_RANGE; 01197 mem->mstr = 0; 01198 mem->msiz = 0; 01199 return ; 01200 } 01201 01202 // Memory dump error massage 01203 void error_print (unsigned char flg){ 01204 switch (flg) { 01205 case ERR_MODIFY_SIZ : 01206 put_r(); 01207 PRINTF("Reach to out of range "); 01208 put_rn(); 01209 break; 01210 case ERR_OUT_OF_RANGE : 01211 put_r(); 01212 PRINTF("Not in a memory area "); 01213 put_rn(); 01214 break; 01215 case ERR_NOTHING : 01216 default : 01217 ; 01218 } 01219 } 01220 01221 // Print memory contents 01222 void put_dump (const unsigned char *buff, unsigned long ofs, int cnt){ 01223 int n; 01224 01225 PRINTF("%08lX ", ofs); 01226 for(n = 0; n < cnt; n++) { PRINTF(" %02X", buff[n]); } 01227 PUTC(' '); 01228 for(n = 0; n < cnt; n++) { 01229 if ((buff[n] < 0x20)||(buff[n] >= 0x7F)) { PUTC('.'); 01230 } else { PUTC(buff[n]); } 01231 } 01232 put_rn(); 01233 } 01234 01235 // dump memory with error check 01236 void dump_w_err_ckeck (char **ptr, MEMO * mem){ 01237 check_range (mem); 01238 for (*ptr=(char*)mem->mstr; mem->msiz >= 16; *ptr += 16, mem->msiz -= 16) { 01239 put_r(); 01240 put_dump((unsigned char*)*ptr, (unsigned int)*ptr, 16); 01241 } 01242 if (mem->msiz) { put_dump((unsigned char*)*ptr, (unsigned int)*ptr, mem->msiz); 01243 } 01244 error_print(mem->mflg); 01245 } 01246 01247 static void mem_inf (char *ptr){ 01248 put_r(); 01249 PRINTF("Mem. Mode d <address> [<count>], s, <ret> or f, q, ?"); 01250 put_rn(); 01251 mem.mstr = mem_range[0][0]; // default start address = Flash 01252 mem.msiz =256; 01253 mem.mold = 0; 01254 mem.mtmp = 0; 01255 mem.mflg = 0; 01256 for (; mem.mflg != 0xff;) { 01257 PRINTF("m>"); 01258 ptr = linebuf; 01259 get_line(ptr, buf_size); 01260 put_r(); 01261 switch(*ptr++){ 01262 case 'd' : // d <address> [<count>] - Dump memory 01263 mem.mtmp = mem.mstr; 01264 if (!xatoi(&ptr, &mem.mstr)) { 01265 mem.mstr = mem.mtmp; 01266 } 01267 if (!xatoi(&ptr, &mem.msiz)) { 01268 mem.msiz = 256; 01269 } 01270 mem.mtmp = mem.msiz; 01271 dump_w_err_ckeck(&ptr, &mem); 01272 mem.mold = mem.mstr; 01273 mem.mstr += mem.mtmp; 01274 break; 01275 case 'f' : // next 01276 case 'n' : 01277 case 0x0d : 01278 mem.msiz = 256; 01279 mem.mtmp = mem.msiz; 01280 dump_w_err_ckeck(&ptr, &mem); 01281 mem.mold = mem.mstr; 01282 mem.mstr += 256; 01283 break; 01284 case 'q' : // quit 01285 mem.mflg = 0xff; 01286 break; 01287 case 'b' : // Back to more 01288 if (mem.mold == 0){ 01289 ; 01290 } else { 01291 mem.mold -= 256; 01292 } 01293 case 'k' : // keep previous address 01294 mem.mstr = mem.mold; 01295 mem.msiz = 256; 01296 mem.mtmp = mem.msiz; 01297 dump_w_err_ckeck(&ptr, &mem); 01298 mem.mstr += 256; 01299 break; 01300 case 'a' : // start RAM top 01301 mem.mstr = mem_range[1][0]; 01302 mem.msiz =256; 01303 mem.mold = 0; 01304 mem.mtmp = 0; 01305 mem.mflg = 0; 01306 dump_w_err_ckeck(&ptr, &mem); 01307 mem.mstr += 256; 01308 break; 01309 case 'o' : // start ROM top 01310 mem.mstr = mem_range[0][0]; 01311 mem.msiz =256; 01312 mem.mold = 0; 01313 mem.mtmp = 0; 01314 mem.mflg = 0; 01315 dump_w_err_ckeck(&ptr, &mem); 01316 mem.mstr += 256; 01317 break; 01318 case 's' : 01319 PRINTF("Memory Configuration"); 01320 put_rn(); 01321 PRINTF("%s0x%08lx to 0x%08lx ", rmsg0, mem_range[0][0], mem_range[0][1]); 01322 put_rn(); 01323 PRINTF("%s0x%08lx to 0x%08lx ", rmsg1, mem_range[1][0], mem_range[1][1]); 01324 put_rn(); 01325 PRINTF("%s0x%08lx to 0x%08lx ", rmsg2, mem_range[2][0], mem_range[2][1]); 01326 put_rn(); 01327 PRINTF("%s0x%08lx to 0x%08lx ", rmsg3, mem_range[3][0], mem_range[3][1]); 01328 put_rn(); 01329 PRINTF("%s0x%08lx to 0x%08lx ", rmsg4, mem_range[4][0], mem_range[4][1]); 01330 put_rn(); 01331 break; 01332 case '?' : 01333 PRINTF("d <address> [<count>] - Dump memory"); 01334 put_rn(); 01335 PRINTF("s - Show memory structure "); 01336 put_rn(); 01337 PRINTF("o - Dump memory / start from ROM top"); 01338 put_rn(); 01339 PRINTF("a - Dump memory / start from RAM top"); 01340 put_rn(); 01341 PRINTF("k - Dump memory / keep same 256bytes"); 01342 put_rn(); 01343 PRINTF("b - Dump memory / before 256bytes"); 01344 put_rn(); 01345 PRINTF("<RET> or f, n - Dump memory / next 256bytes"); 01346 put_rn(); 01347 PRINTF("q - Exit memory mode"); 01348 put_rn(); 01349 break; 01350 default: 01351 PUTC('?'); 01352 put_rn(); 01353 } 01354 } 01355 PRINTF("Return to Normal Mode"); 01356 } 01357 #endif //USE_MEM 01358 01359 #if USE_EEP 01360 static void mem_chk_msg (char mflg){ 01361 switch (mflg) { 01362 case ERR_MODIFY_SIZ : 01363 PRINTF(" Reached out of range"); 01364 put_rn(); 01365 break; 01366 case ERR_OUT_OF_RANGE : 01367 PRINTF(" Not in a memory area"); 01368 put_rn(); 01369 break; 01370 case ERR_NOTHING : 01371 default : 01372 ; 01373 } 01374 } 01375 01376 void put_eep_dump ( 01377 uint32_t addr, // Heading address value 01378 uint8_t len // Number of items to be dumped 01379 ){ 01380 uint32_t i; 01381 uint8_t eep[16]; 01382 //????????????????????????????????????????????????????????????????????????? 01383 #warning "?????" 01384 PRINTF("%08x ", (int)addr); // address 01385 for (i = 0; i < len; i++) { // Hexdecimal dump 01386 eep[i] = xat24c1024.read(addr++); 01387 PRINTF(" %02x", eep[i]); 01388 } 01389 PUTC(' '); 01390 for (i = 0; i < len; i++){ // ASCII dump 01391 PUTC((eep[i] >= ' ' && eep[i] <= '~') ? eep[i] : '.'); 01392 } 01393 put_rn(); 01394 } 01395 01396 static void check_eeprange (MEMO * eepmem){ 01397 uint32_t m; 01398 01399 m = sizeof(eepmem_range) / sizeof(*eepmem_range); 01400 eepmem->mflg = ERR_NOTHING; 01401 if (eepmem->mstr >= eepmem_range[0]){ 01402 if (eepmem->mstr < eepmem_range[1]){ 01403 m = eepmem->mstr + eepmem->msiz; 01404 if (m < eepmem_range[1]){ 01405 return; // no modification 01406 } else { 01407 m = eepmem_range[1]; 01408 eepmem->msiz = m - eepmem->mstr + 1; 01409 eepmem->mflg = ERR_MODIFY_SIZ; 01410 return; // modified size 01411 } 01412 } 01413 } 01414 eepmem->mflg = ERR_OUT_OF_RANGE; 01415 eepmem->mstr = 0; 01416 eepmem->msiz = 0; 01417 return ; 01418 } 01419 01420 static void eepmem_inf (char *ptr){ 01421 uint8_t c, dt; 01422 unsigned long p1, p2, p3; 01423 01424 put_r(); 01425 PRINTF("Enter EEPROM 1) d <address> 256bytes, 2) s, 3) <ret>, 4) q 5) ?"); 01426 put_rn(); 01427 eepmem.mstr = eepmem_range[0]; // start head of table 01428 eepmem.msiz =256; 01429 eepmem.mold = 0; 01430 eepmem.mtmp = 0; 01431 eepmem.mflg = 0; 01432 eepmem.mbhw = DW_CHAR; 01433 for (; eepmem.mflg != 0xff;) { 01434 PRINTF("e>"); 01435 ptr = linebuf; 01436 get_line(ptr, buf_size); 01437 put_r(); 01438 switch(*ptr++){ 01439 case 'd' : // d <address> - Dump memory 01440 eepmem.mtmp = eepmem.mstr; // save defult start addres 01441 if (!xatoi(&ptr, &eepmem.mstr)){ 01442 eepmem.mstr = eepmem.mtmp; // recover defult address 01443 } 01444 eepmem.msiz = 256; 01445 eepmem.msiz /= eepmem.mbhw; 01446 eepmem.mtmp = eepmem.msiz * eepmem.mbhw; 01447 check_eeprange (&eepmem); 01448 for (ptr=(char*)eepmem.mstr; 01449 eepmem.msiz >= 16/eepmem.mbhw; 01450 ptr += 16, eepmem.msiz -= 16/eepmem.mbhw) 01451 { 01452 put_eep_dump((UINT)ptr, 16/eepmem.mbhw); 01453 } 01454 if (eepmem.msiz){ 01455 put_eep_dump((UINT)ptr, eepmem.msiz); 01456 } 01457 mem_chk_msg( eepmem.mflg ); 01458 eepmem.mold = eepmem.mstr; 01459 eepmem.mstr += eepmem.mtmp; 01460 break; 01461 case 'f' : // next 01462 case 'n' : 01463 case 0x0d : // CR 01464 eepmem.msiz = 256/eepmem.mbhw; 01465 eepmem.mtmp = eepmem.msiz; 01466 check_eeprange (&eepmem); 01467 for (ptr=(char*)eepmem.mstr; 01468 eepmem.msiz >= 16/eepmem.mbhw; 01469 ptr += 16, eepmem.msiz -= 16/eepmem.mbhw) 01470 { 01471 put_eep_dump((UINT)ptr, 16/eepmem.mbhw); 01472 } 01473 mem_chk_msg(eepmem.mflg); 01474 eepmem.mold = eepmem.mstr; 01475 eepmem.mstr += 256; 01476 break; 01477 case 'q' : // quit 01478 eepmem.mflg = 0xff; 01479 break; 01480 case 'b' : // Back to more 01481 if (eepmem.mold == 0){ 01482 ; 01483 } else { 01484 eepmem.mold -= 256; 01485 } 01486 case 'k' : // keep previous address 01487 eepmem.mstr = eepmem.mold; 01488 eepmem.msiz = 256/eepmem.mbhw; 01489 eepmem.mtmp = eepmem.msiz; 01490 check_eeprange (&eepmem); 01491 for (ptr=(char*)eepmem.mstr; eepmem.msiz >= 16/eepmem.mbhw; ptr += 16, 01492 eepmem.msiz -= 16/eepmem.mbhw){ 01493 put_eep_dump((UINT)ptr, 16/eepmem.mbhw); 01494 } 01495 mem_chk_msg(eepmem.mflg); 01496 eepmem.mstr += 256; 01497 break; 01498 case 'e' : // e <address> [<value> ...] - Edit memory 01499 ptr = linebuf; 01500 get_line(ptr, buf_size); 01501 p3 = DW_CHAR; 01502 if (!xatoi(&ptr, &p1)){ 01503 PRINTF("? ->e <address> [<value> ...]"); 01504 put_rn(); 01505 break; // Get start address 01506 } 01507 if (xatoi(&ptr, &p2)) { // 2nd parameter is given 01508 do { 01509 xat24c1024.write((uint16_t)p1, (uint8_t)p2); 01510 ThisThread::sleep_for(10ms); 01511 dt = xat24c1024.read((uint16_t)p1); 01512 if (dt != (uint8_t)p2){ 01513 PRINTF("?\r\n"); 01514 } 01515 p1 += p3; 01516 } while (xatoi(&ptr, &p2)); // Get next value 01517 break; 01518 } 01519 for (;;) {// 2nd parameter is not given (interactive mode) 01520 PRINTF("%08x 0x%02x-", (int)p1, *(BYTE*)p1); 01521 ptr = linebuf; 01522 get_line(ptr, buf_size); 01523 if (*ptr == '.'){ break;} 01524 if (*ptr == 0x1b){ break;} 01525 if ((BYTE)*ptr >= ' ') { 01526 if (!xatoi(&ptr, &p2)){ continue;} 01527 xat24c1024.write((uint16_t)p1, (uint8_t)p2); 01528 ThisThread::sleep_for(10ms); 01529 dt = xat24c1024.read((uint16_t)p1); 01530 if (dt != (uint8_t)p2){ 01531 PRINTF("?\r\n"); 01532 } 01533 } 01534 p1 += p3; 01535 } 01536 break; 01537 case 's' : 01538 PRINTF("AT24C1024B"); 01539 put_rn(); 01540 //????????????????????????????????????????????????????????????????????????? 01541 #warning "?????" 01542 PRINTF("EEPROM 0x%08lx to 0x%08lx", (int)eepmem_range[0], (int)eepmem_range[1]); 01543 put_rn(); 01544 break; 01545 case '?' : 01546 PRINTF("d <address> -Dump memory"); 01547 PRINTF(" (e.g. >d 0x10f00<RET>)"); 01548 put_rn(); 01549 PRINTF("e <address> [<value> ...] - Edit memory"); 01550 put_rn(); 01551 PRINTF("s -Show memory structure"); 01552 put_rn(); 01553 PRINTF("<RET>-Dump memory, next 256 bytes (also 'f','n')"); 01554 put_rn(); 01555 PRINTF("k -Dump memory, same as before 256 bytes ('b' -256)"); 01556 put_rn(); 01557 PRINTF("q -Exit EEPROM mode" ); 01558 put_rn(); 01559 break; 01560 default: 01561 PUTC('?'); 01562 put_rn(); 01563 } 01564 } 01565 PRINTF("Return to Normal Mode"); 01566 } 01567 #endif 01568 01569 //----------------------------------------------------------------------------- 01570 // Monitor Main Program 01571 //----------------------------------------------------------------------------- 01572 int mon_hw (void) { 01573 char *ptr; 01574 01575 put_r(); 01576 PRINTF("%s [Help:'?' key]", mon_msg_hw); 01577 put_rn(); 01578 #if USE_SYS 01579 get_freq(); 01580 #endif //USE_SYS 01581 for (;;) { 01582 put_r(); 01583 PUTC('>'); 01584 ptr = linebuf; 01585 get_line(ptr, buf_size); 01586 switch (*ptr++) { 01587 #if USE_MEM 01588 //--------------------------------------------------------------------------------- 01589 // Memory 01590 //--------------------------------------------------------------------------------- 01591 case 'm' : 01592 mem_inf(ptr); 01593 put_rn(); 01594 break; 01595 #endif // USE_MEM 01596 #if USE_EEP 01597 //--------------------------------------------------------------------------------- 01598 // EEPROM Memory 01599 //--------------------------------------------------------------------------------- 01600 /* EEPROM Memory */ 01601 case 'e' : 01602 eepmem_inf(ptr); 01603 put_rn(); 01604 break; 01605 #endif // USE_EEP 01606 #if USE_REG_SPI_UART 01607 //-------------------------------------------------------------------------------------- 01608 // Register 01609 //-------------------------------------------------------------------------------------- 01610 case 'r' : 01611 uint8_t r_flg; 01612 put_r(); 01613 PRINTF("Reg. Mode p,u,i,s,t,a,d,l,w,c & ?"); 01614 put_rn(); 01615 r_flg = 0; 01616 for (; r_flg != 0xff;) { 01617 PRINTF("r>"); 01618 ptr = linebuf; 01619 get_line(ptr, sizeof(linebuf)); 01620 put_r(); 01621 switch(*ptr++){ 01622 case 'p' : 01623 switch(*ptr++){ 01624 case '0' : 01625 io_config0(); 01626 break; 01627 case '1' : 01628 io_config1(); 01629 break; 01630 case '*' : 01631 io_config0(); 01632 put_rn(); 01633 io_config1(); 01634 break; 01635 case '?' : 01636 default: 01637 PRINTF("Enter p0,p1 and p* for all"); 01638 put_rn(); 01639 } 01640 break;; 01641 case 'u' : 01642 uart_reg(); 01643 break; 01644 //case 'i' : 01645 // i2c_reg(); 01646 // break; 01647 case 's' : 01648 switch(*ptr++){ 01649 case '0' : 01650 spi_reg(SPI_0); 01651 break; 01652 case '1' : 01653 spi_reg(SPI_1); 01654 break; 01655 case '*' : 01656 spi_reg(SPI_0); 01657 put_rn(); 01658 spi_reg( SPI_1 ); 01659 break; 01660 case '?' : 01661 default: 01662 PRINTF("Enter s0,s1 and s* for all"); 01663 put_rn(); 01664 } 01665 break; 01666 case 't' : // 01667 not_yet_impliment(); 01668 break; 01669 case 'a' : // 01670 not_yet_impliment(); 01671 break; 01672 case 'd' : // 01673 not_yet_impliment(); 01674 break; 01675 case 'w' : // 01676 not_yet_impliment(); 01677 break; 01678 case 'l' : // 01679 not_yet_impliment(); 01680 break; 01681 case 'c' : // 01682 not_yet_impliment(); 01683 break; 01684 case 'x' : // 01685 not_yet_impliment(); 01686 break; 01687 case 'y' : // 01688 not_yet_impliment(); 01689 break; 01690 case '?' : 01691 PRINTF("p - I/O Pin Config"); 01692 put_rn(); 01693 PRINTF("u - UART"); 01694 put_rn(); 01695 PRINTF("i - I2C -> separate command 'i'"); 01696 put_rn(); 01697 PRINTF("s - SPI"); 01698 put_rn(); 01699 PRINTF("t - TIMER"); 01700 put_rn(); 01701 PRINTF("a - ADC"); 01702 put_rn(); 01703 PRINTF("d - DAC"); 01704 put_rn(); 01705 PRINTF("l - LDC"); 01706 put_rn(); 01707 PRINTF("w - WWDG"); 01708 put_rn(); 01709 PRINTF("c - COMP"); 01710 put_rn(); 01711 break; 01712 case 'q' : // quit 01713 r_flg = 0xff; 01714 break; 01715 default: 01716 PUTC('?'); 01717 put_rn(); 01718 } 01719 } 01720 PRINTF("Return to Normal Mode"); 01721 put_rn(); 01722 break; 01723 #endif // USE_REG_SPI_UART 01724 #if USE_PORT 01725 //--------------------------------------------------------------------------------- 01726 // Port configration 01727 //--------------------------------------------------------------------------------- 01728 case 'p' : // 01729 put_r(); 01730 switch(*ptr++){ 01731 case '0' : 01732 io_config0(); 01733 break; 01734 case '1' : 01735 io_config1(); 01736 break; 01737 case '*' : 01738 io_config0(); 01739 put_rn(); 01740 io_config1(); 01741 break; 01742 case '?' : 01743 default: 01744 PRINTF("Enter p0,p1 and p* for all"); 01745 put_rn(); 01746 } 01747 break; 01748 #endif // USE_PORT 01749 #if USE_REG_I2C 01750 //--------------------------------------------------------------------------------- 01751 // I2C register 01752 //--------------------------------------------------------------------------------- 01753 case 'i' : // 01754 put_r(); 01755 i2c_io_reg(); 01756 i2c_reg(); 01757 i2c_freq(); 01758 break; 01759 #endif // USE_REG_I2C 01760 #if USE_SYS 01761 //--------------------------------------------------------------------------------- 01762 // System 01763 //--------------------------------------------------------------------------------- 01764 case 's' : // System related information 01765 switch (*ptr++) { 01766 case 'f' : // sc - show system clock frequency 01767 get_freq_w_print(); 01768 break; 01769 case 'c' : // sc - show system CPU information 01770 cpu_inf(); 01771 break; 01772 case '?' : 01773 default: 01774 put_r(); 01775 PRINTF("sc - System CPU information"); 01776 put_rn(); 01777 PRINTF("sf - System Clock"); 01778 put_rn(); 01779 break; 01780 } 01781 break; 01782 #endif // USE_SYS 01783 //--------------------------------------------------------------------------------- 01784 // Help 01785 //--------------------------------------------------------------------------------- 01786 case '?' : 01787 put_r(); 01788 msg_hlp_hw(); 01789 break; 01790 //--------------------------------------------------------------------------------- 01791 // Return to main routine 01792 //--------------------------------------------------------------------------------- 01793 case 'q' : // Quit 01794 PRINTF("\rReturn to monitor "); 01795 return 0; 01796 //--------------------------------------------------------------------------------- 01797 // Special command for DEBUG 01798 //--------------------------------------------------------------------------------- 01799 #if DEBUG 01800 case 'x' : 01801 not_yet_impliment(); 01802 break; 01803 #endif 01804 } 01805 } 01806 } 01807 01808 #endif
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