Frequency counter using GPS 1PPS signal and temperature controlled 50MHz Base clock. Ported from F411 Frequency Counter.

Dependencies:   QEI DRV8830 PID ADT7410 TextLCD Frq_cuntr_Nucleo-F746ZG RingBuffer

Fork of Frequency_Counter_w_GPS_1PPS by Kenji Arai

Please refer following.
/users/kenjiArai/notebook/frequency-counters/

Revision:
1:2a347c40b1da
Parent:
0:c988614df67a
Child:
2:bff82681a822
--- a/main.cpp	Sun May 26 03:05:25 2013 +0000
+++ b/main.cpp	Sun May 26 05:38:26 2013 +0000
@@ -1,53 +1,61 @@
 //
-//  5MHZ CLOCK OUT USING PWM1 PIN
-//  (ONLY LPC1768-mbed)
-//
-// Code and Comment is from
-// http://mbed.org/forum/mbed/topic/733/
-//
-// The LPC1768 clocks at 96MHz. 
-// 96e6 / 5e6 gives 19.2. 
-// The PWM block counts off of the system clock,
-// so your period counter would have to be either 19 or 20. 
-// 19 gives you a frequency of just over 5.052MHz, 
-// and 20 gives you 4.8 MHz. (Note, to get these frequencies, you have to bypass the library).
-//
-// Assuming that the 5.052andabit is good enough, 
-// here's how you get there. I'll use the library object as a starting point,
-// as it does a load of the pin connection setup,
-// enabling the block and all that for us.
+//  CLOCK OUT to PWM1 PIN Sample with Freq Counter using Cap2.0 
+//  For LPC1768-mbed
 //
-// I'll just go and trample over some of its settings afterwards.
-// I'm going to use pin 21 of the mbed, which is PWM output 6.
+//  Reference: 5MHz Clock Out Code and Comment - http://mbed.org/forum/mbed/topic/733/
 //
-// The PWM block has a match register 0, 
-// which is used as the period counter. 
-// Then, each of the PWM outputs (1 through to 6) have their own match counters,
-// which are used to determine when to change the output level.
-// We're using the block in a simple "output high, until match counter matched, then output low" mode.
-// Thus our value of MR0 is going to be 18 (we count from zero, match at 18),
-// and our value of MR6 (if using p21) is going to be 9.
-// These counters are derived from the system clock, through a peripheral clock divider and a prescaler.
-// So what we need to do is:
+//  !! To Self Measurement Output Clock, Connect p21 <-> p30 with jumper wire.
 //
-//    1)Reset the PWM block
-//    2)Set the peripheral clock divider to /1 (the library sets the prescaler to /1 for us)
-//    3)Load the match registers
-//    4)Tell the block to start at next match
-//    5)Re-start the PWM block
 
 #include "mbed.h"
 
-PwmOut fmclck(p21);
+PwmOut fmclck(p21);     // for RESERVE pin21 as PWM1[6]
+DigitalIn clkin(p30);   // for RESERVE pin30 as CAP2[0]
+
+// Reset Counter and Count Start
+void P30_RESET_CTR(void)
+{
+    LPC_TIM2->TCR = 2;             // Reset the counter (bit1<=1,bit0<=0)
+    LPC_TIM2->TCR = 1;             // UnReset counter (bit1<=0,bit0<=1)
+}
+
+// Get Counter Value
+int P30_GET_CTR(void)
+{
+    return LPC_TIM2->TC; // Read the counter value
+}
 
-int main() {        
+// Setting p30 to Cap2.0
+void P30_INIT_CTR(void)
+{
+    LPC_SC->PCONP |= 1 << 22;               // 1)Power up TimerCounter2 (bit22)
+    LPC_PINCON->PINSEL0 |= 3 << 8;          // 2)Set P0[4] to CAP2[0]
+    LPC_TIM2->TCR = 2;                          // 3)Counter Reset (bit1<=1,bit0<=0)
+    LPC_TIM2->CTCR = 1;                     // 4)Count on riging edge Cap2[0]
+    LPC_TIM2->CCR = 0;                                          // 5)Input Capture Disabled
+    LPC_TIM2->TCR = 1;                          // 6)Counter Start (bit1<=0,bit0<=1)
+}
+
+// Clock Output From pin21(PWM6)
+// Set Clock Freq with div.
+// if mbed is running at 96MHz, div is set 96 to Get 1MHz.
+void PWM6_SETCLK(int div)
+{
     LPC_PWM1->TCR = (1 << 1);               // 1)Reset counter, disable PWM
     LPC_SC->PCLKSEL0 &= ~(0x3 << 12);  
     LPC_SC->PCLKSEL0 |= (1 << 12);          // 2)Set peripheral clock divider to /1, i.e. system clock
-    LPC_PWM1->MR0 = 18;                     // 3)Match Register 0 is shared period counter for all PWM1
-    LPC_PWM1->MR6 = 9;                      // 3)Pin 21 is PWM output 6, so Match Register 6
+    LPC_PWM1->MR0 = div - 1;                // 3)Match Register 0 is shared period counter for all PWM1
+    LPC_PWM1->MR6 = 9;                      // 3)Pin 21 is PWM1[6], so Match Register 6
     LPC_PWM1->LER |= 1;                     // 4)Start updating at next period start
-    LPC_PWM1->TCR = (1 << 0) || (1 << 3);   // 5)Enable counter and PWM
+    LPC_PWM1->TCR = (1 << 0) || (1 << 3);   // 5)Enable counter and PWM    
+}
 
-    while(1);
-}
\ No newline at end of file
+int main() {        
+    PWM6_SETCLK(96) ; // Outout mbed's "PWM6" pin to 96MHZ/19 = 5.052MHz (Approx)
+    P30_INIT_CTR();
+    while(1){
+        P30_RESET_CTR();
+        wait(1.0); // Gate time for count
+        printf("pin30 Freq = %d (Hz)\r\n",P30_GET_CTR());
+    }
+}