Kenji Arai / Mbed OS Frequency_Cntr_1PPS_F746ZG

Frequency counter using GPS 1PPS signal and temperature controlled 50MHz Base clock. Ported from F411 Frequency Counter.

Dependencies:   QEI DRV8830 PID ADT7410 TextLCD Frq_cuntr_Nucleo-F746ZG RingBuffer

Fork of Frequency_Counter_w_GPS_1PPS by Kenji Arai

Please refer following.
/users/kenjiArai/notebook/frequency-counters/

main.cpp@0:c988614df67a, 2013-05-26 (annotated)

Committer:
mio
Date:
Sun May 26 03:05:25 2013 +0000
Revision:
0:c988614df67a
Child:
1:2a347c40b1da
5MHz OSC / No Debug

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mio 0:c988614df67a 1 //
mio 0:c988614df67a 2 // 5MHZ CLOCK OUT USING PWM1 PIN
mio 0:c988614df67a 3 // (ONLY LPC1768-mbed)
mio 0:c988614df67a 4 //
mio 0:c988614df67a 5 // Code and Comment is from
mio 0:c988614df67a 6 // http://mbed.org/forum/mbed/topic/733/
mio 0:c988614df67a 7 //
mio 0:c988614df67a 8 // The LPC1768 clocks at 96MHz.
mio 0:c988614df67a 9 // 96e6 / 5e6 gives 19.2.
mio 0:c988614df67a 10 // The PWM block counts off of the system clock,
mio 0:c988614df67a 11 // so your period counter would have to be either 19 or 20.
mio 0:c988614df67a 12 // 19 gives you a frequency of just over 5.052MHz,
mio 0:c988614df67a 13 // and 20 gives you 4.8 MHz. (Note, to get these frequencies, you have to bypass the library).
mio 0:c988614df67a 14 //
mio 0:c988614df67a 15 // Assuming that the 5.052andabit is good enough,
mio 0:c988614df67a 16 // here's how you get there. I'll use the library object as a starting point,
mio 0:c988614df67a 17 // as it does a load of the pin connection setup,
mio 0:c988614df67a 18 // enabling the block and all that for us.
mio 0:c988614df67a 19 //
mio 0:c988614df67a 20 // I'll just go and trample over some of its settings afterwards.
mio 0:c988614df67a 21 // I'm going to use pin 21 of the mbed, which is PWM output 6.
mio 0:c988614df67a 22 //
mio 0:c988614df67a 23 // The PWM block has a match register 0,
mio 0:c988614df67a 24 // which is used as the period counter.
mio 0:c988614df67a 25 // Then, each of the PWM outputs (1 through to 6) have their own match counters,
mio 0:c988614df67a 26 // which are used to determine when to change the output level.
mio 0:c988614df67a 27 // We're using the block in a simple "output high, until match counter matched, then output low" mode.
mio 0:c988614df67a 28 // Thus our value of MR0 is going to be 18 (we count from zero, match at 18),
mio 0:c988614df67a 29 // and our value of MR6 (if using p21) is going to be 9.
mio 0:c988614df67a 30 // These counters are derived from the system clock, through a peripheral clock divider and a prescaler.
mio 0:c988614df67a 31 // So what we need to do is:
mio 0:c988614df67a 32 //
mio 0:c988614df67a 33 // 1)Reset the PWM block
mio 0:c988614df67a 34 // 2)Set the peripheral clock divider to /1 (the library sets the prescaler to /1 for us)
mio 0:c988614df67a 35 // 3)Load the match registers
mio 0:c988614df67a 36 // 4)Tell the block to start at next match
mio 0:c988614df67a 37 // 5)Re-start the PWM block
mio 0:c988614df67a 38
mio 0:c988614df67a 39 #include "mbed.h"
mio 0:c988614df67a 40
mio 0:c988614df67a 41 PwmOut fmclck(p21);
mio 0:c988614df67a 42
mio 0:c988614df67a 43 int main() {
mio 0:c988614df67a 44 LPC_PWM1->TCR = (1 << 1); // 1)Reset counter, disable PWM
mio 0:c988614df67a 45 LPC_SC->PCLKSEL0 &= ~(0x3 << 12);
mio 0:c988614df67a 46 LPC_SC->PCLKSEL0 |= (1 << 12); // 2)Set peripheral clock divider to /1, i.e. system clock
mio 0:c988614df67a 47 LPC_PWM1->MR0 = 18; // 3)Match Register 0 is shared period counter for all PWM1
mio 0:c988614df67a 48 LPC_PWM1->MR6 = 9; // 3)Pin 21 is PWM output 6, so Match Register 6
mio 0:c988614df67a 49 LPC_PWM1->LER |= 1; // 4)Start updating at next period start
mio 0:c988614df67a 50 LPC_PWM1->TCR = (1 << 0) || (1 << 3); // 5)Enable counter and PWM
mio 0:c988614df67a 51
mio 0:c988614df67a 52 while(1);
mio 0:c988614df67a 53 }