Kenji Arai / Mbed OS Frequency_Cntr_1PPS_F746ZG

Frequency counter using GPS 1PPS signal and temperature controlled 50MHz Base clock. Ported from F411 Frequency Counter.

Dependencies:   QEI DRV8830 PID ADT7410 TextLCD Frq_cuntr_Nucleo-F746ZG RingBuffer

Fork of Frequency_Counter_w_GPS_1PPS by Kenji Arai

Please refer following.
/users/kenjiArai/notebook/frequency-counters/

main.cpp@1:2a347c40b1da, 2013-05-26 (annotated)

Committer:
mio
Date:
Sun May 26 05:38:26 2013 +0000
Revision:
1:2a347c40b1da
Parent:
0:c988614df67a
Child:
2:bff82681a822
5MHz Oscillator output with self counter

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mio 0:c988614df67a 1 //
mio 1:2a347c40b1da 2 // CLOCK OUT to PWM1 PIN Sample with Freq Counter using Cap2.0
mio 1:2a347c40b1da 3 // For LPC1768-mbed
mio 0:c988614df67a 4 //
mio 1:2a347c40b1da 5 // Reference: 5MHz Clock Out Code and Comment - http://mbed.org/forum/mbed/topic/733/
mio 0:c988614df67a 6 //
mio 1:2a347c40b1da 7 // !! To Self Measurement Output Clock, Connect p21 <-> p30 with jumper wire.
mio 0:c988614df67a 8 //
mio 0:c988614df67a 9
mio 0:c988614df67a 10 #include "mbed.h"
mio 0:c988614df67a 11
mio 1:2a347c40b1da 12 PwmOut fmclck(p21); // for RESERVE pin21 as PWM1[6]
mio 1:2a347c40b1da 13 DigitalIn clkin(p30); // for RESERVE pin30 as CAP2[0]
mio 1:2a347c40b1da 14
mio 1:2a347c40b1da 15 // Reset Counter and Count Start
mio 1:2a347c40b1da 16 void P30_RESET_CTR(void)
mio 1:2a347c40b1da 17 {
mio 1:2a347c40b1da 18 LPC_TIM2->TCR = 2; // Reset the counter (bit1<=1,bit0<=0)
mio 1:2a347c40b1da 19 LPC_TIM2->TCR = 1; // UnReset counter (bit1<=0,bit0<=1)
mio 1:2a347c40b1da 20 }
mio 1:2a347c40b1da 21
mio 1:2a347c40b1da 22 // Get Counter Value
mio 1:2a347c40b1da 23 int P30_GET_CTR(void)
mio 1:2a347c40b1da 24 {
mio 1:2a347c40b1da 25 return LPC_TIM2->TC; // Read the counter value
mio 1:2a347c40b1da 26 }
mio 0:c988614df67a 27
mio 1:2a347c40b1da 28 // Setting p30 to Cap2.0
mio 1:2a347c40b1da 29 void P30_INIT_CTR(void)
mio 1:2a347c40b1da 30 {
mio 1:2a347c40b1da 31 LPC_SC->PCONP |= 1 << 22; // 1)Power up TimerCounter2 (bit22)
mio 1:2a347c40b1da 32 LPC_PINCON->PINSEL0 |= 3 << 8; // 2)Set P0[4] to CAP2[0]
mio 1:2a347c40b1da 33 LPC_TIM2->TCR = 2; // 3)Counter Reset (bit1<=1,bit0<=0)
mio 1:2a347c40b1da 34 LPC_TIM2->CTCR = 1; // 4)Count on riging edge Cap2[0]
mio 1:2a347c40b1da 35 LPC_TIM2->CCR = 0; // 5)Input Capture Disabled
mio 1:2a347c40b1da 36 LPC_TIM2->TCR = 1; // 6)Counter Start (bit1<=0,bit0<=1)
mio 1:2a347c40b1da 37 }
mio 1:2a347c40b1da 38
mio 1:2a347c40b1da 39 // Clock Output From pin21(PWM6)
mio 1:2a347c40b1da 40 // Set Clock Freq with div.
mio 1:2a347c40b1da 41 // if mbed is running at 96MHz, div is set 96 to Get 1MHz.
mio 1:2a347c40b1da 42 void PWM6_SETCLK(int div)
mio 1:2a347c40b1da 43 {
mio 0:c988614df67a 44 LPC_PWM1->TCR = (1 << 1); // 1)Reset counter, disable PWM
mio 0:c988614df67a 45 LPC_SC->PCLKSEL0 &= ~(0x3 << 12);
mio 0:c988614df67a 46 LPC_SC->PCLKSEL0 |= (1 << 12); // 2)Set peripheral clock divider to /1, i.e. system clock
mio 1:2a347c40b1da 47 LPC_PWM1->MR0 = div - 1; // 3)Match Register 0 is shared period counter for all PWM1
mio 1:2a347c40b1da 48 LPC_PWM1->MR6 = 9; // 3)Pin 21 is PWM1[6], so Match Register 6
mio 0:c988614df67a 49 LPC_PWM1->LER |= 1; // 4)Start updating at next period start
mio 1:2a347c40b1da 50 LPC_PWM1->TCR = (1 << 0) || (1 << 3); // 5)Enable counter and PWM
mio 1:2a347c40b1da 51 }
mio 0:c988614df67a 52
mio 1:2a347c40b1da 53 int main() {
mio 1:2a347c40b1da 54 PWM6_SETCLK(96) ; // Outout mbed's "PWM6" pin to 96MHZ/19 = 5.052MHz (Approx)
mio 1:2a347c40b1da 55 P30_INIT_CTR();
mio 1:2a347c40b1da 56 while(1){
mio 1:2a347c40b1da 57 P30_RESET_CTR();
mio 1:2a347c40b1da 58 wait(1.0); // Gate time for count
mio 1:2a347c40b1da 59 printf("pin30 Freq = %d (Hz)\r\n",P30_GET_CTR());
mio 1:2a347c40b1da 60 }
mio 1:2a347c40b1da 61 }