test
Fork of SWO by
SWO.cpp@0:0fd55660fc26, 2014-03-28 (annotated)
- Committer:
- wim
- Date:
- Fri Mar 28 19:32:13 2014 +0000
- Revision:
- 0:0fd55660fc26
- Child:
- 1:bae4cff278f6
First Test
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
wim | 0:0fd55660fc26 | 1 | |
wim | 0:0fd55660fc26 | 2 | #include "SWO.h" |
wim | 0:0fd55660fc26 | 3 | |
wim | 0:0fd55660fc26 | 4 | |
wim | 0:0fd55660fc26 | 5 | /********************************************************************* |
wim | 0:0fd55660fc26 | 6 | * |
wim | 0:0fd55660fc26 | 7 | * Defines for Cortex-M debug unit |
wim | 0:0fd55660fc26 | 8 | */ |
wim | 0:0fd55660fc26 | 9 | #define ITM_STIM_U32(n) (*(volatile unsigned int*)(0xE0000000+4*n)) // Stimulus Port n Register word access |
wim | 0:0fd55660fc26 | 10 | //#define ITM_STIM_U32_0 (*(volatile unsigned int*)0xE0000000) // Stimulus Port 0 Register word access |
wim | 0:0fd55660fc26 | 11 | //#define ITM_STIM_U8_0 (*(volatile char*)0xE0000000) // Stimulus Port 0 Register byte access |
wim | 0:0fd55660fc26 | 12 | #define ITM_ENA (*(volatile unsigned int*)0xE0000E00) // Trace Enable Ports Register |
wim | 0:0fd55660fc26 | 13 | #define ITM_TCR (*(volatile unsigned int*)0xE0000E80) // Trace control register |
wim | 0:0fd55660fc26 | 14 | |
wim | 0:0fd55660fc26 | 15 | |
wim | 0:0fd55660fc26 | 16 | |
wim | 0:0fd55660fc26 | 17 | /********************************************************************* |
wim | 0:0fd55660fc26 | 18 | * |
wim | 0:0fd55660fc26 | 19 | * SWO_PrintChar() |
wim | 0:0fd55660fc26 | 20 | * |
wim | 0:0fd55660fc26 | 21 | * @brief |
wim | 0:0fd55660fc26 | 22 | * Checks if SWO is set up. If it is not, return, |
wim | 0:0fd55660fc26 | 23 | * to avoid program hangs if no debugger is connected. |
wim | 0:0fd55660fc26 | 24 | * If it is set up, print a character to the ITM_STIM register |
wim | 0:0fd55660fc26 | 25 | * in order to provide data for SWO. |
wim | 0:0fd55660fc26 | 26 | * @param c The Character to be printed. |
wim | 0:0fd55660fc26 | 27 | * @notes Additional checks for device specific registers can be added. |
wim | 0:0fd55660fc26 | 28 | */ |
wim | 0:0fd55660fc26 | 29 | void SWO_PrintChar(char c) { |
wim | 0:0fd55660fc26 | 30 | // |
wim | 0:0fd55660fc26 | 31 | // Check if ITM_TCR.ITMENA is set |
wim | 0:0fd55660fc26 | 32 | // |
wim | 0:0fd55660fc26 | 33 | if ((ITM_TCR & 1) == 0) { |
wim | 0:0fd55660fc26 | 34 | return; |
wim | 0:0fd55660fc26 | 35 | } |
wim | 0:0fd55660fc26 | 36 | // |
wim | 0:0fd55660fc26 | 37 | // Check if stimulus port is enabled |
wim | 0:0fd55660fc26 | 38 | // |
wim | 0:0fd55660fc26 | 39 | if ((ITM_ENA & 1) == 0) { |
wim | 0:0fd55660fc26 | 40 | return; |
wim | 0:0fd55660fc26 | 41 | } |
wim | 0:0fd55660fc26 | 42 | // |
wim | 0:0fd55660fc26 | 43 | // Wait until STIMx is ready, |
wim | 0:0fd55660fc26 | 44 | // then send data |
wim | 0:0fd55660fc26 | 45 | // |
wim | 0:0fd55660fc26 | 46 | // while ((ITM_STIM_U8(0) & 1) == 0); |
wim | 0:0fd55660fc26 | 47 | // ITM_STIM_U8(0) = c; |
wim | 0:0fd55660fc26 | 48 | |
wim | 0:0fd55660fc26 | 49 | while ((ITM_STIM_U32(0) & 1) == 0); |
wim | 0:0fd55660fc26 | 50 | ITM_STIM_U32(0) = c; |
wim | 0:0fd55660fc26 | 51 | } |
wim | 0:0fd55660fc26 | 52 | |
wim | 0:0fd55660fc26 | 53 | /********************************************************************* |
wim | 0:0fd55660fc26 | 54 | * |
wim | 0:0fd55660fc26 | 55 | * SWO_PrintString() |
wim | 0:0fd55660fc26 | 56 | * |
wim | 0:0fd55660fc26 | 57 | * @brief Print a string via SWO. |
wim | 0:0fd55660fc26 | 58 | * @param *s The string to be printed. |
wim | 0:0fd55660fc26 | 59 | * |
wim | 0:0fd55660fc26 | 60 | */ |
wim | 0:0fd55660fc26 | 61 | void SWO_PrintString(const char *s) { |
wim | 0:0fd55660fc26 | 62 | // |
wim | 0:0fd55660fc26 | 63 | // Print out character per character |
wim | 0:0fd55660fc26 | 64 | // |
wim | 0:0fd55660fc26 | 65 | while (*s) { |
wim | 0:0fd55660fc26 | 66 | SWO_PrintChar(*s++); |
wim | 0:0fd55660fc26 | 67 | } |
wim | 0:0fd55660fc26 | 68 | } |