karthick B / GR-PEACH_video

vedio_gr_peach

Fork of GR-PEACH_video by Renesas

drivers/vdec/src/r_vdec_register.c@0:853f5b7408a7, 2015-06-26 (annotated)

Committer:
dkato
Date:
Fri Jun 26 02:17:53 2015 +0000
Revision:
0:853f5b7408a7
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dkato 0:853f5b7408a7 1 /*******************************************************************************
dkato 0:853f5b7408a7 2 * DISCLAIMER
dkato 0:853f5b7408a7 3 * This software is supplied by Renesas Electronics Corporation and is only
dkato 0:853f5b7408a7 4 * intended for use with Renesas products. No other uses are authorized. This
dkato 0:853f5b7408a7 5 * software is owned by Renesas Electronics Corporation and is protected under
dkato 0:853f5b7408a7 6 * all applicable laws, including copyright laws.
dkato 0:853f5b7408a7 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
dkato 0:853f5b7408a7 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
dkato 0:853f5b7408a7 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
dkato 0:853f5b7408a7 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
dkato 0:853f5b7408a7 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
dkato 0:853f5b7408a7 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
dkato 0:853f5b7408a7 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
dkato 0:853f5b7408a7 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
dkato 0:853f5b7408a7 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
dkato 0:853f5b7408a7 16 * Renesas reserves the right, without notice, to make changes to this software
dkato 0:853f5b7408a7 17 * and to discontinue the availability of this software. By using this software,
dkato 0:853f5b7408a7 18 * you agree to the additional terms and conditions found by accessing the
dkato 0:853f5b7408a7 19 * following link:
dkato 0:853f5b7408a7 20 * http://www.renesas.com/disclaimer
dkato 0:853f5b7408a7 21 * Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
dkato 0:853f5b7408a7 22 *******************************************************************************/
dkato 0:853f5b7408a7 23 /**************************************************************************//**
dkato 0:853f5b7408a7 24 * @file r_vdec_register.c
dkato 0:853f5b7408a7 25 * @version 1.00
dkato 0:853f5b7408a7 26 * $Rev: 199 $
dkato 0:853f5b7408a7 27 * $Date:: 2014-05-23 16:33:52 +0900#$
dkato 0:853f5b7408a7 28 * @brief VDEC driver register setup processing
dkato 0:853f5b7408a7 29 ******************************************************************************/
dkato 0:853f5b7408a7 30
dkato 0:853f5b7408a7 31 /******************************************************************************
dkato 0:853f5b7408a7 32 Includes <System Includes> , "Project Includes"
dkato 0:853f5b7408a7 33 ******************************************************************************/
dkato 0:853f5b7408a7 34 #include "r_vdec.h"
dkato 0:853f5b7408a7 35 #include "r_vdec_user.h"
dkato 0:853f5b7408a7 36 #include "r_vdec_register.h"
dkato 0:853f5b7408a7 37
dkato 0:853f5b7408a7 38
dkato 0:853f5b7408a7 39 /******************************************************************************
dkato 0:853f5b7408a7 40 Macro definitions
dkato 0:853f5b7408a7 41 ******************************************************************************/
dkato 0:853f5b7408a7 42 /* shift value */
dkato 0:853f5b7408a7 43 #define VEDC_REG_SHIFT_15 (15u)
dkato 0:853f5b7408a7 44 #define VEDC_REG_SHIFT_14 (14u)
dkato 0:853f5b7408a7 45 #define VEDC_REG_SHIFT_13 (13u)
dkato 0:853f5b7408a7 46 #define VEDC_REG_SHIFT_12 (12u)
dkato 0:853f5b7408a7 47 #define VEDC_REG_SHIFT_11 (11u)
dkato 0:853f5b7408a7 48 #define VEDC_REG_SHIFT_10 (10u)
dkato 0:853f5b7408a7 49 #define VEDC_REG_SHIFT_9 (9u)
dkato 0:853f5b7408a7 50 #define VEDC_REG_SHIFT_8 (8u)
dkato 0:853f5b7408a7 51 #define VEDC_REG_SHIFT_6 (6u)
dkato 0:853f5b7408a7 52 #define VEDC_REG_SHIFT_5 (5u)
dkato 0:853f5b7408a7 53 #define VEDC_REG_SHIFT_4 (4u)
dkato 0:853f5b7408a7 54 #define VEDC_REG_SHIFT_2 (2u)
dkato 0:853f5b7408a7 55 #define VEDC_REG_SHIFT_1 (1u)
dkato 0:853f5b7408a7 56
dkato 0:853f5b7408a7 57 /* bit set pattern */
dkato 0:853f5b7408a7 58 #define VDEC_REG_SET_0X8000 (0x8000u)
dkato 0:853f5b7408a7 59 #define VDEC_REG_SET_0X4000 (0x4000u)
dkato 0:853f5b7408a7 60 #define VDEC_REG_SET_0X2000 (0x2000u)
dkato 0:853f5b7408a7 61 #define VDEC_REG_SET_0X1000 (0x1000u)
dkato 0:853f5b7408a7 62 #define VDEC_REG_SET_0X0800 (0x0800u)
dkato 0:853f5b7408a7 63 #define VDEC_REG_SET_0X0100 (0x0100u)
dkato 0:853f5b7408a7 64 #define VDEC_REG_SET_0X0080 (0x0080u)
dkato 0:853f5b7408a7 65 #define VDEC_REG_SET_0X0020 (0x0020u)
dkato 0:853f5b7408a7 66 #define VDEC_REG_SET_0X0010 (0x0010u)
dkato 0:853f5b7408a7 67 #define VDEC_REG_SET_0X0008 (0x0008u)
dkato 0:853f5b7408a7 68 #define VDEC_REG_SET_0X0004 (0x0004u)
dkato 0:853f5b7408a7 69 #define VDEC_REG_SET_0X0002 (0x0002u)
dkato 0:853f5b7408a7 70 #define VDEC_REG_SET_0X0001 (0x0001u)
dkato 0:853f5b7408a7 71
dkato 0:853f5b7408a7 72 /* bit mask pattern */
dkato 0:853f5b7408a7 73 #define VDEC_REG_BIT_MASK_0X8000 (0x8000u)
dkato 0:853f5b7408a7 74 #define VDEC_REG_BIT_MASK_0X4000 (0x4000u)
dkato 0:853f5b7408a7 75 #define VDEC_REG_BIT_MASK_0X2000 (0x2000u)
dkato 0:853f5b7408a7 76 #define VDEC_REG_BIT_MASK_0X1000 (0x1000u)
dkato 0:853f5b7408a7 77 #define VDEC_REG_BIT_MASK_0X0800 (0x0800u)
dkato 0:853f5b7408a7 78 #define VDEC_REG_BIT_MASK_0X0400 (0x0400u)
dkato 0:853f5b7408a7 79 #define VDEC_REG_BIT_MASK_0X0200 (0x0200u)
dkato 0:853f5b7408a7 80 #define VDEC_REG_BIT_MASK_0X0100 (0x0100u)
dkato 0:853f5b7408a7 81
dkato 0:853f5b7408a7 82 /* register mask value */
dkato 0:853f5b7408a7 83 #define VDEC_REG_MASK_0X03FF (0x03FFu) /* mask vdec_reg->syncssr */
dkato 0:853f5b7408a7 84 #define VDEC_REG_MASK_0XFF1F (0xFF1Fu) /* mask vdec_reg->ycscr7 */
dkato 0:853f5b7408a7 85 #define VDEC_REG_MASK_0XF3FF (0xF3FFu) /* mask vdec_reg->hafccr1 */
dkato 0:853f5b7408a7 86 #define VDEC_REG_MASK_0X83FF (0x83FFu) /* mask vdec_reg->dcpcr1 */
dkato 0:853f5b7408a7 87 #define VDEC_REG_MASK_0X01FF (0x01FFu) /* mask vdec_reg->ycscr11 */
dkato 0:853f5b7408a7 88 #define VDEC_REG_MASK_0X1C00 (0x1C00u) /* mask vdec_reg->dcpcr9 */
dkato 0:853f5b7408a7 89 #define VDEC_REG_MASK_0X1F00 (0x1F00u) /* mask vdec_reg->pgacr */
dkato 0:853f5b7408a7 90 #define VDEC_REG_MASK_0X3F00 (0x3F00u) /* mask vdec_reg->agccr2 */
dkato 0:853f5b7408a7 91 #define VDEC_REG_MASK_0X0007 (0x0007u) /* mask vdec_reg->rgorcr7 */
dkato 0:853f5b7408a7 92 #define VDEC_REG_MASK_0XF800 (0xF800u) /* mask vdec_reg->ycscr8 */
dkato 0:853f5b7408a7 93 #define VDEC_REG_MASK_0XFC00 (0xFC00u) /* mask vdec_reg->synscr1 */
dkato 0:853f5b7408a7 94 #define VDEC_REG_MASK_0X00FF (0x00FFu) /* mask vdec_reg->synscr1 */
dkato 0:853f5b7408a7 95 #define VDEC_REG_MASK_0X0003 (0x0003u) /* mask vdec_reg->cromasr1 */
dkato 0:853f5b7408a7 96
dkato 0:853f5b7408a7 97 /******************************************************************************
dkato 0:853f5b7408a7 98 Typedef definitions
dkato 0:853f5b7408a7 99 ******************************************************************************/
dkato 0:853f5b7408a7 100
dkato 0:853f5b7408a7 101 /******************************************************************************
dkato 0:853f5b7408a7 102 Private global variables and functions
dkato 0:853f5b7408a7 103 ******************************************************************************/
dkato 0:853f5b7408a7 104 static void NoiseReductionLPF(
dkato 0:853f5b7408a7 105 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 106 const vdec_noise_rd_lpf_t * const p_noise_rd_lpf);
dkato 0:853f5b7408a7 107 static void SyncSlicer(const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer);
dkato 0:853f5b7408a7 108 static void HorizontalAFC(
dkato 0:853f5b7408a7 109 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 110 const vdec_horizontal_afc_t * const p_horizontal_afc);
dkato 0:853f5b7408a7 111 static void VerticalCountdown(
dkato 0:853f5b7408a7 112 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 113 const vdec_vcount_down_t * const p_vcount_down);
dkato 0:853f5b7408a7 114 static void AgcPga(const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc);
dkato 0:853f5b7408a7 115 static void PeakLimiterControl(
dkato 0:853f5b7408a7 116 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 117 const vdec_peak_limiter_t * const p_peak_limiter);
dkato 0:853f5b7408a7 118 static void OverRangeControl(const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range);
dkato 0:853f5b7408a7 119 static void YcSeparationControl(
dkato 0:853f5b7408a7 120 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 121 const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl);
dkato 0:853f5b7408a7 122 static void FilterTAPsCoefficient(
dkato 0:853f5b7408a7 123 volatile uint16_t * const * fil_reg_address,
dkato 0:853f5b7408a7 124 const vdec_chrfil_tap_t * const fil2_2d);
dkato 0:853f5b7408a7 125
dkato 0:853f5b7408a7 126
dkato 0:853f5b7408a7 127 /**************************************************************************//**
dkato 0:853f5b7408a7 128 * @brief Sets registers for initialization
dkato 0:853f5b7408a7 129 * @param[in] ch : Channel
dkato 0:853f5b7408a7 130 * @param[in] vinsel : Input pin control
dkato 0:853f5b7408a7 131 * @retval None
dkato 0:853f5b7408a7 132 *****************************************************************************/
dkato 0:853f5b7408a7 133 void VDEC_Initialize (const vdec_channel_t ch, const vdec_adc_vinsel_t vinsel)
dkato 0:853f5b7408a7 134 {
dkato 0:853f5b7408a7 135 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 136 uint16_t reg_data;
dkato 0:853f5b7408a7 137
dkato 0:853f5b7408a7 138 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 139
dkato 0:853f5b7408a7 140 /* Input pin control */
dkato 0:853f5b7408a7 141 if (vinsel == VDEC_ADC_VINSEL_VIN1) {
dkato 0:853f5b7408a7 142 reg_data = (uint16_t)((uint32_t)*(vdec_reg->adccr2) & (~0x0001u));
dkato 0:853f5b7408a7 143 *(vdec_reg->adccr2) = reg_data;
dkato 0:853f5b7408a7 144 } else {
dkato 0:853f5b7408a7 145 reg_data = (uint16_t)((uint32_t)*(vdec_reg->adccr2) | (0x0001u));
dkato 0:853f5b7408a7 146 *(vdec_reg->adccr2) = reg_data;
dkato 0:853f5b7408a7 147 }
dkato 0:853f5b7408a7 148 return;
dkato 0:853f5b7408a7 149 } /* End of function VDEC_Initialize() */
dkato 0:853f5b7408a7 150
dkato 0:853f5b7408a7 151 /**************************************************************************//**
dkato 0:853f5b7408a7 152 * @brief Sets registers for active image period
dkato 0:853f5b7408a7 153 * @param[in] ch : Channel
dkato 0:853f5b7408a7 154 * @param[in] param : Active image period parameter
dkato 0:853f5b7408a7 155 * @retval None
dkato 0:853f5b7408a7 156 *****************************************************************************/
dkato 0:853f5b7408a7 157 void VDEC_ActivePeriod (const vdec_channel_t ch, const vdec_active_period_t * const param)
dkato 0:853f5b7408a7 158 {
dkato 0:853f5b7408a7 159 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 160
dkato 0:853f5b7408a7 161 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 162
dkato 0:853f5b7408a7 163 /* Left end of input video signal capturing area */
dkato 0:853f5b7408a7 164 *(vdec_reg->tgcr1) = param->srcleft;
dkato 0:853f5b7408a7 165 /* Top end of input video signal capturing area
dkato 0:853f5b7408a7 166 and height of input video signal capturing area */
dkato 0:853f5b7408a7 167 *(vdec_reg->tgcr2) = (uint16_t)(((uint32_t)param->srctop << VEDC_REG_SHIFT_10) | (uint32_t)param->srcheight);
dkato 0:853f5b7408a7 168 /* Width of input video signal capturing area */
dkato 0:853f5b7408a7 169 *(vdec_reg->tgcr3) = param->srcwidth;
dkato 0:853f5b7408a7 170
dkato 0:853f5b7408a7 171 return;
dkato 0:853f5b7408a7 172 } /* End of function VDEC_ActivePeriod() */
dkato 0:853f5b7408a7 173
dkato 0:853f5b7408a7 174 /**************************************************************************//**
dkato 0:853f5b7408a7 175 * @brief Sets registers for sync separation
dkato 0:853f5b7408a7 176 * @param[in] ch : Channel
dkato 0:853f5b7408a7 177 * @param[in] param : Sync separation parameter
dkato 0:853f5b7408a7 178 * @retval None
dkato 0:853f5b7408a7 179 *****************************************************************************/
dkato 0:853f5b7408a7 180 void VDEC_SyncSeparation (const vdec_channel_t ch, const vdec_sync_separation_t * const param)
dkato 0:853f5b7408a7 181 {
dkato 0:853f5b7408a7 182 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 183
dkato 0:853f5b7408a7 184 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 185
dkato 0:853f5b7408a7 186 /* Noise reduction LPF */
dkato 0:853f5b7408a7 187 NoiseReductionLPF(vdec_reg, param->noise_rd_lpf);
dkato 0:853f5b7408a7 188 /* Auto level control sync slicer */
dkato 0:853f5b7408a7 189 SyncSlicer(vdec_reg, param->sync_slicer);
dkato 0:853f5b7408a7 190 /* Horizontal AFC */
dkato 0:853f5b7408a7 191 HorizontalAFC(vdec_reg, param->horizontal_afc);
dkato 0:853f5b7408a7 192 /* Vertical count-down */
dkato 0:853f5b7408a7 193 VerticalCountdown(vdec_reg, param->vcount_down);
dkato 0:853f5b7408a7 194 /* AGC/PGA */
dkato 0:853f5b7408a7 195 AgcPga(vdec_reg, param->agc);
dkato 0:853f5b7408a7 196 /* Peak limiter control */
dkato 0:853f5b7408a7 197 PeakLimiterControl(vdec_reg, param->peak_limiter);
dkato 0:853f5b7408a7 198
dkato 0:853f5b7408a7 199 return;
dkato 0:853f5b7408a7 200 } /* End of function VDEC_SyncSeparation() */
dkato 0:853f5b7408a7 201
dkato 0:853f5b7408a7 202 /**************************************************************************//**
dkato 0:853f5b7408a7 203 * @brief Sets registers for Y/C separation
dkato 0:853f5b7408a7 204 * @param[in] ch : Channel
dkato 0:853f5b7408a7 205 * @param[in] param : Y/C separation parameter
dkato 0:853f5b7408a7 206 * @retval None
dkato 0:853f5b7408a7 207 *****************************************************************************/
dkato 0:853f5b7408a7 208 void VDEC_YcSeparation (const vdec_channel_t ch, const vdec_yc_separation_t * const param)
dkato 0:853f5b7408a7 209 {
dkato 0:853f5b7408a7 210 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 211
dkato 0:853f5b7408a7 212 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 213
dkato 0:853f5b7408a7 214 /* Over-range control */
dkato 0:853f5b7408a7 215 OverRangeControl(vdec_reg, param->over_range);
dkato 0:853f5b7408a7 216 /* Y/C separation control */
dkato 0:853f5b7408a7 217 YcSeparationControl(vdec_reg, param->yc_sep_ctrl);
dkato 0:853f5b7408a7 218
dkato 0:853f5b7408a7 219 /* Two-dimensional cascade broadband (3.58/4.43/SECAM-DR)/TAKE-OFF filter TAP coefficient */
dkato 0:853f5b7408a7 220 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwa_f, param->fil2_2d_wa);
dkato 0:853f5b7408a7 221 /* Two-dimensional cascade broadband (SECAM-DB) filter TAP coefficient */
dkato 0:853f5b7408a7 222 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctwb_f, param->fil2_2d_wb);
dkato 0:853f5b7408a7 223 /* Two-dimensional cascade narrowband (3.58/4.43/SECAM-DR) filter TAP coefficient */
dkato 0:853f5b7408a7 224 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctna_f, param->fil2_2d_na);
dkato 0:853f5b7408a7 225 /* Two-dimensional cascade narrowband (SECAMDB) filter TAP coefficient */
dkato 0:853f5b7408a7 226 FilterTAPsCoefficient(vdec_filter_reg_address[ch].yctnb_f, param->fil2_2d_nb);
dkato 0:853f5b7408a7 227
dkato 0:853f5b7408a7 228 return;
dkato 0:853f5b7408a7 229 } /* End of function VDEC_YcSeparation() */
dkato 0:853f5b7408a7 230
dkato 0:853f5b7408a7 231 /**************************************************************************//**
dkato 0:853f5b7408a7 232 * @brief Sets registers for chroma decoding
dkato 0:853f5b7408a7 233 * @param[in] ch : Channel
dkato 0:853f5b7408a7 234 * @param[in] param : Chroma decoding parameter
dkato 0:853f5b7408a7 235 * @retval None
dkato 0:853f5b7408a7 236 *****************************************************************************/
dkato 0:853f5b7408a7 237 void VDEC_ChromaDecoding (const vdec_channel_t ch, const vdec_chroma_decoding_t * const param)
dkato 0:853f5b7408a7 238 {
dkato 0:853f5b7408a7 239 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 240 vdec_chrmdec_ctrl_t * p_chrmdec_ctrl;
dkato 0:853f5b7408a7 241 vdec_burst_lock_t * p_burst_lock;
dkato 0:853f5b7408a7 242 vdec_acc_t * p_acc;
dkato 0:853f5b7408a7 243 vdec_tint_ry_t * p_tint_ry;
dkato 0:853f5b7408a7 244 uint32_t reg_data;
dkato 0:853f5b7408a7 245
dkato 0:853f5b7408a7 246 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 247 p_chrmdec_ctrl = param->chrmdec_ctrl;
dkato 0:853f5b7408a7 248 p_burst_lock = param->burst_lock;
dkato 0:853f5b7408a7 249 p_acc = param->acc;
dkato 0:853f5b7408a7 250 p_tint_ry = param->tint_ry;
dkato 0:853f5b7408a7 251
dkato 0:853f5b7408a7 252 /* Color system detection */
dkato 0:853f5b7408a7 253 if (p_chrmdec_ctrl != NULL) {
dkato 0:853f5b7408a7 254 reg_data = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
dkato 0:853f5b7408a7 255 /* Default color system */
dkato 0:853f5b7408a7 256 reg_data |= (uint32_t)p_chrmdec_ctrl->defaultsys << VEDC_REG_SHIFT_6;
dkato 0:853f5b7408a7 257 /* NTSC-M detection control */
dkato 0:853f5b7408a7 258 reg_data |= (p_chrmdec_ctrl->nontsc358_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0020 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 259 /* NTSC-4.43 detection control */
dkato 0:853f5b7408a7 260 reg_data |= (p_chrmdec_ctrl->nontsc443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0010 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 261 /* PAL-M detection control */
dkato 0:853f5b7408a7 262 reg_data |= (p_chrmdec_ctrl->nopalm_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0008 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 263 /* PAL-N detection control */
dkato 0:853f5b7408a7 264 reg_data |= (p_chrmdec_ctrl->nopaln_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0004 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 265 /* PAL-B, G, H, I, D detection control */
dkato 0:853f5b7408a7 266 reg_data |= (p_chrmdec_ctrl->nopal443_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0002 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 267 /* SECAM detection control */
dkato 0:853f5b7408a7 268 reg_data |= (p_chrmdec_ctrl->nosecam_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X0001 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 269
dkato 0:853f5b7408a7 270 *(vdec_reg->btlcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 271
dkato 0:853f5b7408a7 272 /* Luminance signal delay adjustment */
dkato 0:853f5b7408a7 273 reg_data = (uint32_t)p_chrmdec_ctrl->lumadelay << VEDC_REG_SHIFT_4;
dkato 0:853f5b7408a7 274 /* LPF for demodulated chroma */
dkato 0:853f5b7408a7 275 reg_data |= (p_chrmdec_ctrl->chromalpf == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
dkato 0:853f5b7408a7 276 /* Averaging processing for pre-demodulated line */
dkato 0:853f5b7408a7 277 reg_data |= (uint32_t)p_chrmdec_ctrl->demodmode;
dkato 0:853f5b7408a7 278
dkato 0:853f5b7408a7 279 *(vdec_reg->ycdcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 280 }
dkato 0:853f5b7408a7 281 /* BCO */
dkato 0:853f5b7408a7 282 if (p_burst_lock != NULL) {
dkato 0:853f5b7408a7 283 reg_data = (uint32_t)*(vdec_reg->btlcr) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
dkato 0:853f5b7408a7 284 /* Burst lock PLL lock range */
dkato 0:853f5b7408a7 285 reg_data |= (uint32_t)p_burst_lock->lockrange << VEDC_REG_SHIFT_14;
dkato 0:853f5b7408a7 286 /* Burst lock PLL loop gain */
dkato 0:853f5b7408a7 287 reg_data |= (uint32_t)p_burst_lock->loopgain << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 288 /* Level for burst lock PLL to re-search free-run frequency */
dkato 0:853f5b7408a7 289 reg_data |= (uint32_t)p_burst_lock->locklimit << VEDC_REG_SHIFT_10;
dkato 0:853f5b7408a7 290
dkato 0:853f5b7408a7 291 *(vdec_reg->btlcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 292
dkato 0:853f5b7408a7 293 /* burst gate pulse position check */
dkato 0:853f5b7408a7 294 reg_data = (uint32_t)p_burst_lock->bgpcheck << VEDC_REG_SHIFT_15;
dkato 0:853f5b7408a7 295 /* burst gate pulse width */
dkato 0:853f5b7408a7 296 reg_data |= (uint32_t)p_burst_lock->bgpwidth << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 297 /* burst gate pulse start position */
dkato 0:853f5b7408a7 298 reg_data |= (uint32_t)p_burst_lock->bgpstart;
dkato 0:853f5b7408a7 299
dkato 0:853f5b7408a7 300 *(vdec_reg->btgpcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 301 }
dkato 0:853f5b7408a7 302 /* ACC and color killer */
dkato 0:853f5b7408a7 303 if (p_acc != NULL) {
dkato 0:853f5b7408a7 304 /* ACC operating mode */
dkato 0:853f5b7408a7 305 reg_data = (p_acc->accmode == VDEC_ACC_MD_AUTO) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
dkato 0:853f5b7408a7 306 /* Maximum ACC Gain */
dkato 0:853f5b7408a7 307 reg_data |= (uint32_t)p_acc->accmaxgain << VEDC_REG_SHIFT_9;
dkato 0:853f5b7408a7 308 /* ACC reference color burst amplitude */
dkato 0:853f5b7408a7 309 reg_data |= (uint32_t)p_acc->acclevel;
dkato 0:853f5b7408a7 310 /* Color killer offset */
dkato 0:853f5b7408a7 311 reg_data |= (uint32_t)p_acc->killeroffset << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 312
dkato 0:853f5b7408a7 313 *(vdec_reg->acccr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 314
dkato 0:853f5b7408a7 315 /* Chroma manual gain (sub) */
dkato 0:853f5b7408a7 316 reg_data = (uint32_t)p_acc->chromasubgain << VEDC_REG_SHIFT_9;
dkato 0:853f5b7408a7 317 /* Chroma manual gain (main) */
dkato 0:853f5b7408a7 318 reg_data |= (uint32_t)p_acc->chromamaingain;
dkato 0:853f5b7408a7 319
dkato 0:853f5b7408a7 320 *(vdec_reg->acccr2) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 321
dkato 0:853f5b7408a7 322 /* ACC response speed */
dkato 0:853f5b7408a7 323 reg_data = (uint32_t)p_acc->accresponse << VEDC_REG_SHIFT_14;
dkato 0:853f5b7408a7 324 /* ACC gain adjustment accuracy */
dkato 0:853f5b7408a7 325 reg_data |= (uint32_t)p_acc->accprecis << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 326 /* Forced color killer mode ON/OFF */
dkato 0:853f5b7408a7 327 reg_data |= (p_acc->killermode == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0080;
dkato 0:853f5b7408a7 328 /* Color killer operation start point */
dkato 0:853f5b7408a7 329 reg_data |= (uint32_t)p_acc->killerlevel << VEDC_REG_SHIFT_1;
dkato 0:853f5b7408a7 330
dkato 0:853f5b7408a7 331 *(vdec_reg->acccr3) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 332 }
dkato 0:853f5b7408a7 333 /* TINT correction/R-Y axis correction (only valid for NTSC/PAL) */
dkato 0:853f5b7408a7 334 if (p_tint_ry != NULL) {
dkato 0:853f5b7408a7 335 /* Fine adjustment of R-Y demodulation axis and hue adjustment level */
dkato 0:853f5b7408a7 336 reg_data = (uint32_t)p_tint_ry->tintsub << VEDC_REG_SHIFT_10;
dkato 0:853f5b7408a7 337 reg_data |= (uint32_t)p_tint_ry->tintmain;
dkato 0:853f5b7408a7 338
dkato 0:853f5b7408a7 339 *(vdec_reg->tintcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 340 }
dkato 0:853f5b7408a7 341 return;
dkato 0:853f5b7408a7 342 } /* End of function VDEC_ChromaDecoding() */
dkato 0:853f5b7408a7 343
dkato 0:853f5b7408a7 344 /**************************************************************************//**
dkato 0:853f5b7408a7 345 * @brief Sets registers for digital clamp
dkato 0:853f5b7408a7 346 * @param[in] ch : Channel
dkato 0:853f5b7408a7 347 * @param[in] param : Digital clamp parameter
dkato 0:853f5b7408a7 348 * @retval None
dkato 0:853f5b7408a7 349 *****************************************************************************/
dkato 0:853f5b7408a7 350 void VDEC_DigitalClamp (const vdec_channel_t ch, const vdec_degital_clamp_t * const param)
dkato 0:853f5b7408a7 351 {
dkato 0:853f5b7408a7 352 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 353 vdec_pedestal_clamp_t * p_pedestal_clamp;
dkato 0:853f5b7408a7 354 vdec_center_clamp_t * p_center_clamp;
dkato 0:853f5b7408a7 355 vdec_noise_det_t * p_noise_det;
dkato 0:853f5b7408a7 356 uint32_t reg_data;
dkato 0:853f5b7408a7 357
dkato 0:853f5b7408a7 358 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 359 p_pedestal_clamp = param->pedestal_clamp;
dkato 0:853f5b7408a7 360 p_center_clamp = param->center_clamp;
dkato 0:853f5b7408a7 361 p_noise_det = param->noise_det;
dkato 0:853f5b7408a7 362
dkato 0:853f5b7408a7 363 /* Digital clamp pulse position check */
dkato 0:853f5b7408a7 364 reg_data = (uint32_t)*(vdec_reg->dcpcr1);
dkato 0:853f5b7408a7 365 if (param->dcpcheck == VDEC_OFF) {
dkato 0:853f5b7408a7 366 reg_data &= (uint32_t)(~VDEC_REG_SET_0X0800);
dkato 0:853f5b7408a7 367 } else {
dkato 0:853f5b7408a7 368 reg_data |= (uint32_t)VDEC_REG_SET_0X0800;
dkato 0:853f5b7408a7 369 }
dkato 0:853f5b7408a7 370 *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 371
dkato 0:853f5b7408a7 372 /* Digital clamp response speed */
dkato 0:853f5b7408a7 373 *(vdec_reg->dcpcr3) = (uint16_t)((uint32_t)param->dcpresponse << VEDC_REG_SHIFT_12);
dkato 0:853f5b7408a7 374 /* Digital clamp start line */
dkato 0:853f5b7408a7 375 *(vdec_reg->dcpcr4) = (uint16_t)((uint32_t)param->dcpstart << VEDC_REG_SHIFT_10);
dkato 0:853f5b7408a7 376 /* Digital clamp end line */
dkato 0:853f5b7408a7 377 *(vdec_reg->dcpcr5) = (uint16_t)((uint32_t)param->dcpend << VEDC_REG_SHIFT_10);
dkato 0:853f5b7408a7 378 /* Digital clamp pulse width */
dkato 0:853f5b7408a7 379 *(vdec_reg->dcpcr6) = (uint16_t)((uint32_t)param->dcpwidth << VEDC_REG_SHIFT_8);
dkato 0:853f5b7408a7 380
dkato 0:853f5b7408a7 381 /* Pedestal clamp */
dkato 0:853f5b7408a7 382 if (p_pedestal_clamp != NULL) {
dkato 0:853f5b7408a7 383 reg_data = (uint32_t)*(vdec_reg->dcpcr1) & (uint32_t)(~VDEC_REG_MASK_0X83FF);
dkato 0:853f5b7408a7 384 /* Clamp level setting mode (Y signal) */
dkato 0:853f5b7408a7 385 reg_data |= (p_pedestal_clamp->dcpmode_y == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 386 (uint32_t)VDEC_REG_SET_0X8000;
dkato 0:853f5b7408a7 387 /* Clamp offset level (Y signal) */
dkato 0:853f5b7408a7 388 reg_data |= (uint32_t)p_pedestal_clamp->blanklevel_y;
dkato 0:853f5b7408a7 389
dkato 0:853f5b7408a7 390 *(vdec_reg->dcpcr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 391
dkato 0:853f5b7408a7 392 /* Digital clamp pulse horizontal start position (Y signal) */
dkato 0:853f5b7408a7 393 *(vdec_reg->dcpcr7) = (uint16_t)((uint32_t)p_pedestal_clamp->dcppos_y << VEDC_REG_SHIFT_8);
dkato 0:853f5b7408a7 394 }
dkato 0:853f5b7408a7 395 /* Center clamp */
dkato 0:853f5b7408a7 396 if (p_center_clamp != NULL) {
dkato 0:853f5b7408a7 397 /* Clamp level setting mode (Cb/Cr signal) */
dkato 0:853f5b7408a7 398 reg_data = (p_center_clamp->dcpmode_c == VDEC_DCPMODE_MANUAL) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 399 (uint32_t)VDEC_REG_SET_0X8000;
dkato 0:853f5b7408a7 400 /* Clamp offset level (Cb signal) */
dkato 0:853f5b7408a7 401 reg_data |= (uint32_t)p_center_clamp->blanklevel_cb << VEDC_REG_SHIFT_6;
dkato 0:853f5b7408a7 402 /* Clamp offset level (Cr signal) */
dkato 0:853f5b7408a7 403 reg_data |= (uint32_t)p_center_clamp->blanklevel_cr;
dkato 0:853f5b7408a7 404
dkato 0:853f5b7408a7 405 *(vdec_reg->dcpcr2) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 406
dkato 0:853f5b7408a7 407 /* Digital clamp pulse horizontal start position (Cb/Cr signal) */
dkato 0:853f5b7408a7 408 *(vdec_reg->dcpcr8) = (uint16_t)((uint32_t)p_center_clamp->dcppos_c << VEDC_REG_SHIFT_8);
dkato 0:853f5b7408a7 409 }
dkato 0:853f5b7408a7 410 /* Noise detection */
dkato 0:853f5b7408a7 411 if (p_noise_det != NULL) {
dkato 0:853f5b7408a7 412 /* Video signal for autocorrelation function */
dkato 0:853f5b7408a7 413 reg_data = (uint32_t)p_noise_det->acfinput << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 414 /* Delay time for autocorrelation function calculation */
dkato 0:853f5b7408a7 415 reg_data |= (uint32_t)p_noise_det->acflagtime << VEDC_REG_SHIFT_4;
dkato 0:853f5b7408a7 416 /* Smoothing parameter of autocorrelation function data */
dkato 0:853f5b7408a7 417 reg_data |= (uint32_t)p_noise_det->acffilter;
dkato 0:853f5b7408a7 418
dkato 0:853f5b7408a7 419 *(vdec_reg->nsdcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 420 }
dkato 0:853f5b7408a7 421 /* Clamp data hold processing (Y, Cb, Cr) OFF */
dkato 0:853f5b7408a7 422 reg_data = (uint32_t)*(vdec_reg->dcpcr9) & (uint32_t)(~VDEC_REG_MASK_0X1C00);
dkato 0:853f5b7408a7 423 *(vdec_reg->dcpcr9) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 424
dkato 0:853f5b7408a7 425 return;
dkato 0:853f5b7408a7 426 } /* End of function VDEC_DigitalClamp() */
dkato 0:853f5b7408a7 427
dkato 0:853f5b7408a7 428 /**************************************************************************//**
dkato 0:853f5b7408a7 429 * @brief Sets registers for output adjustment
dkato 0:853f5b7408a7 430 * @param[in] ch : Channel
dkato 0:853f5b7408a7 431 * @param[in] param : Output adjustment parameter
dkato 0:853f5b7408a7 432 * @retval None
dkato 0:853f5b7408a7 433 *****************************************************************************/
dkato 0:853f5b7408a7 434 void VDEC_Output (const vdec_channel_t ch, const vdec_output_t * const param)
dkato 0:853f5b7408a7 435 {
dkato 0:853f5b7408a7 436 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 437
dkato 0:853f5b7408a7 438 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 439
dkato 0:853f5b7408a7 440 /* Y, Cb and Cr signal gain coefficient */
dkato 0:853f5b7408a7 441 *(vdec_reg->ygaincr) = param->y_gain2;
dkato 0:853f5b7408a7 442 *(vdec_reg->cbgaincr) = param->cb_gain2;
dkato 0:853f5b7408a7 443 *(vdec_reg->crgaincr) = param->cr_gain2;
dkato 0:853f5b7408a7 444
dkato 0:853f5b7408a7 445 return;
dkato 0:853f5b7408a7 446 } /* End of function VDEC_Output() */
dkato 0:853f5b7408a7 447
dkato 0:853f5b7408a7 448 /**************************************************************************//**
dkato 0:853f5b7408a7 449 * @brief Query VDEC parameters
dkato 0:853f5b7408a7 450 * @param[in] ch : Channel
dkato 0:853f5b7408a7 451 * @param[out] q_sync_sep : Sync separation parameters
dkato 0:853f5b7408a7 452 * @param[out] q_agc : Agc parameters
dkato 0:853f5b7408a7 453 * @param[out] q_chroma_dec : Chroma decoding parameters
dkato 0:853f5b7408a7 454 * @param[out] q_digital_clamp : Digital clamp parameters
dkato 0:853f5b7408a7 455 * @retval None
dkato 0:853f5b7408a7 456 *****************************************************************************/
dkato 0:853f5b7408a7 457 void VDEC_Query (
dkato 0:853f5b7408a7 458 const vdec_channel_t ch,
dkato 0:853f5b7408a7 459 vdec_q_sync_sep_t * const q_sync_sep,
dkato 0:853f5b7408a7 460 vdec_q_agc_t * const q_agc,
dkato 0:853f5b7408a7 461 vdec_q_chroma_dec_t * const q_chroma_dec,
dkato 0:853f5b7408a7 462 vdec_q_digital_clamp_t * const q_digital_clamp)
dkato 0:853f5b7408a7 463 {
dkato 0:853f5b7408a7 464 const vdec_reg_address_t * vdec_reg;
dkato 0:853f5b7408a7 465 uint32_t reg_value;
dkato 0:853f5b7408a7 466
dkato 0:853f5b7408a7 467 vdec_reg = &vdec_reg_address[ch];
dkato 0:853f5b7408a7 468
dkato 0:853f5b7408a7 469 /* Sync separation */
dkato 0:853f5b7408a7 470 if (q_sync_sep != NULL) {
dkato 0:853f5b7408a7 471 reg_value = (uint32_t)*(vdec_reg->vsyncsr);
dkato 0:853f5b7408a7 472 /* Horizontal AFC lock detection result */
dkato 0:853f5b7408a7 473 q_sync_sep->fhlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X4000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
dkato 0:853f5b7408a7 474 /* Detection result of low S/N signal by sync separation */
dkato 0:853f5b7408a7 475 q_sync_sep->isnoisy = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_NO : VDEC_YES;
dkato 0:853f5b7408a7 476 /* Speed detection result */
dkato 0:853f5b7408a7 477 q_sync_sep->fhmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_FHMD_NORMAL :
dkato 0:853f5b7408a7 478 VDEC_FHMD_MULTIPLIED;
dkato 0:853f5b7408a7 479 /* No-signal detection result */
dkato 0:853f5b7408a7 480 q_sync_sep->nosignal_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
dkato 0:853f5b7408a7 481 /* Vertical countdown lock detection result */
dkato 0:853f5b7408a7 482 q_sync_sep->fvlock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
dkato 0:853f5b7408a7 483 /* Vertical countdown oscillation mode */
dkato 0:853f5b7408a7 484 q_sync_sep->fvmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0200) == 0u) ? VDEC_FVMD_50HZ :
dkato 0:853f5b7408a7 485 VDEC_FVMD_60HZ;
dkato 0:853f5b7408a7 486 /* Interlace detection result */
dkato 0:853f5b7408a7 487 q_sync_sep->interlaced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) ? VDEC_NO : VDEC_YES;
dkato 0:853f5b7408a7 488 /* Vertical cycle measurement result */
dkato 0:853f5b7408a7 489 q_sync_sep->fvcount = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
dkato 0:853f5b7408a7 490 /* Horizontal AFC oscillation cycle */
dkato 0:853f5b7408a7 491 q_sync_sep->fhcount = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X8000) == 0u) ? 0x0000u : (uint32_t)0x0001u;
dkato 0:853f5b7408a7 492 q_sync_sep->fhcount |= (uint32_t)*(vdec_reg->hsyncsr) << VEDC_REG_SHIFT_1;
dkato 0:853f5b7408a7 493
dkato 0:853f5b7408a7 494 reg_value = (uint32_t)*(vdec_reg->syncssr);
dkato 0:853f5b7408a7 495 /* Sync amplitude detection result during VBI period */
dkato 0:853f5b7408a7 496 q_sync_sep->isreduced = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
dkato 0:853f5b7408a7 497 /* Sync pulse amplitude detection result */
dkato 0:853f5b7408a7 498 q_sync_sep->syncdepth = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
dkato 0:853f5b7408a7 499 }
dkato 0:853f5b7408a7 500 /* Agc */
dkato 0:853f5b7408a7 501 if (q_agc != NULL) {
dkato 0:853f5b7408a7 502 reg_value = (uint32_t)*(vdec_reg->agccsr1);
dkato 0:853f5b7408a7 503 /* Number of pixels which have larger luminance value than peak luminance limited by peak limiter */
dkato 0:853f5b7408a7 504 q_agc->highsamples = (uint16_t)(reg_value >> VEDC_REG_SHIFT_8);
dkato 0:853f5b7408a7 505 /* Number of overflowing pixels */
dkato 0:853f5b7408a7 506 q_agc->peaksamples = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
dkato 0:853f5b7408a7 507
dkato 0:853f5b7408a7 508 reg_value = (uint32_t)*(vdec_reg->agccsr2);
dkato 0:853f5b7408a7 509 /* AGC convergence detection result */
dkato 0:853f5b7408a7 510 if ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0100) == 0u) {
dkato 0:853f5b7408a7 511 q_agc->agcconverge = (uint16_t)0x0000u;
dkato 0:853f5b7408a7 512 } else {
dkato 0:853f5b7408a7 513 q_agc->agcconverge = (uint16_t)0x0001u;
dkato 0:853f5b7408a7 514 }
dkato 0:853f5b7408a7 515 /* Current AGC gain value */
dkato 0:853f5b7408a7 516 q_agc->agcgain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
dkato 0:853f5b7408a7 517 }
dkato 0:853f5b7408a7 518 /* Chroma decoding */
dkato 0:853f5b7408a7 519 if (q_chroma_dec != NULL) {
dkato 0:853f5b7408a7 520 reg_value = (uint32_t)*(vdec_reg->cromasr1);
dkato 0:853f5b7408a7 521 /* Color system detection result */
dkato 0:853f5b7408a7 522 q_chroma_dec->colorsys = (vdec_color_sys_t)(reg_value >> VEDC_REG_SHIFT_14);
dkato 0:853f5b7408a7 523 /* Color sub-carrier frequency detection result */
dkato 0:853f5b7408a7 524 q_chroma_dec->fscmode = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X2000) == 0u) ? VDEC_FSCMD_3_58 :
dkato 0:853f5b7408a7 525 VDEC_FSCMD_4_43;
dkato 0:853f5b7408a7 526 /* Burst lock PLL lock state detection result */
dkato 0:853f5b7408a7 527 q_chroma_dec->fsclock = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_UNLOCK : VDEC_LOCK;
dkato 0:853f5b7408a7 528 /* Color burst detection result */
dkato 0:853f5b7408a7 529 q_chroma_dec->noburst_ = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_YES : VDEC_NO;
dkato 0:853f5b7408a7 530 /* Current ACC gain value (sub) */
dkato 0:853f5b7408a7 531 q_chroma_dec->accsubgain = (vdec_chrm_subgain_t)((reg_value >> VEDC_REG_SHIFT_9) &
dkato 0:853f5b7408a7 532 (uint32_t)VDEC_REG_MASK_0X0003);
dkato 0:853f5b7408a7 533 /* Current ACC gain value (main) */
dkato 0:853f5b7408a7 534 q_chroma_dec->accmaingain = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X01FF);
dkato 0:853f5b7408a7 535
dkato 0:853f5b7408a7 536 reg_value = (uint32_t)*(vdec_reg->cromasr2);
dkato 0:853f5b7408a7 537 /* SECAM detection result */
dkato 0:853f5b7408a7 538 q_chroma_dec->issecam = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X1000) == 0u) ? VDEC_NO : VDEC_YES;
dkato 0:853f5b7408a7 539 /* PAL detection result */
dkato 0:853f5b7408a7 540 q_chroma_dec->ispal = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0800) == 0u) ? VDEC_NO : VDEC_YES;
dkato 0:853f5b7408a7 541 /* NTSC detection result */
dkato 0:853f5b7408a7 542 q_chroma_dec->isntsc = ((reg_value & (uint32_t)VDEC_REG_BIT_MASK_0X0400) == 0u) ? VDEC_NO : VDEC_YES;
dkato 0:853f5b7408a7 543 /* Low S/N signal detection result by burst lock PLL */
dkato 0:853f5b7408a7 544 q_chroma_dec->locklevel = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X00FF);
dkato 0:853f5b7408a7 545 }
dkato 0:853f5b7408a7 546 /* Digital clamp */
dkato 0:853f5b7408a7 547 if (q_digital_clamp != NULL) {
dkato 0:853f5b7408a7 548 reg_value = (uint32_t)*(vdec_reg->dcpsr1);
dkato 0:853f5b7408a7 549 /* Digital clamp subtraction value (Cb signal) */
dkato 0:853f5b7408a7 550 q_digital_clamp->clamplevel_cb = (uint16_t)(reg_value >> VEDC_REG_SHIFT_10);
dkato 0:853f5b7408a7 551 /* Digital clamp subtraction value (Y signal) */
dkato 0:853f5b7408a7 552 q_digital_clamp->clamplevel_y = (uint16_t)(reg_value & (uint32_t)VDEC_REG_MASK_0X03FF);
dkato 0:853f5b7408a7 553
dkato 0:853f5b7408a7 554 /* Digital clamp subtraction value (Cr signal) */
dkato 0:853f5b7408a7 555 q_digital_clamp->clamplevel_cr = (uint16_t)((uint32_t)*(vdec_reg->dcpsr2) >> VEDC_REG_SHIFT_10);
dkato 0:853f5b7408a7 556
dkato 0:853f5b7408a7 557 /* Noise autocorrelation strength at digital clamp pulse position */
dkato 0:853f5b7408a7 558 q_digital_clamp->acfstrength = *(vdec_reg->nsdsr);
dkato 0:853f5b7408a7 559 }
dkato 0:853f5b7408a7 560 return;
dkato 0:853f5b7408a7 561 } /* End of function VDEC_Query() */
dkato 0:853f5b7408a7 562
dkato 0:853f5b7408a7 563 /**************************************************************************//**
dkato 0:853f5b7408a7 564 * @brief Sets registers for noise reduction LPF
dkato 0:853f5b7408a7 565 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 566 * @param[in] p_noise_rd_lpf : Noise reduction LPF parameter
dkato 0:853f5b7408a7 567 * @retval None
dkato 0:853f5b7408a7 568 *****************************************************************************/
dkato 0:853f5b7408a7 569 static void NoiseReductionLPF (
dkato 0:853f5b7408a7 570 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 571 const vdec_noise_rd_lpf_t * const p_noise_rd_lpf)
dkato 0:853f5b7408a7 572 {
dkato 0:853f5b7408a7 573 uint32_t reg_data;
dkato 0:853f5b7408a7 574
dkato 0:853f5b7408a7 575 /* Noise reduction LPF */
dkato 0:853f5b7408a7 576 if (p_noise_rd_lpf != NULL) {
dkato 0:853f5b7408a7 577 reg_data = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0XFC00);
dkato 0:853f5b7408a7 578 /* LPF cutoff frequency before vertical sync separation */
dkato 0:853f5b7408a7 579 reg_data |= (uint32_t)p_noise_rd_lpf->lpfvsync << VEDC_REG_SHIFT_13;
dkato 0:853f5b7408a7 580 /* LPF cutoff frequency before horizontal sync separation */
dkato 0:853f5b7408a7 581 reg_data |= (uint32_t)p_noise_rd_lpf->lpfhsync << VEDC_REG_SHIFT_10;
dkato 0:853f5b7408a7 582
dkato 0:853f5b7408a7 583 *(vdec_reg->synscr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 584 }
dkato 0:853f5b7408a7 585 return;
dkato 0:853f5b7408a7 586 } /* End of function NoiseReductionLPF() */
dkato 0:853f5b7408a7 587
dkato 0:853f5b7408a7 588 /**************************************************************************//**
dkato 0:853f5b7408a7 589 * @brief Sets registers for auto level control sync slicer
dkato 0:853f5b7408a7 590 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 591 * @param[in] p_sync_slicer : Auto level control sync slicer parameter
dkato 0:853f5b7408a7 592 * @retval None
dkato 0:853f5b7408a7 593 *****************************************************************************/
dkato 0:853f5b7408a7 594 static void SyncSlicer (const vdec_reg_address_t * const vdec_reg, const vdec_sync_slicer_t * const p_sync_slicer)
dkato 0:853f5b7408a7 595 {
dkato 0:853f5b7408a7 596 uint32_t reg_data;
dkato 0:853f5b7408a7 597
dkato 0:853f5b7408a7 598 /* Auto level control sync slicer */
dkato 0:853f5b7408a7 599 if (p_sync_slicer != NULL) {
dkato 0:853f5b7408a7 600 reg_data = (uint32_t)*(vdec_reg->synscr1) & (uint32_t)(~VDEC_REG_MASK_0X00FF);
dkato 0:853f5b7408a7 601 /* Reference level operation speed control for composite sync separation (for Hsync signal) */
dkato 0:853f5b7408a7 602 reg_data |= (uint32_t)p_sync_slicer->velocityshift_h << VEDC_REG_SHIFT_4;
dkato 0:853f5b7408a7 603 /* Auto-slice level setting for composite sync separation circuit (for Hsync signal) */
dkato 0:853f5b7408a7 604 reg_data |= (uint32_t)p_sync_slicer->slicermode_h << VEDC_REG_SHIFT_2;
dkato 0:853f5b7408a7 605 /* Auto-slice level setting for composite sync separation circuit (for Vsync signal) */
dkato 0:853f5b7408a7 606 reg_data |= (uint32_t)p_sync_slicer->slicermode_v;
dkato 0:853f5b7408a7 607
dkato 0:853f5b7408a7 608 *(vdec_reg->synscr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 609
dkato 0:853f5b7408a7 610 /* Max ratio of horizontal cycle to horizontal sync signal pulse width
dkato 0:853f5b7408a7 611 and min ratio of horizontal cycle to horizontal sync signal pulse width (for Hsync signal) */
dkato 0:853f5b7408a7 612 reg_data = (uint32_t)p_sync_slicer->syncmaxduty_h << VEDC_REG_SHIFT_6;
dkato 0:853f5b7408a7 613 reg_data |= (uint32_t)p_sync_slicer->syncminduty_h;
dkato 0:853f5b7408a7 614
dkato 0:853f5b7408a7 615 *(vdec_reg->synscr2) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 616
dkato 0:853f5b7408a7 617 /* Clipping level and slice level for composite sync signal separation (for Hsync signal) */
dkato 0:853f5b7408a7 618 reg_data = (uint32_t)p_sync_slicer->ssclipsel << VEDC_REG_SHIFT_10;
dkato 0:853f5b7408a7 619 reg_data |= (uint32_t)p_sync_slicer->csyncslice_h;
dkato 0:853f5b7408a7 620
dkato 0:853f5b7408a7 621 *(vdec_reg->synscr3) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 622
dkato 0:853f5b7408a7 623 /* Max ratio of horizontal cycle to horizontal sync signal pulse width
dkato 0:853f5b7408a7 624 and min ratio of horizontal cycle to horizontal sync signal pulse width (for Vsync signal) */
dkato 0:853f5b7408a7 625 reg_data = (uint32_t)p_sync_slicer->syncmaxduty_v << VEDC_REG_SHIFT_6;
dkato 0:853f5b7408a7 626 reg_data |= (uint32_t)p_sync_slicer->syncminduty_v;
dkato 0:853f5b7408a7 627
dkato 0:853f5b7408a7 628 *(vdec_reg->synscr4) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 629
dkato 0:853f5b7408a7 630 /* Delays the separated vertical sync signal for 1/4 horizontal cycle */
dkato 0:853f5b7408a7 631 reg_data = (p_sync_slicer->vsyncdelay == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
dkato 0:853f5b7408a7 632 /* Threshold for vertical sync separation */
dkato 0:853f5b7408a7 633 reg_data |= (uint32_t)p_sync_slicer->vsyncslice << VEDC_REG_SHIFT_10;
dkato 0:853f5b7408a7 634 /* Slice level for composite sync signal separation (for Vsync signal) */
dkato 0:853f5b7408a7 635 reg_data |= (uint32_t)p_sync_slicer->csyncslice_v;
dkato 0:853f5b7408a7 636
dkato 0:853f5b7408a7 637 *(vdec_reg->synscr5) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 638 }
dkato 0:853f5b7408a7 639 return;
dkato 0:853f5b7408a7 640 } /* End of function SyncSlicer() */
dkato 0:853f5b7408a7 641
dkato 0:853f5b7408a7 642 /**************************************************************************//**
dkato 0:853f5b7408a7 643 * @brief Sets registers for horizontal AFC
dkato 0:853f5b7408a7 644 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 645 * @param[in] p_horizontal_afc : Horizontal AFC parameter
dkato 0:853f5b7408a7 646 * @retval None
dkato 0:853f5b7408a7 647 *****************************************************************************/
dkato 0:853f5b7408a7 648 static void HorizontalAFC (
dkato 0:853f5b7408a7 649 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 650 const vdec_horizontal_afc_t * const p_horizontal_afc)
dkato 0:853f5b7408a7 651 {
dkato 0:853f5b7408a7 652 uint32_t reg_data;
dkato 0:853f5b7408a7 653
dkato 0:853f5b7408a7 654 /* Horizontal AFC */
dkato 0:853f5b7408a7 655 if (p_horizontal_afc != NULL) {
dkato 0:853f5b7408a7 656 reg_data = (uint32_t)*(vdec_reg->hafccr1) & (uint32_t)(~VDEC_REG_MASK_0XF3FF);
dkato 0:853f5b7408a7 657 /* Horizontal AFC loop gain */
dkato 0:853f5b7408a7 658 reg_data |= (uint32_t)p_horizontal_afc->hafcgain << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 659 /* Horizontal AFC center oscillation frequency */
dkato 0:853f5b7408a7 660 reg_data |= (uint32_t)p_horizontal_afc->hafctyp;
dkato 0:853f5b7408a7 661
dkato 0:853f5b7408a7 662 *(vdec_reg->hafccr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 663
dkato 0:853f5b7408a7 664 /* Start line of horizontal AFC normal operation
dkato 0:853f5b7408a7 665 and Horizontal AFC forced double-speed oscillation (DOX2HOSC = 0, auto control) */
dkato 0:853f5b7408a7 666 reg_data = (uint32_t)p_horizontal_afc->hafcstart << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 667 /* Disable of horizontal AFC double speed detection */
dkato 0:853f5b7408a7 668 reg_data |= (p_horizontal_afc->nox2hosc == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0800;
dkato 0:853f5b7408a7 669 /* Maximum oscillation frequency of horizontal AFC */
dkato 0:853f5b7408a7 670 reg_data |= (uint32_t)p_horizontal_afc->hafcmax;
dkato 0:853f5b7408a7 671
dkato 0:853f5b7408a7 672 *(vdec_reg->hafccr2) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 673
dkato 0:853f5b7408a7 674 /* End line of horizontal AFC normal operation */
dkato 0:853f5b7408a7 675 reg_data = (uint32_t)p_horizontal_afc->hafcend << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 676 /* Horizontal AFC VBI period operating mode */
dkato 0:853f5b7408a7 677 reg_data |= (uint32_t)p_horizontal_afc->hafcmode << VEDC_REG_SHIFT_10;
dkato 0:853f5b7408a7 678 /* Min oscillation frequency of horizontal AFC */
dkato 0:853f5b7408a7 679 reg_data |= (uint32_t)p_horizontal_afc->hafcmin;
dkato 0:853f5b7408a7 680
dkato 0:853f5b7408a7 681 *(vdec_reg->hafccr3) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 682
dkato 0:853f5b7408a7 683 /* Forcible or LOWGAIN control */
dkato 0:853f5b7408a7 684 reg_data = (p_horizontal_afc->phdet_fix == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0010;
dkato 0:853f5b7408a7 685 /* Phase comparator feedback adjust for low sync signal lock stability */
dkato 0:853f5b7408a7 686 reg_data |= (uint32_t)p_horizontal_afc->phdet_div;
dkato 0:853f5b7408a7 687
dkato 0:853f5b7408a7 688 *(vdec_reg->afcpfcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 689 }
dkato 0:853f5b7408a7 690 return;
dkato 0:853f5b7408a7 691 } /* End of function HorizontalAFC() */
dkato 0:853f5b7408a7 692
dkato 0:853f5b7408a7 693 /**************************************************************************//**
dkato 0:853f5b7408a7 694 * @brief Sets registers for vertical count-down
dkato 0:853f5b7408a7 695 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 696 * @param[in] p_vcount_down : Vertical count-down parameter
dkato 0:853f5b7408a7 697 * @retval None
dkato 0:853f5b7408a7 698 *****************************************************************************/
dkato 0:853f5b7408a7 699 static void VerticalCountdown (
dkato 0:853f5b7408a7 700 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 701 const vdec_vcount_down_t * const p_vcount_down)
dkato 0:853f5b7408a7 702 {
dkato 0:853f5b7408a7 703 uint32_t reg_data;
dkato 0:853f5b7408a7 704
dkato 0:853f5b7408a7 705 /* Vertical count-down */
dkato 0:853f5b7408a7 706 if (p_vcount_down != NULL) {
dkato 0:853f5b7408a7 707 /* Vertical countdown 50-Hz oscillation mode
dkato 0:853f5b7408a7 708 and Vertical countdown free-run oscillation mode (VCDFREERUN = OFF) */
dkato 0:853f5b7408a7 709 reg_data = (p_vcount_down->novcd50_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X4000 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 710 /* Vertical countdown 60-Hz (59.94-Hz) oscillation mode */
dkato 0:853f5b7408a7 711 reg_data |= (p_vcount_down->novcd60_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X2000 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 712 /* Vertical countdown center oscillation frequency */
dkato 0:853f5b7408a7 713 reg_data |= (uint32_t)p_vcount_down->vcddefault << VEDC_REG_SHIFT_11;
dkato 0:853f5b7408a7 714 /* Vertical countdown sync area */
dkato 0:853f5b7408a7 715 reg_data |= (uint32_t)p_vcount_down->vcdwindow << VEDC_REG_SHIFT_5;
dkato 0:853f5b7408a7 716 /* Vertical countdown minimum oscillation frequency */
dkato 0:853f5b7408a7 717 reg_data |= (uint32_t)p_vcount_down->vcdoffset;
dkato 0:853f5b7408a7 718
dkato 0:853f5b7408a7 719 *(vdec_reg->vcdwcr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 720 }
dkato 0:853f5b7408a7 721 return;
dkato 0:853f5b7408a7 722 } /* End of function VerticalCountdown() */
dkato 0:853f5b7408a7 723
dkato 0:853f5b7408a7 724 /**************************************************************************//**
dkato 0:853f5b7408a7 725 * @brief Sets registers for AGC/PGA
dkato 0:853f5b7408a7 726 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 727 * @param[in] p_agc : AGC/PGA parameter
dkato 0:853f5b7408a7 728 * @retval None
dkato 0:853f5b7408a7 729 *****************************************************************************/
dkato 0:853f5b7408a7 730 static void AgcPga (const vdec_reg_address_t * const vdec_reg, const vdec_agc_t * const p_agc)
dkato 0:853f5b7408a7 731 {
dkato 0:853f5b7408a7 732 uint32_t reg_data;
dkato 0:853f5b7408a7 733
dkato 0:853f5b7408a7 734 /* AGC/PGA */
dkato 0:853f5b7408a7 735 if (p_agc != NULL) {
dkato 0:853f5b7408a7 736 /* A/D converter AGC ON/OFF control & PGA switch */
dkato 0:853f5b7408a7 737 if (p_agc->agcmode == VDEC_OFF) {
dkato 0:853f5b7408a7 738 reg_data = (uint32_t)*(vdec_reg->pgacr) | (uint32_t)VDEC_REG_SET_0X2000;
dkato 0:853f5b7408a7 739 *(vdec_reg->pgacr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 740 *(vdec_reg->adccr1) = (uint16_t)0u;
dkato 0:853f5b7408a7 741 } else {
dkato 0:853f5b7408a7 742 *(vdec_reg->adccr1) = (uint16_t)VDEC_REG_SET_0X0100;
dkato 0:853f5b7408a7 743 reg_data = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_SET_0X2000);
dkato 0:853f5b7408a7 744 *(vdec_reg->pgacr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 745 }
dkato 0:853f5b7408a7 746 /* PGA gain */
dkato 0:853f5b7408a7 747 reg_data = (uint32_t)*(vdec_reg->pgacr) & (uint32_t)(~VDEC_REG_MASK_0X1F00);
dkato 0:853f5b7408a7 748 reg_data |= (uint32_t)p_agc->pga_gain << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 749
dkato 0:853f5b7408a7 750 *(vdec_reg->pgacr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 751
dkato 0:853f5b7408a7 752 /* PGA register update register */
dkato 0:853f5b7408a7 753 *(vdec_reg->pga_update) = (uint16_t)1u;
dkato 0:853f5b7408a7 754
dkato 0:853f5b7408a7 755 /* Manual control of sync signal amplitude detection during VBI period */
dkato 0:853f5b7408a7 756 reg_data = (p_agc->doreduce == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X2000;
dkato 0:853f5b7408a7 757 /* Control of sync signal amplitude detection during VBI period */
dkato 0:853f5b7408a7 758 reg_data |= (p_agc->noreduce_ == VDEC_OFF) ? (uint32_t)VDEC_REG_SET_0X1000 : (uint32_t)0x0000u;
dkato 0:853f5b7408a7 759 /* AGC response speed */
dkato 0:853f5b7408a7 760 reg_data |= (uint32_t)p_agc->agcresponse << VEDC_REG_SHIFT_9;
dkato 0:853f5b7408a7 761 /* Sync signal reference amplitude */
dkato 0:853f5b7408a7 762 reg_data |= (uint32_t)p_agc->agclevel;
dkato 0:853f5b7408a7 763
dkato 0:853f5b7408a7 764 *(vdec_reg->agccr1) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 765
dkato 0:853f5b7408a7 766 /* AGC gain adjustment accuracy */
dkato 0:853f5b7408a7 767 reg_data = (uint32_t)*(vdec_reg->agccr2) & (uint32_t)(~VDEC_REG_MASK_0X3F00);
dkato 0:853f5b7408a7 768 reg_data |= (uint32_t)p_agc->agcprecis << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 769
dkato 0:853f5b7408a7 770 *(vdec_reg->agccr2) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 771 }
dkato 0:853f5b7408a7 772 return;
dkato 0:853f5b7408a7 773 } /* End of function AgcPga() */
dkato 0:853f5b7408a7 774
dkato 0:853f5b7408a7 775 /**************************************************************************//**
dkato 0:853f5b7408a7 776 * @brief Sets registers for peak limiter control
dkato 0:853f5b7408a7 777 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 778 * @param[in] p_peak_limiter : Peak limiter control parameter
dkato 0:853f5b7408a7 779 * @retval None
dkato 0:853f5b7408a7 780 *****************************************************************************/
dkato 0:853f5b7408a7 781 static void PeakLimiterControl (
dkato 0:853f5b7408a7 782 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 783 const vdec_peak_limiter_t * const p_peak_limiter)
dkato 0:853f5b7408a7 784 {
dkato 0:853f5b7408a7 785 uint32_t reg_data;
dkato 0:853f5b7408a7 786
dkato 0:853f5b7408a7 787 /* Peak limiter control */
dkato 0:853f5b7408a7 788 if (p_peak_limiter != NULL) {
dkato 0:853f5b7408a7 789 /* Peak luminance value limited by peak limiter */
dkato 0:853f5b7408a7 790 reg_data = (uint32_t)p_peak_limiter->peaklevel << VEDC_REG_SHIFT_14;
dkato 0:853f5b7408a7 791 /* Response speed with peak limiter gain decreased */
dkato 0:853f5b7408a7 792 reg_data |= (uint32_t)p_peak_limiter->peakattack << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 793 /* Response speed with peak limiter gain increased */
dkato 0:853f5b7408a7 794 reg_data |= (uint32_t)p_peak_limiter->peakrelease << VEDC_REG_SHIFT_10;
dkato 0:853f5b7408a7 795 /* Maximum compression rate of peak limiter */
dkato 0:853f5b7408a7 796 reg_data |= (uint32_t)p_peak_limiter->peakratio << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 797 /* Allowable number of overflowing pixels */
dkato 0:853f5b7408a7 798 reg_data |= (uint32_t)p_peak_limiter->maxpeaksamples;
dkato 0:853f5b7408a7 799
dkato 0:853f5b7408a7 800 *(vdec_reg->pklimitcr) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 801 }
dkato 0:853f5b7408a7 802 return;
dkato 0:853f5b7408a7 803 } /* End of function PeakLimiterControl() */
dkato 0:853f5b7408a7 804
dkato 0:853f5b7408a7 805 /**************************************************************************//**
dkato 0:853f5b7408a7 806 * @brief Sets registers for over-range control
dkato 0:853f5b7408a7 807 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 808 * @param[in] p_over_range : Over-range control parameter
dkato 0:853f5b7408a7 809 * @retval None
dkato 0:853f5b7408a7 810 *****************************************************************************/
dkato 0:853f5b7408a7 811 static void OverRangeControl (const vdec_reg_address_t * const vdec_reg, const vdec_over_range_t * const p_over_range)
dkato 0:853f5b7408a7 812 {
dkato 0:853f5b7408a7 813 uint32_t reg_data;
dkato 0:853f5b7408a7 814
dkato 0:853f5b7408a7 815 /* Over-range control */
dkato 0:853f5b7408a7 816 if (p_over_range != NULL) {
dkato 0:853f5b7408a7 817 /* A/D over-threshold level (between levels 0 and 1) */
dkato 0:853f5b7408a7 818 *(vdec_reg->rgorcr1) = p_over_range->radj_o_level0;
dkato 0:853f5b7408a7 819 /* A/D under-threshold level (between levels 2 and 3) */
dkato 0:853f5b7408a7 820 *(vdec_reg->rgorcr2) = p_over_range->radj_u_level0;
dkato 0:853f5b7408a7 821 /* A/D over-threshold level (between levels 1 and 2) */
dkato 0:853f5b7408a7 822 *(vdec_reg->rgorcr3) = p_over_range->radj_o_level1;
dkato 0:853f5b7408a7 823 /* A/D under-threshold level (between levels 1 and 2) */
dkato 0:853f5b7408a7 824 *(vdec_reg->rgorcr4) = p_over_range->radj_u_level1;
dkato 0:853f5b7408a7 825 /* A/D over-threshold level (between levels 2 and 3) */
dkato 0:853f5b7408a7 826 *(vdec_reg->rgorcr5) = p_over_range->radj_o_level2;
dkato 0:853f5b7408a7 827 /* A/D under-threshold level (between levels 0 and 1) */
dkato 0:853f5b7408a7 828 *(vdec_reg->rgorcr6) = p_over_range->radj_u_level2;
dkato 0:853f5b7408a7 829
dkato 0:853f5b7408a7 830 reg_data = (uint32_t)*(vdec_reg->rgorcr7) & (uint32_t)(~VDEC_REG_MASK_0X0007);
dkato 0:853f5b7408a7 831 /* Over-range detection enable */
dkato 0:853f5b7408a7 832 reg_data |= (p_over_range->ucmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0004;
dkato 0:853f5b7408a7 833 /* Under-range detection enable */
dkato 0:853f5b7408a7 834 reg_data |= (p_over_range->dcmp_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X0002;
dkato 0:853f5b7408a7 835 /* Horizontal enlargement of over/under-range level */
dkato 0:853f5b7408a7 836 reg_data |= (p_over_range->hwide_sw == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)0x0001u;
dkato 0:853f5b7408a7 837
dkato 0:853f5b7408a7 838 *(vdec_reg->rgorcr7) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 839 }
dkato 0:853f5b7408a7 840 return;
dkato 0:853f5b7408a7 841 } /* End of function OverRangeControl() */
dkato 0:853f5b7408a7 842
dkato 0:853f5b7408a7 843 /**************************************************************************//**
dkato 0:853f5b7408a7 844 * @brief Sets registers for Y/C separation control
dkato 0:853f5b7408a7 845 * @param[in] vdec_reg : VDEC registers
dkato 0:853f5b7408a7 846 * @param[in] p_yc_sep_ctrl : Y/C separation control parameter
dkato 0:853f5b7408a7 847 * @retval None
dkato 0:853f5b7408a7 848 *****************************************************************************/
dkato 0:853f5b7408a7 849 static void YcSeparationControl (
dkato 0:853f5b7408a7 850 const vdec_reg_address_t * const vdec_reg,
dkato 0:853f5b7408a7 851 const vdec_yc_sep_ctrl_t * const p_yc_sep_ctrl)
dkato 0:853f5b7408a7 852 {
dkato 0:853f5b7408a7 853 uint32_t reg_data;
dkato 0:853f5b7408a7 854
dkato 0:853f5b7408a7 855 /* Y/C separation control */
dkato 0:853f5b7408a7 856 if (p_yc_sep_ctrl != NULL) {
dkato 0:853f5b7408a7 857 /* Two-dimensional Y/C separation filter select coefficient (K15, K13, and K11) */
dkato 0:853f5b7408a7 858 reg_data = (uint32_t)p_yc_sep_ctrl->k15 << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 859 reg_data |= (uint32_t)p_yc_sep_ctrl->k13 << VEDC_REG_SHIFT_6;
dkato 0:853f5b7408a7 860 reg_data |= (uint32_t)p_yc_sep_ctrl->k11;
dkato 0:853f5b7408a7 861
dkato 0:853f5b7408a7 862 *(vdec_reg->ycscr3) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 863
dkato 0:853f5b7408a7 864 /* Two-dimensional Y/C separation filter select coefficient (K16, K14, and K12) */
dkato 0:853f5b7408a7 865 reg_data = (uint32_t)p_yc_sep_ctrl->k16 << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 866 reg_data |= (uint32_t)p_yc_sep_ctrl->k14 << VEDC_REG_SHIFT_6;
dkato 0:853f5b7408a7 867 reg_data |= (uint32_t)p_yc_sep_ctrl->k12;
dkato 0:853f5b7408a7 868
dkato 0:853f5b7408a7 869 *(vdec_reg->ycscr4) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 870
dkato 0:853f5b7408a7 871 /* Two-dimensional Y/C separation filter select coefficient (K22A and K21A) */
dkato 0:853f5b7408a7 872 reg_data = (uint32_t)p_yc_sep_ctrl->k22a << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 873 reg_data |= (uint32_t)p_yc_sep_ctrl->k21a;
dkato 0:853f5b7408a7 874
dkato 0:853f5b7408a7 875 *(vdec_reg->ycscr5) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 876
dkato 0:853f5b7408a7 877 /* Two-dimensional Y/C separation filter select coefficient (K22B and K21B) */
dkato 0:853f5b7408a7 878 reg_data = (uint32_t)p_yc_sep_ctrl->k22b << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 879 reg_data |= (uint32_t)p_yc_sep_ctrl->k21b;
dkato 0:853f5b7408a7 880
dkato 0:853f5b7408a7 881 *(vdec_reg->ycscr6) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 882
dkato 0:853f5b7408a7 883 /* Two-dimensional Y/C separation filter select coefficient (K23B, K23A, and K24) */
dkato 0:853f5b7408a7 884 reg_data = (uint32_t)*(vdec_reg->ycscr7) & (uint32_t)(~VDEC_REG_MASK_0XFF1F);
dkato 0:853f5b7408a7 885 reg_data |= (uint32_t)p_yc_sep_ctrl->k23b << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 886 reg_data |= (uint32_t)p_yc_sep_ctrl->k23a << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 887 reg_data |= (uint32_t)p_yc_sep_ctrl->k24;
dkato 0:853f5b7408a7 888
dkato 0:853f5b7408a7 889 *(vdec_reg->ycscr7) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 890
dkato 0:853f5b7408a7 891 reg_data = (uint32_t)*(vdec_reg->ycscr8) & (uint32_t)(~VDEC_REG_MASK_0XF800);
dkato 0:853f5b7408a7 892 /* Latter-stage horizontal BPF select */
dkato 0:853f5b7408a7 893 reg_data |= (p_yc_sep_ctrl->hbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 894 (uint32_t)VDEC_REG_SET_0X8000;
dkato 0:853f5b7408a7 895 /* Latter-stage horizontal/vertical BPF select */
dkato 0:853f5b7408a7 896 reg_data |= (p_yc_sep_ctrl->hvbpf_narrow == VDEC_LSTG_BPFSEL_BYPASS) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 897 (uint32_t)VDEC_REG_SET_0X4000;
dkato 0:853f5b7408a7 898 /* Former-stage horizontal BPF select */
dkato 0:853f5b7408a7 899 reg_data |= (p_yc_sep_ctrl->hbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 900 (uint32_t)VDEC_REG_SET_0X2000;
dkato 0:853f5b7408a7 901 /* Former-stage horizontal/vertical BPF select */
dkato 0:853f5b7408a7 902 reg_data |= (p_yc_sep_ctrl->hvbpf1_9tap_on == VDEC_FSTG_BPFSEL_17TAP) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 903 (uint32_t)VDEC_REG_SET_0X1000;
dkato 0:853f5b7408a7 904 /* Horizontal filter and horizontal/vertical filter bandwidth switch signal */
dkato 0:853f5b7408a7 905 reg_data |= (p_yc_sep_ctrl->hfil_tap_sel == VDEC_HFIL_TAP_SEL_17TAP) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 906 (uint32_t)VDEC_REG_SET_0X0800;
dkato 0:853f5b7408a7 907
dkato 0:853f5b7408a7 908 *(vdec_reg->ycscr8) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 909
dkato 0:853f5b7408a7 910 /* Two-dimensional filter mixing select */
dkato 0:853f5b7408a7 911 reg_data = (p_yc_sep_ctrl->det2_on == VDEC_OFF) ? (uint32_t)0x0000u : (uint32_t)VDEC_REG_SET_0X8000;
dkato 0:853f5b7408a7 912 /* Mixing ratio of signal after passing horizontal filter
dkato 0:853f5b7408a7 913 to signal after passing former-stage horizontal filter */
dkato 0:853f5b7408a7 914 reg_data |= (uint32_t)p_yc_sep_ctrl->hsel_mix_y << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 915 /* Mixing ratio of signal after passing vertical filter
dkato 0:853f5b7408a7 916 to signal after passing former-stage horizontal/vertical filter */
dkato 0:853f5b7408a7 917 reg_data |= (uint32_t)p_yc_sep_ctrl->vsel_mix_y << VEDC_REG_SHIFT_4;
dkato 0:853f5b7408a7 918 /* Mixing ratio of signal after passing horizontal/vertical filter
dkato 0:853f5b7408a7 919 to signal after passing former-stage horizontal/vertical filter */
dkato 0:853f5b7408a7 920 reg_data |= (uint32_t)p_yc_sep_ctrl->hvsel_mix_y;
dkato 0:853f5b7408a7 921
dkato 0:853f5b7408a7 922 *(vdec_reg->ycscr9) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 923
dkato 0:853f5b7408a7 924 /* Vertical luminance detection level for correlation detection filter */
dkato 0:853f5b7408a7 925 reg_data = (uint32_t)*(vdec_reg->ycscr11) & (uint32_t)(~VDEC_REG_MASK_0X01FF);
dkato 0:853f5b7408a7 926 reg_data |= (uint32_t)p_yc_sep_ctrl->v_y_level;
dkato 0:853f5b7408a7 927
dkato 0:853f5b7408a7 928 *(vdec_reg->ycscr11) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 929
dkato 0:853f5b7408a7 930 if (p_yc_sep_ctrl->det2_on == VDEC_OFF) {
dkato 0:853f5b7408a7 931 reg_data = ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_12) |
dkato 0:853f5b7408a7 932 ((uint32_t)VDEC_FILMIX_RATIO_0 << VEDC_REG_SHIFT_8);
dkato 0:853f5b7408a7 933 } else {
dkato 0:853f5b7408a7 934 /* Mixing ratio of C signal after passing horizontal/vertical adaptive filter
dkato 0:853f5b7408a7 935 to signal after passing correlation detection filter */
dkato 0:853f5b7408a7 936 reg_data = (uint32_t)p_yc_sep_ctrl->det2_mix_c << VEDC_REG_SHIFT_12;
dkato 0:853f5b7408a7 937 /* Mixing ratio of C signal for Y generation after passing
dkato 0:853f5b7408a7 938 horizontal/vertical adaptive filter to signal after passing correlation */
dkato 0:853f5b7408a7 939 reg_data |= (uint32_t)p_yc_sep_ctrl->det2_mix_y << VEDC_REG_SHIFT_8;
dkato 0:853f5b7408a7 940 }
dkato 0:853f5b7408a7 941 /* Two-dimensional cascade/TAKE-OFF filter mode select */
dkato 0:853f5b7408a7 942 reg_data |= (uint32_t)p_yc_sep_ctrl->fil2_mode_2d << VEDC_REG_SHIFT_2;
dkato 0:853f5b7408a7 943 /* Two-dimensional cascade filter select */
dkato 0:853f5b7408a7 944 reg_data |= (p_yc_sep_ctrl->fil2_narrow_2d == VDEC_2D_FIL_SEL_BYPASS) ? (uint32_t)0x0000u :
dkato 0:853f5b7408a7 945 (uint32_t)0x0001u;
dkato 0:853f5b7408a7 946
dkato 0:853f5b7408a7 947 *(vdec_reg->ycscr12) = (uint16_t)reg_data;
dkato 0:853f5b7408a7 948 }
dkato 0:853f5b7408a7 949 return;
dkato 0:853f5b7408a7 950 } /* End of function YcSeparationControl() */
dkato 0:853f5b7408a7 951
dkato 0:853f5b7408a7 952 /**************************************************************************//**
dkato 0:853f5b7408a7 953 * @brief Sets registers for chroma filter TAP coefficient
dkato 0:853f5b7408a7 954 * @param[in] fil_reg_address : 2D filter TAP coefficient registers
dkato 0:853f5b7408a7 955 * @param[in] fil2_2d : Chroma filter TAP coefficient for Y/C separation
dkato 0:853f5b7408a7 956 * @retval None
dkato 0:853f5b7408a7 957 *****************************************************************************/
dkato 0:853f5b7408a7 958 static void FilterTAPsCoefficient (
dkato 0:853f5b7408a7 959 volatile uint16_t * const * fil_reg_address,
dkato 0:853f5b7408a7 960 const vdec_chrfil_tap_t * const fil2_2d)
dkato 0:853f5b7408a7 961 {
dkato 0:853f5b7408a7 962 int32_t tap_coef;
dkato 0:853f5b7408a7 963 volatile uint16_t * fil_reg;
dkato 0:853f5b7408a7 964 const uint16_t * taps;
dkato 0:853f5b7408a7 965
dkato 0:853f5b7408a7 966 if (fil2_2d != NULL) {
dkato 0:853f5b7408a7 967 taps = fil2_2d->fil2_2d_f;
dkato 0:853f5b7408a7 968 for (tap_coef = 0; tap_coef < VDEC_CHRFIL_TAPCOEF_NUM; tap_coef++) {
dkato 0:853f5b7408a7 969 fil_reg = *fil_reg_address;
dkato 0:853f5b7408a7 970 fil_reg_address++;
dkato 0:853f5b7408a7 971 *fil_reg = *taps;
dkato 0:853f5b7408a7 972 taps++;
dkato 0:853f5b7408a7 973 }
dkato 0:853f5b7408a7 974 }
dkato 0:853f5b7408a7 975 return;
dkato 0:853f5b7408a7 976 } /* End of function FilterTAPsCoefficient() */
dkato 0:853f5b7408a7 977