Kazuki Yamamoto / Mbed 2 deprecated uart_i2c_conv

UART to I2C master(s) converter, targetting to emulate SC18IM700(NXP) chip

Dependencies:   mbed

UART to I2C master(s) converter, targetting to emulate SC18IM700(NXP) chip

Features

up to 4x I2C master

  • for LPC824 implement, we can use up to 4 channels of I2C masters
    • 1x Fm+ and 3x Fm I2C channels
  • for LPC1768 implement, we can use up to 2 channels of I2C masters
    • 2x Fm I2C channels
  • for LPC11U35 implement, only one channel for I2C master, but program uses USB CDC class for UART communication (means no external USB-Serial converter chip)
    • 1x Fm+ I2C channels

1x SPI master

up to 2x 8bit GPIO

Tested Platforms

LPC824

LPC1768

LPC11U35

Quote:

LPC11U35 implement requires importing USBDevice library to use USBSerial class

visit https://github.com/K4zuki/tinyI2C for more information

main.cpp@83:f10af47696bb, 2016-09-12 (annotated)

Committer:
Kazuki Yamamoto
Date:
Mon Sep 12 01:01:23 2016 +0900
Revision:
83:f10af47696bb
Parent:
80:3cbe7972872b
Child:
84:394b8cc7bef2
fix indent format

Who changed what in which revision?

UserRevisionLine numberNew contents of line
K4zuki 78:434514b8d383 1 /** uart_i2c_conv for LPC824
K4zuki 78:434514b8d383 2 */
K4zuki 78:434514b8d383 3
K4zuki 78:434514b8d383 4 #include "mbed.h"
K4zuki 78:434514b8d383 5 #include "settings.h"
K4zuki 78:434514b8d383 6 //Table 3. ASCII commands supported by SC18IM700
K4zuki 78:434514b8d383 7 //ASCII command Hex value Command function
K4zuki 78:434514b8d383 8 //[X] S 0x53 I2C-bus START
K4zuki 80:3cbe7972872b 9 //[X] P 0x50 I2C/SPI-bus STOP, end of packet
K4zuki 78:434514b8d383 10 //[X] R 0x52 read SC18IM700 internal register
K4zuki 80:3cbe7972872b 11 //[X] W 0x57 write to internal register(s)
K4zuki 80:3cbe7972872b 12 //[X] I 0x49 read GPIO port
K4zuki 80:3cbe7972872b 13 //[X] O 0x4F write to GPIO port
K4zuki 78:434514b8d383 14 //[_] Z 0x5A power down
K4zuki 78:434514b8d383 15 //[X] C 0x43 change channel
K4zuki 80:3cbe7972872b 16 //[X] E 0x45 SPI transfer start
K4zuki 78:434514b8d383 17 //[_] V 0x__ enable VDDIO output to chip
K4zuki 78:434514b8d383 18
K4zuki 78:434514b8d383 19 /**
K4zuki 78:434514b8d383 20 "C| '0'| P"
K4zuki 78:434514b8d383 21 "C| '1'| P"
K4zuki 78:434514b8d383 22 "C| '2'| P"
K4zuki 78:434514b8d383 23 "C| '3'| P"
K4zuki 78:434514b8d383 24 "S| 0x_8 _0| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| P"
K4zuki 78:434514b8d383 25 "S| 0x_8 _0| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| S| 0x_8 _1| 0x_0 _4| P"
K4zuki 78:434514b8d383 26 "S| 0x_8 _1| 0x_0 _4| P"
K4zuki 78:434514b8d383 27 "R| '0'| P"
K4zuki 78:434514b8d383 28 "R| '0'| '1'| ...| P"
K4zuki 78:434514b8d383 29 "W| '0' 0x_a _a| P"
K4zuki 78:434514b8d383 30 "W| '0' 0x_a _a| '1' 0x_b _b| ...| P"
K4zuki 78:434514b8d383 31 "I| '0'| P"
K4zuki 78:434514b8d383 32 "O| '0'| 0x_a _a| P"
K4zuki 78:434514b8d383 33 "E| 0x_0 _4| 0x_0 _0| 0x_D _E _A _D _B _E _A _F| P" //write
K4zuki 78:434514b8d383 34 "E| 0x_0 _4| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| P" //write and read
K4zuki 78:434514b8d383 35 */
K4zuki 78:434514b8d383 36 int main()
K4zuki 78:434514b8d383 37 {
K4zuki 80:3cbe7972872b 38 I2C* dev = &dev1;
K4zuki 78:434514b8d383 39
K4zuki 80:3cbe7972872b 40 #ifdef isUART
K4zuki 80:3cbe7972872b 41 pc.baud(115200);
K4zuki 80:3cbe7972872b 42 #endif
K4zuki 80:3cbe7972872b 43 _spi.frequency(8000000);
K4zuki 78:434514b8d383 44
K4zuki 80:3cbe7972872b 45 bool s = false;
K4zuki 80:3cbe7972872b 46 dev1.frequency(400000);
K4zuki 80:3cbe7972872b 47 #if defined(TARGET_SSCI824) || defined(TARGET_LP824MAX)
K4zuki 80:3cbe7972872b 48 dev1.frequency(800000);//800k; works around 940kHz with 200ohm pullups/ not work at 1M?
K4zuki 80:3cbe7972872b 49 LPC_IOCON->PIO0_11 &= ~(0x03<<8);
K4zuki 80:3cbe7972872b 50 LPC_IOCON->PIO0_11 |= (0x02<<8);
K4zuki 80:3cbe7972872b 51 LPC_IOCON->PIO0_10 &= ~(0x03<<8);
K4zuki 80:3cbe7972872b 52 LPC_IOCON->PIO0_10 |= (0x02<<8);
K4zuki 80:3cbe7972872b 53 #elif defined(TARGET_MCU_LPC11U35_501) || defined(TARGET_LPC11U35_401)
K4zuki 80:3cbe7972872b 54 dev1.frequency(800000);//800k; works around 940kHz with 200ohm pullups/ not work at 1M?
K4zuki 80:3cbe7972872b 55 LPC_IOCON->PIO0_4 &= ~(0x03<<8);
K4zuki 80:3cbe7972872b 56 LPC_IOCON->PIO0_4 |= (0x02<<8);
K4zuki 80:3cbe7972872b 57 LPC_IOCON->PIO0_5 &= ~(0x03<<8);
K4zuki 80:3cbe7972872b 58 LPC_IOCON->PIO0_5 |= (0x02<<8);
K4zuki 80:3cbe7972872b 59 #endif
K4zuki 78:434514b8d383 60
K4zuki 80:3cbe7972872b 61 #ifdef isI2C2
K4zuki 80:3cbe7972872b 62 dev2.frequency(400000);//400k
K4zuki 80:3cbe7972872b 63 #endif
K4zuki 80:3cbe7972872b 64 #ifdef isI2C3
K4zuki 80:3cbe7972872b 65 dev3.frequency(400000);//400k
K4zuki 80:3cbe7972872b 66 #endif
K4zuki 80:3cbe7972872b 67 #ifdef isI2C4
K4zuki 80:3cbe7972872b 68 dev4.frequency(400000);//400k
K4zuki 80:3cbe7972872b 69 #endif
K4zuki 80:3cbe7972872b 70 #ifdef isGPIO1
K4zuki 80:3cbe7972872b 71 DigitalInOut* gpio1[] = {
K4zuki 80:3cbe7972872b 72 &_GPIO10,
K4zuki 80:3cbe7972872b 73 &_GPIO11,
K4zuki 80:3cbe7972872b 74 &_GPIO12,
K4zuki 80:3cbe7972872b 75 &_GPIO13,
K4zuki 80:3cbe7972872b 76 &_GPIO14,
K4zuki 80:3cbe7972872b 77 &_GPIO15,
K4zuki 80:3cbe7972872b 78 &_GPIO16,
K4zuki 80:3cbe7972872b 79 &_GPIO17,
K4zuki 80:3cbe7972872b 80 };
K4zuki 80:3cbe7972872b 81 for(int k = 0; k < 8; k++){
K4zuki 80:3cbe7972872b 82 gpio1[k]->input();
K4zuki 80:3cbe7972872b 83 gpio1[k]->mode( PullUp );
K4zuki 80:3cbe7972872b 84 }
K4zuki 80:3cbe7972872b 85 #endif
K4zuki 78:434514b8d383 86
K4zuki 80:3cbe7972872b 87 DigitalInOut* gpio0[] = {
K4zuki 80:3cbe7972872b 88 &_GPIO00,
K4zuki 80:3cbe7972872b 89 &_GPIO01,
K4zuki 80:3cbe7972872b 90 &_GPIO02,
K4zuki 80:3cbe7972872b 91 &_GPIO03,
K4zuki 80:3cbe7972872b 92 &_GPIO04,
K4zuki 80:3cbe7972872b 93 &_GPIO05,
K4zuki 80:3cbe7972872b 94 &_GPIO06,
K4zuki 80:3cbe7972872b 95 &_GPIO07,
K4zuki 80:3cbe7972872b 96 };
K4zuki 80:3cbe7972872b 97 for(int k = 0; k < 8; k++){
K4zuki 80:3cbe7972872b 98 gpio0[k]->input();
K4zuki 80:3cbe7972872b 99 gpio0[k]->mode( PullUp );
K4zuki 80:3cbe7972872b 100 }
K4zuki 80:3cbe7972872b 101
K4zuki 80:3cbe7972872b 102 int ack = 0;
K4zuki 80:3cbe7972872b 103 int plength = 0;
K4zuki 80:3cbe7972872b 104 int recieve[256];
K4zuki 80:3cbe7972872b 105 char send[256];
K4zuki 80:3cbe7972872b 106 for(int k = 0; k < 256; k+=4){
K4zuki 80:3cbe7972872b 107 // cafe moca
K4zuki 80:3cbe7972872b 108 recieve[k + 0] = send[k + 0] = 0xC4;
K4zuki 80:3cbe7972872b 109 recieve[k + 1] = send[k + 1] = 0xFE;
K4zuki 80:3cbe7972872b 110 recieve[k + 2] = send[k + 2] = 0xE0;
K4zuki 80:3cbe7972872b 111 recieve[k + 3] = send[k + 3] = 0xCA;
K4zuki 80:3cbe7972872b 112 }
K4zuki 78:434514b8d383 113
K4zuki 80:3cbe7972872b 114 int read = 0;
K4zuki 80:3cbe7972872b 115 int address = 0;
K4zuki 80:3cbe7972872b 116 int data = 0;
K4zuki 80:3cbe7972872b 117 int _data = 0;
K4zuki 80:3cbe7972872b 118 int length = 0;
K4zuki 80:3cbe7972872b 119 int channel = 0;
K4zuki 80:3cbe7972872b 120 int format = 8;
K4zuki 80:3cbe7972872b 121 int enabled = 0;
K4zuki 80:3cbe7972872b 122 int disabled = 0;
K4zuki 80:3cbe7972872b 123 enum command_e {
K4zuki 80:3cbe7972872b 124 CMD_S = 'S',
K4zuki 80:3cbe7972872b 125 CMD_P = 'P',
K4zuki 80:3cbe7972872b 126 CMD_C = 'C',
K4zuki 80:3cbe7972872b 127 CMD_R = 'R',
K4zuki 80:3cbe7972872b 128 CMD_W = 'W',
K4zuki 80:3cbe7972872b 129 CMD_I = 'I',
K4zuki 80:3cbe7972872b 130 CMD_O = 'O',
K4zuki 80:3cbe7972872b 131 CMD_E = 'E',
K4zuki 80:3cbe7972872b 132 };
K4zuki 80:3cbe7972872b 133 enum channel_e {
K4zuki 80:3cbe7972872b 134 CH0 = '0',
K4zuki 80:3cbe7972872b 135 CH1 = '1',
K4zuki 80:3cbe7972872b 136 CH2 = '2',
K4zuki 80:3cbe7972872b 137 CH3 = '3',
K4zuki 80:3cbe7972872b 138 };
K4zuki 80:3cbe7972872b 139 enum register_e {
K4zuki 80:3cbe7972872b 140 CHIP_ID = '0',
K4zuki 80:3cbe7972872b 141 GPIO0_STAT = '1',
K4zuki 80:3cbe7972872b 142 GPIO1_STAT = '2',
K4zuki 80:3cbe7972872b 143 GPIO0_CONF = '3',
K4zuki 80:3cbe7972872b 144 GPIO1_CONF = '4',
K4zuki 80:3cbe7972872b 145 I2C_CONF = '5',
K4zuki 80:3cbe7972872b 146 SPI_CONF = '6',
K4zuki 80:3cbe7972872b 147 REG7,
K4zuki 80:3cbe7972872b 148 REG8,
K4zuki 80:3cbe7972872b 149 REG9,
K4zuki 80:3cbe7972872b 150 };
K4zuki 80:3cbe7972872b 151 static uint8_t registers[]={
K4zuki 80:3cbe7972872b 152 chip_id,
K4zuki 80:3cbe7972872b 153 0x00,
K4zuki 80:3cbe7972872b 154 0x00,
K4zuki 80:3cbe7972872b 155 0x00,
K4zuki 80:3cbe7972872b 156 0x00,
K4zuki 80:3cbe7972872b 157 0xFF,
K4zuki 80:3cbe7972872b 158 0x70,
K4zuki 80:3cbe7972872b 159 REG7,
K4zuki 80:3cbe7972872b 160 REG8,
K4zuki 80:3cbe7972872b 161 REG9,
K4zuki 80:3cbe7972872b 162 };
K4zuki 78:434514b8d383 163
K4zuki 80:3cbe7972872b 164 int i = 0;
K4zuki 80:3cbe7972872b 165 while(1) {
K4zuki 80:3cbe7972872b 166 i = 0;
K4zuki 80:3cbe7972872b 167 length = 0;
K4zuki 80:3cbe7972872b 168 while( true ) {
K4zuki 80:3cbe7972872b 169 read = pc.getc();
K4zuki 80:3cbe7972872b 170 recieve[i] = read;
K4zuki 80:3cbe7972872b 171 i++;
K4zuki 80:3cbe7972872b 172 if(read == 'P') {
K4zuki 80:3cbe7972872b 173 plength = i;
K4zuki 80:3cbe7972872b 174 break;
K4zuki 80:3cbe7972872b 175 }
K4zuki 80:3cbe7972872b 176 }
K4zuki 80:3cbe7972872b 177 i = 0;
K4zuki 80:3cbe7972872b 178 while( i < plength ) {
K4zuki 80:3cbe7972872b 179 switch( recieve[ i ] ) {
K4zuki 80:3cbe7972872b 180 case CMD_C:
K4zuki 80:3cbe7972872b 181 {
K4zuki 80:3cbe7972872b 182 s = false;
K4zuki 80:3cbe7972872b 183 channel = recieve[i + 1];
K4zuki 80:3cbe7972872b 184 switch( channel ) {
K4zuki 80:3cbe7972872b 185 case CH0:
K4zuki 80:3cbe7972872b 186 {
K4zuki 80:3cbe7972872b 187 channel = CH0;
K4zuki 80:3cbe7972872b 188 dev = &dev1;
K4zuki 80:3cbe7972872b 189 break;
K4zuki 78:434514b8d383 190 }
K4zuki 80:3cbe7972872b 191 #ifdef isI2C2
K4zuki 80:3cbe7972872b 192 case CH1:
K4zuki 80:3cbe7972872b 193 {
K4zuki 80:3cbe7972872b 194 channel = CH1;
K4zuki 80:3cbe7972872b 195 dev = &dev2;
K4zuki 80:3cbe7972872b 196 break;
K4zuki 80:3cbe7972872b 197 }
K4zuki 80:3cbe7972872b 198 #endif
K4zuki 80:3cbe7972872b 199 #ifdef isI2C3
K4zuki 80:3cbe7972872b 200 case CH2:
K4zuki 80:3cbe7972872b 201 {
K4zuki 80:3cbe7972872b 202 channel = CH2;
K4zuki 80:3cbe7972872b 203 dev = &dev3;
K4zuki 80:3cbe7972872b 204 break;
K4zuki 80:3cbe7972872b 205 }
K4zuki 80:3cbe7972872b 206 #endif
K4zuki 80:3cbe7972872b 207 #ifdef isI2C4
K4zuki 80:3cbe7972872b 208 case CH3:
K4zuki 80:3cbe7972872b 209 {
K4zuki 80:3cbe7972872b 210 channel = CH3;
K4zuki 80:3cbe7972872b 211 dev = &dev4;
K4zuki 80:3cbe7972872b 212 break;
K4zuki 80:3cbe7972872b 213 }
K4zuki 80:3cbe7972872b 214 #endif
K4zuki 80:3cbe7972872b 215 default:
K4zuki 80:3cbe7972872b 216 {
K4zuki 80:3cbe7972872b 217 channel = CH0;
K4zuki 80:3cbe7972872b 218 dev = &dev1;
K4zuki 80:3cbe7972872b 219 break;
K4zuki 80:3cbe7972872b 220 }
K4zuki 80:3cbe7972872b 221 }
K4zuki 80:3cbe7972872b 222 i += 2;
K4zuki 80:3cbe7972872b 223 break;
K4zuki 78:434514b8d383 224 }
K4zuki 80:3cbe7972872b 225 case CMD_S:
K4zuki 80:3cbe7972872b 226 {
K4zuki 80:3cbe7972872b 227 s = true;
K4zuki 80:3cbe7972872b 228 ack = plength - 2 - (i+1) + (recieve[i+2] & 0x01);
K4zuki 80:3cbe7972872b 229 if( ack >= 4 ) { //valid packet
K4zuki 80:3cbe7972872b 230 address = 0xff & (recieve[i+1] << 4 | (recieve[i+2] & 0x0F));
K4zuki 80:3cbe7972872b 231 length = 0xff & (recieve[i+3] << 4 | (recieve[i+4] & 0x0F));
K4zuki 78:434514b8d383 232
K4zuki 80:3cbe7972872b 233 if( address & 0x01 ) { //read
K4zuki 80:3cbe7972872b 234 ack = dev->read(address, send, length, false); //added
K4zuki 80:3cbe7972872b 235 send[length] = ack;
K4zuki 80:3cbe7972872b 236 length += 1;
K4zuki 80:3cbe7972872b 237 i += 5;
K4zuki 80:3cbe7972872b 238 } else { // write
K4zuki 80:3cbe7972872b 239 for(int j = 0; j < (length * 2); j += 2) {
K4zuki 80:3cbe7972872b 240 ack = 0xff&((recieve[5+j] << 4) | (recieve[6+j] & 0x0F));
K4zuki 80:3cbe7972872b 241 *(send+(j/2)) = ack; //added
K4zuki 80:3cbe7972872b 242 }
K4zuki 80:3cbe7972872b 243 ack = dev->write(address, send, length, true); //added
K4zuki 80:3cbe7972872b 244 i += (5 + length * 2);
K4zuki 80:3cbe7972872b 245 send[0] = ack;
K4zuki 80:3cbe7972872b 246 length = 1;
K4zuki 80:3cbe7972872b 247 }
K4zuki 80:3cbe7972872b 248 } else {
K4zuki 80:3cbe7972872b 249 pc.printf("bad packet! %d, %d, %02X, %d\n\r",
K4zuki 80:3cbe7972872b 250 plength, i, recieve[(i + 2)] & 0x0F, ack);
K4zuki 80:3cbe7972872b 251 s = false;
K4zuki 80:3cbe7972872b 252 i = plength;
K4zuki 80:3cbe7972872b 253 }
K4zuki 80:3cbe7972872b 254 break;
K4zuki 80:3cbe7972872b 255 }
K4zuki 80:3cbe7972872b 256 case CMD_P:
K4zuki 80:3cbe7972872b 257 {
K4zuki 80:3cbe7972872b 258 if(s){
K4zuki 80:3cbe7972872b 259 dev->stop();
K4zuki 80:3cbe7972872b 260 s = false;
K4zuki 80:3cbe7972872b 261 if( send[length - 1] == 0 ){
K4zuki 80:3cbe7972872b 262 pc.printf("ACK,");
K4zuki 80:3cbe7972872b 263 }else{
K4zuki 80:3cbe7972872b 264 pc.printf("NAK,");
K4zuki 80:3cbe7972872b 265 }
K4zuki 80:3cbe7972872b 266 length--;
K4zuki 80:3cbe7972872b 267 }
K4zuki 80:3cbe7972872b 268 i = plength;
K4zuki 80:3cbe7972872b 269 for(int j = 0; j < length; j++) {
K4zuki 80:3cbe7972872b 270 pc.printf("%02X,", send[j]);
K4zuki 80:3cbe7972872b 271 }
K4zuki 80:3cbe7972872b 272 pc.printf("ok\n\r");
K4zuki 80:3cbe7972872b 273 break;
K4zuki 80:3cbe7972872b 274 }
K4zuki 80:3cbe7972872b 275 case CMD_R:
K4zuki 80:3cbe7972872b 276 {
K4zuki 80:3cbe7972872b 277 s = false;
K4zuki 80:3cbe7972872b 278 length = plength - 2;
K4zuki 80:3cbe7972872b 279 if(length < 1){
K4zuki 80:3cbe7972872b 280 pc.printf("bad packet! %d\n\r",length);
K4zuki 80:3cbe7972872b 281 i = plength + 1;
K4zuki 80:3cbe7972872b 282 length = 0;
K4zuki 80:3cbe7972872b 283 }else{
K4zuki 80:3cbe7972872b 284 for(int j = 0; j < length; j++){
K4zuki 80:3cbe7972872b 285 address = recieve[i+1+j];
K4zuki 80:3cbe7972872b 286 switch(address){
K4zuki 80:3cbe7972872b 287 case CHIP_ID:
K4zuki 78:434514b8d383 288 {
K4zuki 80:3cbe7972872b 289 data = chip_id;
K4zuki 80:3cbe7972872b 290 break;
K4zuki 78:434514b8d383 291 }
K4zuki 80:3cbe7972872b 292 case GPIO0_STAT:
K4zuki 80:3cbe7972872b 293 {
K4zuki 80:3cbe7972872b 294 for(int k = 0; k < 8; k++){
K4zuki 80:3cbe7972872b 295 _data = gpio0[k]->read();
K4zuki 80:3cbe7972872b 296 data |= (_data << k);
K4zuki 80:3cbe7972872b 297 }
K4zuki 80:3cbe7972872b 298 registers[GPIO0_STAT-'0'] = data;
K4zuki 80:3cbe7972872b 299 break;
K4zuki 80:3cbe7972872b 300 }
K4zuki 80:3cbe7972872b 301 case GPIO0_CONF:
K4zuki 80:3cbe7972872b 302 {
K4zuki 80:3cbe7972872b 303 data = registers[GPIO0_CONF-'0'];
K4zuki 80:3cbe7972872b 304 break;
K4zuki 80:3cbe7972872b 305 }
K4zuki 80:3cbe7972872b 306 #ifdef isGPIO1
K4zuki 80:3cbe7972872b 307 case GPIO1_STAT:
K4zuki 78:434514b8d383 308 {
K4zuki 80:3cbe7972872b 309 for(int k = 0; k < 8; k++){
K4zuki 80:3cbe7972872b 310 _data = gpio1[k]->read();
K4zuki 80:3cbe7972872b 311 data |= (_data << k);
K4zuki 80:3cbe7972872b 312 }
K4zuki 80:3cbe7972872b 313 registers[GPIO1_STAT-'0'] = data;
K4zuki 80:3cbe7972872b 314 break;
K4zuki 78:434514b8d383 315 }
K4zuki 80:3cbe7972872b 316 case GPIO1_CONF:
K4zuki 78:434514b8d383 317 {
K4zuki 80:3cbe7972872b 318 data = registers[GPIO1_CONF-'0'];
K4zuki 80:3cbe7972872b 319 break;
K4zuki 78:434514b8d383 320 }
K4zuki 80:3cbe7972872b 321 #endif
K4zuki 80:3cbe7972872b 322 case I2C_CONF:
K4zuki 78:434514b8d383 323 {
K4zuki 80:3cbe7972872b 324 data = registers[I2C_CONF-'0'];
K4zuki 80:3cbe7972872b 325 break;
K4zuki 78:434514b8d383 326 }
K4zuki 80:3cbe7972872b 327 case SPI_CONF:
K4zuki 78:434514b8d383 328 {
K4zuki 80:3cbe7972872b 329 data = registers[SPI_CONF-'0'];
K4zuki 80:3cbe7972872b 330 break;
K4zuki 78:434514b8d383 331 }
K4zuki 78:434514b8d383 332 default:
K4zuki 78:434514b8d383 333 {
K4zuki 80:3cbe7972872b 334 data = 0xAA;
K4zuki 80:3cbe7972872b 335 break;
K4zuki 80:3cbe7972872b 336 }
K4zuki 80:3cbe7972872b 337 }
K4zuki 80:3cbe7972872b 338 send[j] = (char)data;
K4zuki 80:3cbe7972872b 339 data = 0;
K4zuki 80:3cbe7972872b 340 }
K4zuki 80:3cbe7972872b 341 i += (length+1);
K4zuki 80:3cbe7972872b 342 }
K4zuki 80:3cbe7972872b 343 break;
K4zuki 80:3cbe7972872b 344 }
K4zuki 80:3cbe7972872b 345 case CMD_W:
K4zuki 80:3cbe7972872b 346 {
K4zuki 80:3cbe7972872b 347 s = false;
K4zuki 80:3cbe7972872b 348 length = plength - 2;
K4zuki 80:3cbe7972872b 349 if(length < 3){
K4zuki 80:3cbe7972872b 350 pc.printf("bad packet! %d\n\r",length);
K4zuki 80:3cbe7972872b 351 i = plength + 1;
K4zuki 80:3cbe7972872b 352 length = 0;
K4zuki 80:3cbe7972872b 353 }else{
K4zuki 80:3cbe7972872b 354 for(int j = 0; j < length; j +=3){
K4zuki 80:3cbe7972872b 355 address = recieve[i+1+j];
K4zuki 80:3cbe7972872b 356 data = 0xff & (recieve[i+2+j] << 4 | (recieve[i+3+j] & 0x0F));
K4zuki 80:3cbe7972872b 357 _data = 0;
K4zuki 80:3cbe7972872b 358 switch(address){
K4zuki 80:3cbe7972872b 359 case CHIP_ID:
K4zuki 80:3cbe7972872b 360 {
K4zuki 80:3cbe7972872b 361 //READ ONLY: do nothing
K4zuki 80:3cbe7972872b 362 data = registers[CHIP_ID-'0'];
K4zuki 80:3cbe7972872b 363 break;
K4zuki 80:3cbe7972872b 364 }
K4zuki 80:3cbe7972872b 365 case GPIO0_STAT:
K4zuki 80:3cbe7972872b 366 {
K4zuki 80:3cbe7972872b 367 _data = registers[GPIO0_CONF-'0'];
K4zuki 80:3cbe7972872b 368 for(int k=0; k<8; k++){
K4zuki 80:3cbe7972872b 369 if(_data&0x01){ // output
K4zuki 80:3cbe7972872b 370 gpio0[k]->write((data>>k)&0x01);
K4zuki 80:3cbe7972872b 371 }else{ // input
K4zuki 80:3cbe7972872b 372 ; // do nothing
K4zuki 80:3cbe7972872b 373 }
K4zuki 80:3cbe7972872b 374 _data >>= 1;
K4zuki 80:3cbe7972872b 375 }
K4zuki 80:3cbe7972872b 376 break;
K4zuki 80:3cbe7972872b 377 }
K4zuki 80:3cbe7972872b 378 case GPIO0_CONF:
K4zuki 80:3cbe7972872b 379 {
K4zuki 80:3cbe7972872b 380 registers[GPIO0_CONF-'0'] = data;
K4zuki 80:3cbe7972872b 381 for(int k = 0; k < 8; k++){
K4zuki 80:3cbe7972872b 382 if(data & 0x01){//output
K4zuki 80:3cbe7972872b 383 gpio0[k]->output();
K4zuki 80:3cbe7972872b 384 }else{//input
K4zuki 80:3cbe7972872b 385 gpio0[k]->input();
K4zuki 80:3cbe7972872b 386 gpio0[k]->mode(PullUp);
K4zuki 80:3cbe7972872b 387 }
K4zuki 80:3cbe7972872b 388 data >>= 1;
K4zuki 80:3cbe7972872b 389 }
K4zuki 80:3cbe7972872b 390 data = registers[GPIO0_CONF-'0'];
K4zuki 80:3cbe7972872b 391 break;
K4zuki 78:434514b8d383 392 }
K4zuki 80:3cbe7972872b 393 #ifdef isGPIO1
K4zuki 80:3cbe7972872b 394 case GPIO1_STAT:
K4zuki 80:3cbe7972872b 395 {
K4zuki 80:3cbe7972872b 396 _data = registers[GPIO1_CONF-'0'];
K4zuki 80:3cbe7972872b 397 for(int k = 0; k < 8; k++){
K4zuki 80:3cbe7972872b 398 if(_data & 0x01){ // output
K4zuki 80:3cbe7972872b 399 gpio1[k]->write((data>>k)&0x01);
K4zuki 80:3cbe7972872b 400 }else{ // input
K4zuki 80:3cbe7972872b 401 ; // do nothing
K4zuki 80:3cbe7972872b 402 }
K4zuki 80:3cbe7972872b 403 _data >>= 1;
K4zuki 80:3cbe7972872b 404 }
K4zuki 80:3cbe7972872b 405 break;
K4zuki 80:3cbe7972872b 406 }
K4zuki 80:3cbe7972872b 407 case GPIO1_CONF:
K4zuki 80:3cbe7972872b 408 {
K4zuki 80:3cbe7972872b 409 registers[GPIO1_CONF-'0'] = data;
K4zuki 80:3cbe7972872b 410 for(int k = 0; k < 6; k++){
K4zuki 80:3cbe7972872b 411 if(data & 0x01){//output
K4zuki 80:3cbe7972872b 412 gpio1[k]->output();
K4zuki 80:3cbe7972872b 413 }else{//input
K4zuki 80:3cbe7972872b 414 gpio1[k]->input();
K4zuki 80:3cbe7972872b 415 gpio1[k]->mode(PullUp);
K4zuki 80:3cbe7972872b 416 }
K4zuki 80:3cbe7972872b 417 data >>= 1;
K4zuki 80:3cbe7972872b 418 }
K4zuki 80:3cbe7972872b 419 data = registers[GPIO1_CONF-'0'];
K4zuki 80:3cbe7972872b 420 break;
K4zuki 80:3cbe7972872b 421 }
K4zuki 80:3cbe7972872b 422 #endif
K4zuki 80:3cbe7972872b 423 case I2C_CONF:
K4zuki 80:3cbe7972872b 424 {
K4zuki 80:3cbe7972872b 425 registers[I2C_CONF-'0'] = data;
K4zuki 80:3cbe7972872b 426 #if defined(TARGET_LPC1768)
K4zuki 80:3cbe7972872b 427 dev1.frequency(100000 * ((0x03 & (data >> 6)) + 1));
K4zuki 80:3cbe7972872b 428 #else
K4zuki 80:3cbe7972872b 429 dev1.frequency(200000 * ((0x03 & (data >> 6)) + 1));
K4zuki 80:3cbe7972872b 430 #endif
K4zuki 80:3cbe7972872b 431 #ifdef isI2C2
K4zuki 80:3cbe7972872b 432 dev2.frequency(100000 * ((0x03 & (data >> 4)) + 1));
K4zuki 80:3cbe7972872b 433 #endif
K4zuki 80:3cbe7972872b 434 #ifdef isI2C3
K4zuki 80:3cbe7972872b 435 dev3.frequency(100000 * ((0x03 & (data >> 2)) + 1));
K4zuki 80:3cbe7972872b 436 #endif
K4zuki 80:3cbe7972872b 437 #ifdef isI2C4
K4zuki 80:3cbe7972872b 438 dev4.frequency(100000 * ((0x03 & (data >> 0)) + 1));
K4zuki 80:3cbe7972872b 439 #endif
K4zuki 80:3cbe7972872b 440 break;
K4zuki 80:3cbe7972872b 441 }
K4zuki 80:3cbe7972872b 442 case SPI_CONF:
K4zuki 80:3cbe7972872b 443 {
K4zuki 80:3cbe7972872b 444 registers[SPI_CONF-'0'] = data;
K4zuki 80:3cbe7972872b 445 format = ((data & 0x04) + 4) << 1;
K4zuki 80:3cbe7972872b 446 _spi.format(format, 0x03 & (data));
K4zuki 80:3cbe7972872b 447 _spi.frequency(1000000 * ((0x07 & (data >> 4)) + 1));
K4zuki 80:3cbe7972872b 448 enabled = (data & 0x08) >> 3;
K4zuki 80:3cbe7972872b 449 /*
K4zuki 80:3cbe7972872b 450 7 not used
K4zuki 80:3cbe7972872b 451 6:4 frequency
K4zuki 80:3cbe7972872b 452 3 CE pol
K4zuki 80:3cbe7972872b 453 2 word size(0=8bit,1=16bit)
K4zuki 80:3cbe7972872b 454 1:0 pol(corresponds to spi.format())
K4zuki 80:3cbe7972872b 455 */
K4zuki 80:3cbe7972872b 456 disabled = ~enabled;
K4zuki 80:3cbe7972872b 457 break;
K4zuki 80:3cbe7972872b 458 }
K4zuki 80:3cbe7972872b 459 default:
K4zuki 80:3cbe7972872b 460 {
K4zuki 80:3cbe7972872b 461 break;
K4zuki 80:3cbe7972872b 462 }
K4zuki 80:3cbe7972872b 463 }
K4zuki 80:3cbe7972872b 464 send[j/3] = data;
K4zuki 78:434514b8d383 465 }
K4zuki 80:3cbe7972872b 466 i += (length + 1);
K4zuki 80:3cbe7972872b 467 length /= 3;
K4zuki 80:3cbe7972872b 468 }
K4zuki 80:3cbe7972872b 469 break;
K4zuki 78:434514b8d383 470 }
K4zuki 80:3cbe7972872b 471 case CMD_I:
K4zuki 80:3cbe7972872b 472 {
K4zuki 80:3cbe7972872b 473 s = false;
K4zuki 80:3cbe7972872b 474 length = plength - 2;
K4zuki 80:3cbe7972872b 475 if(length < 1){
K4zuki 80:3cbe7972872b 476 pc.printf("bad packet! %d\n\r",length);
K4zuki 80:3cbe7972872b 477 i = plength + 1;
K4zuki 80:3cbe7972872b 478 length = 0;
K4zuki 80:3cbe7972872b 479 }else{
K4zuki 80:3cbe7972872b 480 for(int j=0; j<length; j++){
K4zuki 80:3cbe7972872b 481 address = recieve[i+1+j];
K4zuki 80:3cbe7972872b 482 _data=0;
K4zuki 80:3cbe7972872b 483 switch(address){
K4zuki 80:3cbe7972872b 484 case GPIO0_STAT:
K4zuki 80:3cbe7972872b 485 {
K4zuki 80:3cbe7972872b 486 for(int k=0; k<8; k++){
K4zuki 80:3cbe7972872b 487 _data = gpio0[k]->read();
K4zuki 80:3cbe7972872b 488 data |= (_data << k);
K4zuki 80:3cbe7972872b 489 }
K4zuki 80:3cbe7972872b 490 registers[GPIO0_STAT-'0'] = data;
K4zuki 80:3cbe7972872b 491 break;
K4zuki 80:3cbe7972872b 492 }
K4zuki 80:3cbe7972872b 493 #ifdef isGPIO1
K4zuki 80:3cbe7972872b 494 case GPIO1_STAT:
K4zuki 80:3cbe7972872b 495 {
K4zuki 80:3cbe7972872b 496 for(int k=0; k<8; k++){
K4zuki 80:3cbe7972872b 497 _data = gpio1[k]->read();
K4zuki 80:3cbe7972872b 498 data |= (_data << k);
K4zuki 80:3cbe7972872b 499 }
K4zuki 80:3cbe7972872b 500 registers[GPIO1_STAT-'0'] = data;
K4zuki 80:3cbe7972872b 501 break;
K4zuki 80:3cbe7972872b 502 }
K4zuki 80:3cbe7972872b 503 #endif
K4zuki 80:3cbe7972872b 504 default:
K4zuki 80:3cbe7972872b 505 {
K4zuki 80:3cbe7972872b 506 data = 0xAA;
K4zuki 80:3cbe7972872b 507 break;
K4zuki 80:3cbe7972872b 508 }
K4zuki 80:3cbe7972872b 509 }
K4zuki 80:3cbe7972872b 510 send[j] = (char)data;
K4zuki 80:3cbe7972872b 511 data = 0;
K4zuki 80:3cbe7972872b 512 }
K4zuki 80:3cbe7972872b 513 i += (length+1);
K4zuki 80:3cbe7972872b 514 }
K4zuki 80:3cbe7972872b 515 break;
K4zuki 80:3cbe7972872b 516 }
K4zuki 80:3cbe7972872b 517 case CMD_O:
K4zuki 80:3cbe7972872b 518 {
K4zuki 80:3cbe7972872b 519 s = false;
K4zuki 80:3cbe7972872b 520 length = plength - 2;
K4zuki 80:3cbe7972872b 521 if(length < 3){
K4zuki 80:3cbe7972872b 522 pc.printf("bad packet! %d\n\r",length);
K4zuki 80:3cbe7972872b 523 i = plength + 1;
K4zuki 80:3cbe7972872b 524 length = 0;
K4zuki 80:3cbe7972872b 525 }else{
K4zuki 80:3cbe7972872b 526 for(int j=0; j<length; j+=3){
K4zuki 80:3cbe7972872b 527 address = recieve[i+1+j];
K4zuki 80:3cbe7972872b 528 data = 0xff & (recieve[i+2+j] << 4 | (recieve[i+3+j] & 0x0F));
K4zuki 80:3cbe7972872b 529 switch(address){
K4zuki 80:3cbe7972872b 530 case GPIO0_STAT:
K4zuki 80:3cbe7972872b 531 {
K4zuki 80:3cbe7972872b 532 _data = registers[GPIO0_CONF-'0'];
K4zuki 80:3cbe7972872b 533 for(int k=0; k<8; k++){
K4zuki 80:3cbe7972872b 534 if(_data&0x01){ // output
K4zuki 80:3cbe7972872b 535 gpio0[k]->write(data&0x01);
K4zuki 80:3cbe7972872b 536 }else{ // input
K4zuki 80:3cbe7972872b 537 ; // do nothing
K4zuki 80:3cbe7972872b 538 }
K4zuki 80:3cbe7972872b 539 data >>= 1;
K4zuki 80:3cbe7972872b 540 _data >>= 1;
K4zuki 80:3cbe7972872b 541 }
K4zuki 80:3cbe7972872b 542 break;
K4zuki 80:3cbe7972872b 543 }
K4zuki 80:3cbe7972872b 544 #ifdef isGPIO1
K4zuki 80:3cbe7972872b 545 case GPIO1_STAT:
K4zuki 80:3cbe7972872b 546 {
K4zuki 80:3cbe7972872b 547 _data = registers[GPIO1_CONF-'0'];
K4zuki 80:3cbe7972872b 548 for(int k=0; k<8; k++){
K4zuki 80:3cbe7972872b 549 if(_data&0x01){ // output
K4zuki 80:3cbe7972872b 550 gpio1[k]->write(data&0x01);
K4zuki 80:3cbe7972872b 551 }else{ // input
K4zuki 80:3cbe7972872b 552 ; // do nothing
K4zuki 80:3cbe7972872b 553 }
K4zuki 80:3cbe7972872b 554 data >>= 1;
K4zuki 80:3cbe7972872b 555 _data >>= 1;
K4zuki 80:3cbe7972872b 556 }
K4zuki 80:3cbe7972872b 557 break;
K4zuki 80:3cbe7972872b 558 }
K4zuki 80:3cbe7972872b 559 #endif
K4zuki 80:3cbe7972872b 560 default:
K4zuki 80:3cbe7972872b 561 {
K4zuki 80:3cbe7972872b 562 break;
K4zuki 80:3cbe7972872b 563 }
K4zuki 80:3cbe7972872b 564 }
K4zuki 80:3cbe7972872b 565 send[j/3] = data;
K4zuki 80:3cbe7972872b 566 }
K4zuki 80:3cbe7972872b 567 }
K4zuki 80:3cbe7972872b 568 i += (length+1);
K4zuki 80:3cbe7972872b 569 length /= 3;
K4zuki 80:3cbe7972872b 570 // pc.printf("command O is not implemented, ");
K4zuki 80:3cbe7972872b 571 break;
K4zuki 80:3cbe7972872b 572 }
K4zuki 80:3cbe7972872b 573 case CMD_E:
K4zuki 80:3cbe7972872b 574 {
K4zuki 80:3cbe7972872b 575 s = false;
K4zuki 80:3cbe7972872b 576 /*
K4zuki 80:3cbe7972872b 577 "0| 1 2| 3 4| 5 6 7 8 9 10 11 12|13" //plength=14
K4zuki 80:3cbe7972872b 578 "E| 0x_0 _1| 0x_0 _0| 0x_D _E| P" //minimum plength=8
K4zuki 80:3cbe7972872b 579 "E| 0x_0 _1| 0x_0 _0| 0x_D _E|_A _D| P" //minimum plength=10(16bit)
K4zuki 80:3cbe7972872b 580 "E| 0x_0 _4| 0x_0 _0| 0x_D _E _A _D _B _E _A _F| P" //write
K4zuki 80:3cbe7972872b 581 "E| 0x_0 _4| 0x_0 _4| 0x_D _E _A _D _B _E _A _F| P" //write and read
K4zuki 80:3cbe7972872b 582 */
K4zuki 80:3cbe7972872b 583 length = plength - 2; //6
K4zuki 80:3cbe7972872b 584 if(length < 6){
K4zuki 80:3cbe7972872b 585 pc.printf("bad packet! %d\n\r",length);
K4zuki 80:3cbe7972872b 586 i = plength + 1;
K4zuki 80:3cbe7972872b 587 length = 0;
K4zuki 80:3cbe7972872b 588 }else{
K4zuki 80:3cbe7972872b 589 length = length-4; //actual data in packet
K4zuki 80:3cbe7972872b 590 data = 0xff & ((recieve[i+1]<<4) | (recieve[i+2]&0x0F)); // write length
K4zuki 80:3cbe7972872b 591 read = 0xff & ((recieve[i+3]<<4) | (recieve[i+4]&0x0F)); // read length
K4zuki 80:3cbe7972872b 592 switch(format){
K4zuki 80:3cbe7972872b 593 case 8:
K4zuki 80:3cbe7972872b 594 {
K4zuki 80:3cbe7972872b 595 _cs.write(enabled);
K4zuki 80:3cbe7972872b 596 for(int j = 0; j < length; j += 2){
K4zuki 80:3cbe7972872b 597 _data = 0xff & ((recieve[i+5+j+0]<<4) | (recieve[i+5+j+1]&0x0F));
K4zuki 80:3cbe7972872b 598 ack = _spi.write(_data);
K4zuki 80:3cbe7972872b 599 // pc.printf("s%02X,",_data);
K4zuki 80:3cbe7972872b 600 send[j/2] = ack;
K4zuki 80:3cbe7972872b 601 }
K4zuki 80:3cbe7972872b 602 for(int j = length; j < (length+2*read); j+=2){
K4zuki 80:3cbe7972872b 603 ack = _spi.write(0xAA); //dummy data to write
K4zuki 80:3cbe7972872b 604 // pc.printf("a%02X,",ack);
K4zuki 80:3cbe7972872b 605 send[j/2] = ack;
K4zuki 80:3cbe7972872b 606 }
K4zuki 80:3cbe7972872b 607 _cs.write(disabled);
K4zuki 80:3cbe7972872b 608 break;
K4zuki 80:3cbe7972872b 609 }
K4zuki 80:3cbe7972872b 610 case 16:
K4zuki 80:3cbe7972872b 611 {
K4zuki 80:3cbe7972872b 612 if((data%2) || (read%2)){ //invalid
K4zuki 80:3cbe7972872b 613 pc.printf("bad packet! %d, %d\n\r",data,read);
K4zuki 80:3cbe7972872b 614 i = plength + 1;
K4zuki 80:3cbe7972872b 615 length = 0;
K4zuki 80:3cbe7972872b 616 }else{
K4zuki 80:3cbe7972872b 617 _cs.write(enabled);
K4zuki 80:3cbe7972872b 618 for(int j = 0; j < length; j += 4){
K4zuki 80:3cbe7972872b 619 _data = 0xffff & (((recieve[i+5+j+0] & 0x0F)<<12)|
K4zuki 80:3cbe7972872b 620 ((recieve[i+5+j+1] & 0x0F)<<8 )|
K4zuki 80:3cbe7972872b 621 ((recieve[i+5+j+2] & 0x0F)<<4 )|
K4zuki 80:3cbe7972872b 622 ((recieve[i+5+j+3] & 0x0F)<<0 )
K4zuki 80:3cbe7972872b 623 );
K4zuki 80:3cbe7972872b 624 ack = _spi.write(_data);
K4zuki 80:3cbe7972872b 625 // pc.printf("s%04X,",_data);
K4zuki 80:3cbe7972872b 626 send[(j/2)+0] = 0xFF & (ack>>8);
K4zuki 80:3cbe7972872b 627 send[(j/2)+1] = 0xFF & (ack>>0);
Kazuki Yamamoto 83:f10af47696bb 628 }
Kazuki Yamamoto 83:f10af47696bb 629 for(int j = length; j < (length+2*read); j += 4){
Kazuki Yamamoto 83:f10af47696bb 630 ack = _spi.write(0xAAAA); //dummy data to write
Kazuki Yamamoto 83:f10af47696bb 631 // pc.printf("a%04X,",ack);
Kazuki Yamamoto 83:f10af47696bb 632 send[(j/2)+0] = 0xFF & (ack>>8);
Kazuki Yamamoto 83:f10af47696bb 633 send[(j/2)+1] = 0xFF & (ack>>0);
Kazuki Yamamoto 83:f10af47696bb 634 }
Kazuki Yamamoto 83:f10af47696bb 635 _cs.write(disabled);
K4zuki 80:3cbe7972872b 636 }
Kazuki Yamamoto 83:f10af47696bb 637 break;
K4zuki 80:3cbe7972872b 638 }
K4zuki 80:3cbe7972872b 639 default:
K4zuki 80:3cbe7972872b 640 {
K4zuki 80:3cbe7972872b 641 pc.printf("this shold not happen %d\n\r",format);
K4zuki 80:3cbe7972872b 642 break;
K4zuki 80:3cbe7972872b 643 }
K4zuki 80:3cbe7972872b 644 }
Kazuki Yamamoto 83:f10af47696bb 645 // pc.printf("command E is for SPI transmission\n\r");
Kazuki Yamamoto 83:f10af47696bb 646 length = read + data;
Kazuki Yamamoto 83:f10af47696bb 647 i = (plength-1);
Kazuki Yamamoto 83:f10af47696bb 648 }
Kazuki Yamamoto 83:f10af47696bb 649 break;
Kazuki Yamamoto 83:f10af47696bb 650 }
Kazuki Yamamoto 83:f10af47696bb 651 case 'Z':
Kazuki Yamamoto 83:f10af47696bb 652 {
Kazuki Yamamoto 83:f10af47696bb 653 s = false;
Kazuki Yamamoto 83:f10af47696bb 654 pc.printf("command Z is not implemented\n\r");
Kazuki Yamamoto 83:f10af47696bb 655 i=plength;
Kazuki Yamamoto 83:f10af47696bb 656 break;
K4zuki 80:3cbe7972872b 657 }
Kazuki Yamamoto 83:f10af47696bb 658 case 'V':
Kazuki Yamamoto 83:f10af47696bb 659 {
Kazuki Yamamoto 83:f10af47696bb 660 s = false;
Kazuki Yamamoto 83:f10af47696bb 661 pc.printf("command V is not implemented\n\r");
Kazuki Yamamoto 83:f10af47696bb 662 i=plength;
Kazuki Yamamoto 83:f10af47696bb 663 break;
Kazuki Yamamoto 83:f10af47696bb 664 }
Kazuki Yamamoto 83:f10af47696bb 665 default:
Kazuki Yamamoto 83:f10af47696bb 666 {
Kazuki Yamamoto 83:f10af47696bb 667 s = false;
Kazuki Yamamoto 83:f10af47696bb 668 pc.printf("command %c is not implemented\n\r", recieve[i]);
Kazuki Yamamoto 83:f10af47696bb 669 i = plength;
Kazuki Yamamoto 83:f10af47696bb 670 break;
Kazuki Yamamoto 83:f10af47696bb 671 }
K4zuki 80:3cbe7972872b 672 }
K4zuki 78:434514b8d383 673 }
Kazuki Yamamoto 83:f10af47696bb 674 i = 0;
Kazuki Yamamoto 83:f10af47696bb 675 length = 0;
K4zuki 80:3cbe7972872b 676 }
K4zuki 78:434514b8d383 677 }