SimpleLib_03272011
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timers.h
00001 /* 00002 * Copyright or � or Copr. 2010, Thomas SOETE 00003 * 00004 * Author e-mail: thomas@soete.org 00005 * Library website : http://mbed.org/users/Alkorin/libraries/SimpleLib/ 00006 * 00007 * This software is governed by the CeCILL license under French law and 00008 * abiding by the rules of distribution of free software. You can use, 00009 * modify and/ or redistribute the software under the terms of the CeCILL 00010 * license as circulated by CEA, CNRS and INRIA at the following URL 00011 * "http://www.cecill.info". 00012 * 00013 * As a counterpart to the access to the source code and rights to copy, 00014 * modify and redistribute granted by the license, users are provided only 00015 * with a limited warranty and the software's author, the holder of the 00016 * economic rights, and the successive licensors have only limited 00017 * liability. 00018 * 00019 * In this respect, the user's attention is drawn to the risks associated 00020 * with loading, using, modifying and/or developing or reproducing the 00021 * software by the user in light of its specific status of free software, 00022 * that may mean that it is complicated to manipulate, and that also 00023 * therefore means that it is reserved for developers and experienced 00024 * professionals having in-depth computer knowledge. Users are therefore 00025 * encouraged to load and test the software's suitability as regards their 00026 * requirements in conditions enabling the security of their systems and/or 00027 * data to be ensured and, more generally, to use and operate it in the 00028 * same conditions as regards security. 00029 * 00030 * The fact that you are presently reading this means that you have had 00031 * knowledge of the CeCILL license and that you accept its terms. 00032 */ 00033 00034 #ifndef __SIMPLELIB_TIMERS_H__ 00035 #define __SIMPLELIB_TIMERS_H__ 00036 00037 #include "mbed_globals.h" 00038 #include "interrupts.h" 00039 00040 /********************************** 00041 * Simple Timers Managment * 00042 ********************************** 00043 * The interrupt handler is : * 00044 * TIMERn_INTERRUPT_HANDLER(void) * 00045 **********************************/ 00046 00047 /** Registers **/ 00048 #define TIMER0_BASE (LPC_TIM0) 00049 #define TIMER1_BASE (LPC_TIM1) 00050 #define TIMER2_BASE (LPC_TIM2) 00051 #define TIMER3_BASE (LPC_TIM3) 00052 #define TIMER_BASE(timer) TOKENPASTE2(timer,_BASE) 00053 00054 // Peripheral Clock Selection registers (See 4.7.3 p56) 00055 #define TIMER0_PCLK_REG (LPC_SC->PCLKSEL0) 00056 #define TIMER1_PCLK_REG (LPC_SC->PCLKSEL0) 00057 #define TIMER2_PCLK_REG (LPC_SC->PCLKSEL1) 00058 #define TIMER3_PCLK_REG (LPC_SC->PCLKSEL1) 00059 #define TIMER_PCLK_REG(timer) TOKENPASTE2(timer,_PCLK_REG) 00060 00061 #define TIMER0_PCLK_OFFSET 2 00062 #define TIMER1_PCLK_OFFSET 4 00063 #define TIMER2_PCLK_OFFSET 12 00064 #define TIMER3_PCLK_OFFSET 14 00065 #define TIMER_PCLK_OFFSET(timer) TOKENPASTE2(timer,_PCLK_OFFSET) 00066 00067 /** Interrupt handlers **/ 00068 #define TIMER0_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER0) 00069 #define TIMER1_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER1) 00070 #define TIMER2_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER2) 00071 #define TIMER3_INTERRUPT_HANDLER TIMER_INTERRUPT_HANDLER(TIMER3) 00072 #define TIMER_INTERRUPT_HANDLER(timer) EXTERN_C void __IRQ TOKENPASTE2(timer,_IRQHandler) 00073 00074 /** Bits **/ 00075 // Power Control for Peripherals (PCONP, 4.8.7.1 p63) 00076 #define TIMER0_PCONP_BIT 1 00077 #define TIMER1_PCONP_BIT 2 00078 #define TIMER2_PCONP_BIT 22 00079 #define TIMER3_PCONP_BIT 23 00080 00081 // Match Control Register (TnMCR, 21.6.8 p496) 00082 #define MATCH_INTERRUPT 1 00083 #define MATCH_RESET 2 00084 #define MATCH_STOP 4 00085 #define MR0_OFFSET 0 00086 #define MR1_OFFSET 3 00087 #define MR2_OFFSET 6 00088 #define MR3_OFFSET 9 00089 00090 // Interrupt Register (TnIR, 21.6.1, p493) 00091 #define MR0_INT (1U << 0) 00092 #define MR1_INT (1U << 1) 00093 #define MR2_INT (1U << 2) 00094 #define MR3_INT (1U << 3) 00095 #define CR0_INT (1U << 4) 00096 #define CR1_INT (1U << 5) 00097 00098 /** Macros **/ 00099 // Enable TIMERn 00100 #define TIMER0_INIT() TIMER_INIT(TIMER0) 00101 #define TIMER1_INIT() TIMER_INIT(TIMER1) 00102 #define TIMER2_INIT() TIMER_INIT(TIMER2) 00103 #define TIMER3_INIT() TIMER_INIT(TIMER3) 00104 #define TIMER_INIT(timer) do { \ 00105 SET_BIT_VALUE(LPC_SC->PCONP, TOKENPASTE2(timer,_PCONP_BIT) , 1); /* Enable Timer */ \ 00106 TIMER_BASE(timer)->TCR = 0x2; /* Reset Timer, Table 427 p493 */ \ 00107 } while(0) 00108 00109 // Set Peripheral Clock 00110 #define TIMER0_SETPCLK(clk) TIMER_SETPCLK(TIMER0, clk) 00111 #define TIMER1_SETPCLK(clk) TIMER_SETPCLK(TIMER1, clk) 00112 #define TIMER2_SETPCLK(clk) TIMER_SETPCLK(TIMER2, clk) 00113 #define TIMER3_SETPCLK(clk) TIMER_SETPCLK(TIMER3, clk) 00114 #define TIMER_SETPCLK(timer, clk) TIMER_PCLK_REG(timer) = ((TIMER_PCLK_REG(timer) & (~(3U << TIMER_PCLK_OFFSET(timer)))) | (clk << TIMER_PCLK_OFFSET(timer))) 00115 00116 // Set Prescale Register 00117 #define TIMER0_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER0, value) 00118 #define TIMER1_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER1, value) 00119 #define TIMER2_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER2, value) 00120 #define TIMER3_SETPRESCALE(value) TIMER_SETPRESCALE(TIMER3, value) 00121 #define TIMER_SETPRESCALE(timer, value) TIMER_BASE(timer)->PR = (value) 00122 00123 // Set Match Register (MR0-3, 21.6.7 p496) 00124 #define TIMER0_SETMATCH(id, value) TIMER_SETMATCH(TIMER0, id, value) 00125 #define TIMER1_SETMATCH(id, value) TIMER_SETMATCH(TIMER1, id, value) 00126 #define TIMER2_SETMATCH(id, value) TIMER_SETMATCH(TIMER2, id, value) 00127 #define TIMER3_SETMATCH(id, value) TIMER_SETMATCH(TIMER3, id, value) 00128 #define TIMER_SETMATCH(timer, id, value) TIMER_BASE(timer)->TOKENPASTE2(MR,id) = (value) 00129 00130 // Set Match Control Register (TnMCR, 21.6.8 p496) 00131 #define TIMER0_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER0, id, value) 00132 #define TIMER1_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER1, id, value) 00133 #define TIMER2_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER2, id, value) 00134 #define TIMER3_SETMATCHCONTROL(id, value) TIMER_SETMATCHCONTROL(TIMER3, id, value) 00135 #define TIMER_SETMATCHCONTROL(timer, id, value) TIMER_BASE(timer)->MCR = (value) << (MR ## id ## _OFFSET) 00136 00137 // Enable interrupt for TIMERn 00138 #define TIMER0_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER0) 00139 #define TIMER1_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER1) 00140 #define TIMER2_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER2) 00141 #define TIMER3_ENABLE_INTERRUPT() TIMER_ENABLE_INTERRUPT(TIMER3) 00142 #define TIMER_ENABLE_INTERRUPT(timer) ENABLE_INTERRUPT(TOKENPASTE2(timer,_IRQn)) 00143 00144 // Interrut Register (TnIR, 21.6.1, p493) 00145 #define TIMER0_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER0, value) 00146 #define TIMER1_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER1, value) 00147 #define TIMER2_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER2, value) 00148 #define TIMER3_CLEAR_INTERRUPT(value) TIMER_CLEAR_INTERRUPT(TIMER3, value) 00149 #define TIMER_CLEAR_INTERRUPT(timer, value) TIMER_BASE(timer)->IR = (value) 00150 00151 // Start Timer 00152 #define TIMER0_START() TIMER_START(TIMER0) 00153 #define TIMER1_START() TIMER_START(TIMER1) 00154 #define TIMER2_START() TIMER_START(TIMER2) 00155 #define TIMER3_START() TIMER_START(TIMER3) 00156 #define TIMER_START(timer) TIMER_BASE(timer)->TCR = 0x1 /* Counter Enable, Table 427 p493*/ 00157 00158 // Get Timer Value 00159 #define TIMER0_VALUE() TIMER_VALUE(TIMER0) 00160 #define TIMER1_VALUE() TIMER_VALUE(TIMER1) 00161 #define TIMER2_VALUE() TIMER_VALUE(TIMER2) 00162 #define TIMER3_VALUE() TIMER_VALUE(TIMER3) 00163 #define TIMER_VALUE(timer) (TIMER_BASE(timer)->TC) 00164 00165 #endif
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