Debug demo for ECG

Dependencies:   MAX30003 max32630fthr

Fork of MAX30003_Demo_Debug by MAXIM - TTS Code

Committer:
coreyharris
Date:
Thu Sep 07 18:26:48 2017 +0000
Revision:
6:e380af098d52
Parent:
5:202ed7222217
Added RtoR support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 4:828118be72d0 1 /*******************************************************************************
coreyharris 4:828118be72d0 2 * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
coreyharris 4:828118be72d0 3 *
coreyharris 4:828118be72d0 4 * Permission is hereby granted, free of charge, to any person obtaining a
coreyharris 4:828118be72d0 5 * copy of this software and associated documentation files (the "Software"),
coreyharris 4:828118be72d0 6 * to deal in the Software without restriction, including without limitation
coreyharris 4:828118be72d0 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
coreyharris 4:828118be72d0 8 * and/or sell copies of the Software, and to permit persons to whom the
coreyharris 4:828118be72d0 9 * Software is furnished to do so, subject to the following conditions:
coreyharris 4:828118be72d0 10 *
coreyharris 4:828118be72d0 11 * The above copyright notice and this permission notice shall be included
coreyharris 4:828118be72d0 12 * in all copies or substantial portions of the Software.
coreyharris 4:828118be72d0 13 *
coreyharris 4:828118be72d0 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
coreyharris 4:828118be72d0 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
coreyharris 4:828118be72d0 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
coreyharris 4:828118be72d0 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
coreyharris 4:828118be72d0 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
coreyharris 4:828118be72d0 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
coreyharris 4:828118be72d0 20 * OTHER DEALINGS IN THE SOFTWARE.
coreyharris 4:828118be72d0 21 *
coreyharris 4:828118be72d0 22 * Except as contained in this notice, the name of Maxim Integrated
coreyharris 4:828118be72d0 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
coreyharris 4:828118be72d0 24 * Products, Inc. Branding Policy.
coreyharris 4:828118be72d0 25 *
coreyharris 4:828118be72d0 26 * The mere transfer of this software does not imply any licenses
coreyharris 4:828118be72d0 27 * of trade secrets, proprietary technology, copyrights, patents,
coreyharris 4:828118be72d0 28 * trademarks, maskwork rights, or any other form of intellectual
coreyharris 4:828118be72d0 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
coreyharris 4:828118be72d0 30 * ownership rights.
coreyharris 4:828118be72d0 31 *******************************************************************************
coreyharris 4:828118be72d0 32 */
coreyharris 4:828118be72d0 33
coreyharris 4:828118be72d0 34
coreyharris 0:38c49bc37c7c 35 #include "mbed.h"
coreyharris 0:38c49bc37c7c 36 #include "max32630fthr.h"
coreyharris 0:38c49bc37c7c 37 #include "MAX30003.h"
coreyharris 0:38c49bc37c7c 38
coreyharris 0:38c49bc37c7c 39 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
coreyharris 0:38c49bc37c7c 40
coreyharris 0:38c49bc37c7c 41 void ecg_config(MAX30003 &ecgAFE);
coreyharris 0:38c49bc37c7c 42
coreyharris 0:38c49bc37c7c 43 /* ECG FIFO nearly full callback */
coreyharris 6:e380af098d52 44 volatile bool ecgIntFlag = 0;
coreyharris 0:38c49bc37c7c 45 void ecgFIFO_callback() {
coreyharris 0:38c49bc37c7c 46
coreyharris 6:e380af098d52 47 ecgIntFlag = 1;
coreyharris 0:38c49bc37c7c 48
coreyharris 0:38c49bc37c7c 49 }
coreyharris 0:38c49bc37c7c 50
coreyharris 0:38c49bc37c7c 51 int main()
coreyharris 3:420d5efbd967 52 {
coreyharris 5:202ed7222217 53
coreyharris 5:202ed7222217 54 // Constants
coreyharris 6:e380af098d52 55 const int EINT_STATUS = 1 << 23;
coreyharris 6:e380af098d52 56 const int RTOR_STATUS = 1 << 10;
coreyharris 6:e380af098d52 57 const int RTOR_REG_OFFSET = 10;
coreyharris 6:e380af098d52 58 const float RTOR_LSB_RES = 0.008f;
coreyharris 6:e380af098d52 59 const int FIFO_OVF = 0x7;
coreyharris 6:e380af098d52 60 const int FIFO_VALID_SAMPLE = 0x0;
coreyharris 6:e380af098d52 61 const int FIFO_FAST_SAMPLE = 0x1;
coreyharris 6:e380af098d52 62 const int ETAG_BITS = 0x7;
coreyharris 3:420d5efbd967 63
coreyharris 5:202ed7222217 64 // Ports and serial connections
coreyharris 1:86843c27cc81 65 Serial pc(USBTX, USBRX); // Use USB debug probe for serial link
coreyharris 1:86843c27cc81 66 pc.baud(115200); // Baud rate = 115200
coreyharris 1:86843c27cc81 67
coreyharris 5:202ed7222217 68 DigitalOut rLed(LED1, LED_OFF); // Debug LEDs
coreyharris 0:38c49bc37c7c 69 DigitalOut gLed(LED2, LED_OFF);
coreyharris 0:38c49bc37c7c 70 DigitalOut bLed(LED3, LED_OFF);
coreyharris 0:38c49bc37c7c 71
coreyharris 1:86843c27cc81 72 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
coreyharris 1:86843c27cc81 73 ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt
coreyharris 0:38c49bc37c7c 74
coreyharris 1:86843c27cc81 75 SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
coreyharris 1:86843c27cc81 76 // P5_2 = MISO, P5_0 = SCK
coreyharris 0:38c49bc37c7c 77
coreyharris 4:828118be72d0 78 MAX30003 ecgAFE(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
coreyharris 4:828118be72d0 79 ecg_config( ecgAFE ); // Config ECG
coreyharris 1:86843c27cc81 80
coreyharris 0:38c49bc37c7c 81
coreyharris 4:828118be72d0 82 ecgAFE.writeRegister( MAX30003::SYNCH , 0);
coreyharris 0:38c49bc37c7c 83
coreyharris 6:e380af098d52 84 uint32_t ecgFIFO, RtoR, readECGSamples, idx, ETAG[32], status;
coreyharris 1:86843c27cc81 85 int16_t ecgSample[32];
coreyharris 6:e380af098d52 86 float BPM;
coreyharris 2:812d40f1853d 87
coreyharris 1:86843c27cc81 88 while(1) {
coreyharris 1:86843c27cc81 89
coreyharris 0:38c49bc37c7c 90 /* Read back ECG samples from the FIFO */
coreyharris 6:e380af098d52 91 if( ecgIntFlag ) {
coreyharris 5:202ed7222217 92
coreyharris 6:e380af098d52 93 ecgIntFlag = 0;
coreyharris 2:812d40f1853d 94 pc.printf("Interrupt received....\r\n");
coreyharris 4:828118be72d0 95 status = ecgAFE.readRegister( MAX30003::STATUS ); // Read the STATUS register
coreyharris 6:e380af098d52 96 pc.printf("Status : 0x%x\r\n"
coreyharris 6:e380af098d52 97 "Current BPM is %3.2f\r\n\r\n", status, BPM);
coreyharris 6:e380af098d52 98
coreyharris 6:e380af098d52 99
coreyharris 6:e380af098d52 100 // Check if R-to-R interrupt asserted
coreyharris 6:e380af098d52 101 if( ( status & RTOR_STATUS ) == RTOR_STATUS ){
coreyharris 6:e380af098d52 102
coreyharris 6:e380af098d52 103 pc.printf("R-to-R Interrupt \r\n");
coreyharris 6:e380af098d52 104
coreyharris 6:e380af098d52 105 // Read RtoR register
coreyharris 6:e380af098d52 106 RtoR = ecgAFE.readRegister( MAX30003::RTOR ) >> RTOR_REG_OFFSET;
coreyharris 6:e380af098d52 107
coreyharris 6:e380af098d52 108 // Convert to BPM
coreyharris 6:e380af098d52 109 BPM = 1.0f / ( RtoR * RTOR_LSB_RES / 60.0f );
coreyharris 6:e380af098d52 110
coreyharris 6:e380af098d52 111 // Print RtoR
coreyharris 6:e380af098d52 112 pc.printf("RtoR : %d\r\n\r\n", RtoR);
coreyharris 6:e380af098d52 113
coreyharris 6:e380af098d52 114 }
coreyharris 2:812d40f1853d 115
coreyharris 3:420d5efbd967 116 // Check if EINT interrupt asserted
coreyharris 6:e380af098d52 117 if ( ( status & EINT_STATUS ) == EINT_STATUS ) {
coreyharris 3:420d5efbd967 118
coreyharris 2:812d40f1853d 119 pc.printf("FIFO Interrupt \r\n");
coreyharris 4:828118be72d0 120 readECGSamples = 0; // Reset sample counter
coreyharris 3:420d5efbd967 121
coreyharris 2:812d40f1853d 122 do {
coreyharris 5:202ed7222217 123 ecgFIFO = ecgAFE.readRegister( MAX30003::ECG_FIFO ); // Read FIFO
coreyharris 4:828118be72d0 124 ecgSample[readECGSamples] = ecgFIFO >> 8; // Isolate voltage data
coreyharris 6:e380af098d52 125 ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS; // Isolate ETAG
coreyharris 4:828118be72d0 126 readECGSamples++; // Increment sample counter
coreyharris 3:420d5efbd967 127
coreyharris 3:420d5efbd967 128 // Check that sample is not last sample in FIFO
coreyharris 6:e380af098d52 129 } while ( ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE ||
coreyharris 6:e380af098d52 130 ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE );
coreyharris 1:86843c27cc81 131
coreyharris 4:828118be72d0 132 pc.printf("%d samples read from FIFO \r\n", readECGSamples);
coreyharris 2:812d40f1853d 133
coreyharris 3:420d5efbd967 134 // Check if FIFO has overflowed
coreyharris 6:e380af098d52 135 if( ETAG[readECGSamples - 1] == FIFO_OVF ){
coreyharris 3:420d5efbd967 136 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
coreyharris 3:420d5efbd967 137 }
coreyharris 3:420d5efbd967 138
coreyharris 5:202ed7222217 139 // Print results
coreyharris 4:828118be72d0 140 for( idx = 0; idx < readECGSamples; idx++ ) {
coreyharris 2:812d40f1853d 141 pc.printf("Sample : %6d, \tETAG : 0x%x\r\n", ecgSample[idx], ETAG[idx]);
coreyharris 2:812d40f1853d 142 }
coreyharris 5:202ed7222217 143 pc.printf("\r\n\r\n\r\n");
coreyharris 5:202ed7222217 144
coreyharris 0:38c49bc37c7c 145 }
coreyharris 0:38c49bc37c7c 146 }
coreyharris 0:38c49bc37c7c 147 }
coreyharris 0:38c49bc37c7c 148 }
coreyharris 0:38c49bc37c7c 149
coreyharris 0:38c49bc37c7c 150
coreyharris 0:38c49bc37c7c 151
coreyharris 0:38c49bc37c7c 152
coreyharris 0:38c49bc37c7c 153 void ecg_config(MAX30003& ecgAFE) {
coreyharris 0:38c49bc37c7c 154
coreyharris 1:86843c27cc81 155 // Reset ECG to clear registers
coreyharris 1:86843c27cc81 156 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 157
coreyharris 1:86843c27cc81 158 // General config register setting
coreyharris 1:86843c27cc81 159 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 3:420d5efbd967 160 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel
coreyharris 3:420d5efbd967 161 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
coreyharris 3:420d5efbd967 162 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
coreyharris 3:420d5efbd967 163 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
coreyharris 6:e380af098d52 164 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
coreyharris 3:420d5efbd967 165 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
coreyharris 1:86843c27cc81 166 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 1:86843c27cc81 167
coreyharris 1:86843c27cc81 168
coreyharris 1:86843c27cc81 169 // ECG Config register setting
coreyharris 1:86843c27cc81 170 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 6:e380af098d52 171 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz
coreyharris 6:e380af098d52 172 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz
coreyharris 6:e380af098d52 173 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V
coreyharris 6:e380af098d52 174 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps
coreyharris 1:86843c27cc81 175 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 1:86843c27cc81 176
coreyharris 1:86843c27cc81 177
coreyharris 1:86843c27cc81 178 //R-to-R configuration
coreyharris 1:86843c27cc81 179 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 6:e380af098d52 180 CNFG_RTOR_r.bits.wndw = 0b0011; // WNDW = 96ms
coreyharris 6:e380af098d52 181 CNFG_RTOR_r.bits.rgain = 0b1111; // Auto-scale gain
coreyharris 6:e380af098d52 182 CNFG_RTOR_r.bits.pavg = 0b11; // 16-average
coreyharris 6:e380af098d52 183 CNFG_RTOR_r.bits.ptsf = 0b0011; // PTSF = 4/16
coreyharris 6:e380af098d52 184 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection
coreyharris 1:86843c27cc81 185 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 1:86843c27cc81 186
coreyharris 1:86843c27cc81 187
coreyharris 1:86843c27cc81 188 //Manage interrupts register setting
coreyharris 1:86843c27cc81 189 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 3:420d5efbd967 190 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples
coreyharris 3:420d5efbd967 191 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back
coreyharris 1:86843c27cc81 192 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 193
coreyharris 0:38c49bc37c7c 194
coreyharris 1:86843c27cc81 195 //Enable interrupts register setting
coreyharris 1:86843c27cc81 196 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 3:420d5efbd967 197 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt
coreyharris 6:e380af098d52 198 EN_INT_r.bits.en_rrint = 1; // Enable R-to-R interrupt
coreyharris 6:e380af098d52 199 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup
coreyharris 1:86843c27cc81 200 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 1:86843c27cc81 201
coreyharris 1:86843c27cc81 202
coreyharris 1:86843c27cc81 203 //Dyanmic modes config
coreyharris 1:86843c27cc81 204 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 3:420d5efbd967 205 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled
coreyharris 1:86843c27cc81 206 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 4:828118be72d0 207
coreyharris 4:828118be72d0 208 // MUX Config
coreyharris 4:828118be72d0 209 MAX30003::MuxConfiguration_u CNFG_MUX_r;
coreyharris 4:828118be72d0 210 CNFG_MUX_r.bits.openn = 0; // Connect ECGN to AFE channel
coreyharris 4:828118be72d0 211 CNFG_MUX_r.bits.openp = 0; // Connect ECGP to AFE channel
coreyharris 4:828118be72d0 212 ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
coreyharris 0:38c49bc37c7c 213
coreyharris 1:86843c27cc81 214 return;
coreyharris 0:38c49bc37c7c 215 }
coreyharris 0:38c49bc37c7c 216