John Greene / Mbed OS MAX30003_Demo_Debug

Debug demo for ECG

Dependencies:   MAX30003 max32630fthr

Fork of MAX30003_Demo_Debug by Central Applications - Mbed Code repo

main.cpp@3:420d5efbd967, 2017-08-22 (annotated)

Committer:
coreyharris
Date:
Tue Aug 22 21:40:49 2017 +0000
Revision:
3:420d5efbd967
Parent:
2:812d40f1853d
Child:
4:828118be72d0
Comments, formatting, constants (done after code review).; ; Still to-do:;  - BPM and RtoR reading/constants

Who changed what in which revision?

UserRevisionLine numberNew contents of line
coreyharris 0:38c49bc37c7c 1 #include "mbed.h"
coreyharris 0:38c49bc37c7c 2 #include "max32630fthr.h"
coreyharris 0:38c49bc37c7c 3 #include "MAX30003.h"
coreyharris 0:38c49bc37c7c 4
coreyharris 0:38c49bc37c7c 5 MAX32630FTHR pegasus(MAX32630FTHR::VIO_3V3);
coreyharris 0:38c49bc37c7c 6
coreyharris 0:38c49bc37c7c 7 void ecg_config(MAX30003 &ecgAFE);
coreyharris 0:38c49bc37c7c 8
coreyharris 0:38c49bc37c7c 9 /* ECG FIFO nearly full callback */
coreyharris 0:38c49bc37c7c 10 volatile bool ecgFIFOIntFlag = 0;
coreyharris 0:38c49bc37c7c 11 void ecgFIFO_callback() {
coreyharris 0:38c49bc37c7c 12
coreyharris 0:38c49bc37c7c 13 ecgFIFOIntFlag = 1;
coreyharris 0:38c49bc37c7c 14
coreyharris 0:38c49bc37c7c 15 }
coreyharris 0:38c49bc37c7c 16
coreyharris 0:38c49bc37c7c 17 int main()
coreyharris 3:420d5efbd967 18 {
coreyharris 3:420d5efbd967 19 const int RTOR_STATUS_MASK = ( 1<<10 );
coreyharris 3:420d5efbd967 20 const int EINT_STATUS_MASK = ( 1<<23 );
coreyharris 3:420d5efbd967 21
coreyharris 1:86843c27cc81 22 Serial pc(USBTX, USBRX); // Use USB debug probe for serial link
coreyharris 1:86843c27cc81 23 pc.baud(115200); // Baud rate = 115200
coreyharris 1:86843c27cc81 24
coreyharris 1:86843c27cc81 25 DigitalOut rLed(LED1, LED_OFF); // Debug LEDs
coreyharris 0:38c49bc37c7c 26 DigitalOut gLed(LED2, LED_OFF);
coreyharris 0:38c49bc37c7c 27 DigitalOut bLed(LED3, LED_OFF);
coreyharris 0:38c49bc37c7c 28
coreyharris 1:86843c27cc81 29 InterruptIn ecgFIFO_int(P5_4); // Config P5_4 as int. in for the
coreyharris 1:86843c27cc81 30 ecgFIFO_int.fall(&ecgFIFO_callback); // ecg FIFO almost full interrupt
coreyharris 0:38c49bc37c7c 31
coreyharris 1:86843c27cc81 32 SPI spiBus(SPI2_MOSI, SPI2_MISO, SPI2_SCK); // SPI bus, P5_1 = MOSI,
coreyharris 1:86843c27cc81 33 // P5_2 = MISO, P5_0 = SCK
coreyharris 0:38c49bc37c7c 34
coreyharris 3:420d5efbd967 35 MAX30003 * ecgAFE;
coreyharris 1:86843c27cc81 36 ecgAFE = new MAX30003(spiBus, P5_3); // New MAX30003 on spiBus, CS = P5_3
coreyharris 1:86843c27cc81 37 ecg_config(*ecgAFE); // Config ECG
coreyharris 1:86843c27cc81 38
coreyharris 0:38c49bc37c7c 39
coreyharris 1:86843c27cc81 40 ecgAFE->writeRegister( MAX30003::SYNCH , 0);
coreyharris 0:38c49bc37c7c 41
coreyharris 2:812d40f1853d 42 uint32_t ecgFIFO, readSamples, idx, ETAG[32], status, RtoR;
coreyharris 1:86843c27cc81 43 int16_t ecgSample[32];
coreyharris 2:812d40f1853d 44 float BPM;
coreyharris 2:812d40f1853d 45
coreyharris 1:86843c27cc81 46 while(1) {
coreyharris 1:86843c27cc81 47
coreyharris 0:38c49bc37c7c 48 /* Read back ECG samples from the FIFO */
coreyharris 0:38c49bc37c7c 49 if( ecgFIFOIntFlag ) {
coreyharris 2:812d40f1853d 50 pc.printf("Interrupt received....\r\n");
coreyharris 3:420d5efbd967 51 status = ecgAFE->readRegister( MAX30003::STATUS ); // Read the STATUS register
coreyharris 3:420d5efbd967 52 pc.printf("Status : 0x%x\r\n"
coreyharris 3:420d5efbd967 53 "Current BPM is %3.2f\r\n\r\n", status, BPM);
coreyharris 2:812d40f1853d 54
coreyharris 3:420d5efbd967 55 // Check if R-to-R interrupt asserted
coreyharris 3:420d5efbd967 56 if( ( status & RTOR_STATUS_MASK ) == RTOR_STATUS_MASK ){ // Check if RtoR update
coreyharris 2:812d40f1853d 57
coreyharris 2:812d40f1853d 58 ecgFIFOIntFlag = 0;
coreyharris 2:812d40f1853d 59 pc.printf("R-to-R Interrupt \r\n");
coreyharris 3:420d5efbd967 60 RtoR = ecgAFE->readRegister( MAX30003::RTOR ); // Read RtoR register
coreyharris 3:420d5efbd967 61 BPM = 60.0*RtoR/32768.0; // Convert to BPM
coreyharris 3:420d5efbd967 62 pc.printf("RtoR : %d\r\n\r\n", RtoR); // Print BPM/RtoR
coreyharris 3:420d5efbd967 63
coreyharris 2:812d40f1853d 64 }
coreyharris 2:812d40f1853d 65
coreyharris 3:420d5efbd967 66 // Check if EINT interrupt asserted
coreyharris 3:420d5efbd967 67 if ( ( status & EINT_STATUS_MASK ) == EINT_STATUS_MASK ) {
coreyharris 3:420d5efbd967 68
coreyharris 3:420d5efbd967 69 ecgFIFOIntFlag = 0;
coreyharris 2:812d40f1853d 70 pc.printf("FIFO Interrupt \r\n");
coreyharris 3:420d5efbd967 71 readSamples = 0; // Reset sample counter
coreyharris 3:420d5efbd967 72
coreyharris 2:812d40f1853d 73 do {
coreyharris 2:812d40f1853d 74 ecgFIFO = ecgAFE->readRegister( MAX30003::ECG_FIFO ); // Read FIFO
coreyharris 2:812d40f1853d 75 ecgSample[readSamples] = ecgFIFO >> 8; // Isolate voltage data
coreyharris 2:812d40f1853d 76 ETAG[readSamples] = ( ecgFIFO >> 3 ) & 0b111; // Isolate ETAG
coreyharris 2:812d40f1853d 77 readSamples++; // Increment sample counter
coreyharris 3:420d5efbd967 78
coreyharris 3:420d5efbd967 79 // Check that sample is not last sample in FIFO
coreyharris 3:420d5efbd967 80 } while ( ETAG[readSamples-1] == 0x0 ||
coreyharris 3:420d5efbd967 81 ETAG[readSamples-1] == 0x1 );
coreyharris 1:86843c27cc81 82
coreyharris 2:812d40f1853d 83 pc.printf("%d samples read from FIFO \r\n", readSamples);
coreyharris 2:812d40f1853d 84
coreyharris 3:420d5efbd967 85 // Check if FIFO has overflowed
coreyharris 3:420d5efbd967 86 if( ETAG[readECGSamples - 1] == 0x7 ){
coreyharris 3:420d5efbd967 87 ecgAFE.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
coreyharris 3:420d5efbd967 88 }
coreyharris 3:420d5efbd967 89
coreyharris 3:420d5efbd967 90 /* Print results */
coreyharris 2:812d40f1853d 91 for( idx = 0; idx < readSamples; idx++ ) {
coreyharris 2:812d40f1853d 92 pc.printf("Sample : %6d, \tETAG : 0x%x\r\n", ecgSample[idx], ETAG[idx]);
coreyharris 2:812d40f1853d 93 }
coreyharris 2:812d40f1853d 94 pc.printf("\r\n\r\n\r\n");
coreyharris 0:38c49bc37c7c 95 }
coreyharris 2:812d40f1853d 96
coreyharris 0:38c49bc37c7c 97 }
coreyharris 0:38c49bc37c7c 98 }
coreyharris 0:38c49bc37c7c 99 }
coreyharris 0:38c49bc37c7c 100
coreyharris 0:38c49bc37c7c 101
coreyharris 0:38c49bc37c7c 102
coreyharris 0:38c49bc37c7c 103
coreyharris 0:38c49bc37c7c 104 void ecg_config(MAX30003& ecgAFE) {
coreyharris 0:38c49bc37c7c 105
coreyharris 1:86843c27cc81 106 // Reset ECG to clear registers
coreyharris 1:86843c27cc81 107 ecgAFE.writeRegister( MAX30003::SW_RST , 0);
coreyharris 0:38c49bc37c7c 108
coreyharris 1:86843c27cc81 109 // General config register setting
coreyharris 1:86843c27cc81 110 MAX30003::GeneralConfiguration_u CNFG_GEN_r;
coreyharris 3:420d5efbd967 111 CNFG_GEN_r.bits.en_ecg = 1; // Enable ECG channel
coreyharris 3:420d5efbd967 112 CNFG_GEN_r.bits.rbiasn = 1; // Enable resistive bias on negative input
coreyharris 3:420d5efbd967 113 CNFG_GEN_r.bits.rbiasp = 1; // Enable resistive bias on positive input
coreyharris 3:420d5efbd967 114 CNFG_GEN_r.bits.en_rbias = 1; // Enable resistive bias
coreyharris 3:420d5efbd967 115 CNFG_GEN_r.bits.imag = 2; // Current magnitude = 10nA
coreyharris 3:420d5efbd967 116 CNFG_GEN_r.bits.en_dcloff = 1; // Enable DC lead-off detection
coreyharris 1:86843c27cc81 117 ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
coreyharris 1:86843c27cc81 118
coreyharris 1:86843c27cc81 119
coreyharris 1:86843c27cc81 120 // ECG Config register setting
coreyharris 1:86843c27cc81 121 MAX30003::ECGConfiguration_u CNFG_ECG_r;
coreyharris 3:420d5efbd967 122 CNFG_ECG_r.bits.dlpf = 1; // Digital LPF cutoff = 40Hz
coreyharris 3:420d5efbd967 123 CNFG_ECG_r.bits.dhpf = 1; // Digital HPF cutoff = 0.5Hz
coreyharris 3:420d5efbd967 124 CNFG_ECG_r.bits.gain = 3; // ECG gain = 160V/V
coreyharris 3:420d5efbd967 125 CNFG_ECG_r.bits.rate = 2; // Sample rate = 128 sps
coreyharris 1:86843c27cc81 126 ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
coreyharris 1:86843c27cc81 127
coreyharris 1:86843c27cc81 128
coreyharris 1:86843c27cc81 129 //R-to-R configuration
coreyharris 1:86843c27cc81 130 MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
coreyharris 3:420d5efbd967 131 CNFG_RTOR_r.bits.en_rtor = 1; // Enable R-to-R detection
coreyharris 1:86843c27cc81 132 ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
coreyharris 1:86843c27cc81 133
coreyharris 1:86843c27cc81 134
coreyharris 1:86843c27cc81 135 //Manage interrupts register setting
coreyharris 1:86843c27cc81 136 MAX30003::ManageInterrupts_u MNG_INT_r;
coreyharris 3:420d5efbd967 137 MNG_INT_r.bits.efit = 0b00011; // Assert EINT w/ 4 unread samples
coreyharris 3:420d5efbd967 138 MNG_INT_r.bits.clr_rrint = 0b01; // Clear R-to-R on RTOR reg. read back
coreyharris 1:86843c27cc81 139 ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
coreyharris 0:38c49bc37c7c 140
coreyharris 0:38c49bc37c7c 141
coreyharris 1:86843c27cc81 142 //Enable interrupts register setting
coreyharris 1:86843c27cc81 143 MAX30003::EnableInterrupts_u EN_INT_r;
coreyharris 3:420d5efbd967 144 EN_INT_r.bits.en_eint = 1; // Enable EINT interrupt
coreyharris 3:420d5efbd967 145 EN_INT_r.bits.en_rrint = 1; // Enable R-to-R interrupt
coreyharris 3:420d5efbd967 146 EN_INT_r.bits.intb_type = 3; // Open-drain NMOS with internal pullup
coreyharris 1:86843c27cc81 147 ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
coreyharris 1:86843c27cc81 148
coreyharris 1:86843c27cc81 149
coreyharris 1:86843c27cc81 150 //Dyanmic modes config
coreyharris 1:86843c27cc81 151 MAX30003::ManageDynamicModes_u MNG_DYN_r;
coreyharris 3:420d5efbd967 152 MNG_DYN_r.bits.fast = 0; // Fast recovery mode disabled
coreyharris 1:86843c27cc81 153 ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
coreyharris 1:86843c27cc81 154
coreyharris 0:38c49bc37c7c 155
coreyharris 1:86843c27cc81 156 return;
coreyharris 0:38c49bc37c7c 157 }
coreyharris 0:38c49bc37c7c 158