John Mitchell / DMSupport

Subdirectory provided by Embedded Artists

Dependencies:   DM_FATFileSystem DM_HttpServer DM_USBHost EthernetInterface USBDevice mbed-rpc mbed-rtos mbed-src

Dependents:   lpc4088_displaymodule_hello_world_Sept_2018

Fork of DMSupport by Embedded Artists

Memory/sdram.cpp@10:1ac4b213f0f7, 2014-12-19 (annotated)

Committer:
embeddedartists
Date:
Fri Dec 19 09:03:25 2014 +0100
Revision:
10:1ac4b213f0f7
Parent:
9:a33326afd686
Child:
30:a97015441bb4
- Added support for executing code in SDRAM.

- Restructured the Display/Touch interfaces.

- Added loading of Display/Touch BIOS.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
embeddedartists 0:6b68dac0d986 1 /*
embeddedartists 9:a33326afd686 2 * Copyright 2014 Embedded Artists AB
embeddedartists 0:6b68dac0d986 3 *
embeddedartists 0:6b68dac0d986 4 * Licensed under the Apache License, Version 2.0 (the "License");
embeddedartists 0:6b68dac0d986 5 * you may not use this file except in compliance with the License.
embeddedartists 0:6b68dac0d986 6 * You may obtain a copy of the License at
embeddedartists 0:6b68dac0d986 7 *
embeddedartists 0:6b68dac0d986 8 * http://www.apache.org/licenses/LICENSE-2.0
embeddedartists 0:6b68dac0d986 9 *
embeddedartists 0:6b68dac0d986 10 * Unless required by applicable law or agreed to in writing, software
embeddedartists 0:6b68dac0d986 11 * distributed under the License is distributed on an "AS IS" BASIS,
embeddedartists 0:6b68dac0d986 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
embeddedartists 0:6b68dac0d986 13 * See the License for the specific language governing permissions and
embeddedartists 0:6b68dac0d986 14 * limitations under the License.
embeddedartists 0:6b68dac0d986 15 */
embeddedartists 0:6b68dac0d986 16
embeddedartists 0:6b68dac0d986 17
embeddedartists 0:6b68dac0d986 18 /******************************************************************************
embeddedartists 0:6b68dac0d986 19 * Includes
embeddedartists 0:6b68dac0d986 20 *****************************************************************************/
embeddedartists 0:6b68dac0d986 21
embeddedartists 0:6b68dac0d986 22 #include "mbed.h"
embeddedartists 0:6b68dac0d986 23 #include "sdram.h"
embeddedartists 0:6b68dac0d986 24
embeddedartists 0:6b68dac0d986 25 #if defined(TOOLCHAIN_ARM) /* KEIL uVision and mbed online compiler */
embeddedartists 0:6b68dac0d986 26 #include "sys_helper.h"
embeddedartists 0:6b68dac0d986 27 #endif
embeddedartists 0:6b68dac0d986 28
embeddedartists 0:6b68dac0d986 29 /******************************************************************************
embeddedartists 0:6b68dac0d986 30 * Defines and typedefs
embeddedartists 0:6b68dac0d986 31 *****************************************************************************/
embeddedartists 0:6b68dac0d986 32
embeddedartists 0:6b68dac0d986 33
embeddedartists 0:6b68dac0d986 34 /******************************************************************************
embeddedartists 0:6b68dac0d986 35 * External global variables
embeddedartists 0:6b68dac0d986 36 *****************************************************************************/
embeddedartists 0:6b68dac0d986 37
embeddedartists 0:6b68dac0d986 38 /******************************************************************************
embeddedartists 0:6b68dac0d986 39 * Local variables
embeddedartists 0:6b68dac0d986 40 *****************************************************************************/
embeddedartists 0:6b68dac0d986 41
embeddedartists 0:6b68dac0d986 42 static volatile uint32_t ringosccount[2] = {0,0};
embeddedartists 0:6b68dac0d986 43
embeddedartists 0:6b68dac0d986 44 static bool okToUseSdramForHeap = true;
embeddedartists 0:6b68dac0d986 45 static bool initialized = false;
embeddedartists 0:6b68dac0d986 46
embeddedartists 0:6b68dac0d986 47 /******************************************************************************
embeddedartists 0:6b68dac0d986 48 * Overridden Global Functions
embeddedartists 0:6b68dac0d986 49 *****************************************************************************/
embeddedartists 0:6b68dac0d986 50
embeddedartists 0:6b68dac0d986 51 #if defined(TOOLCHAIN_ARM) /* KEIL uVision and mbed online compiler */
embeddedartists 0:6b68dac0d986 52 //http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0349c/Cihehbce.html
embeddedartists 0:6b68dac0d986 53
embeddedartists 0:6b68dac0d986 54 extern "C" unsigned __rt_heap_extend(unsigned size, void **block) {
embeddedartists 0:6b68dac0d986 55 static uint32_t lastReturnedBlock = 0;
embeddedartists 0:6b68dac0d986 56
embeddedartists 0:6b68dac0d986 57 if (okToUseSdramForHeap && !initialized) {
embeddedartists 0:6b68dac0d986 58 sdram_init();
embeddedartists 0:6b68dac0d986 59 }
embeddedartists 0:6b68dac0d986 60
embeddedartists 0:6b68dac0d986 61 // Make sure that SDRAM is only returned once (as all of it is returned
embeddedartists 0:6b68dac0d986 62 // the first time) and only if the user has chosen to do it (via the
embeddedartists 0:6b68dac0d986 63 // okToUseSdramForHeap variable.
embeddedartists 0:6b68dac0d986 64 if (okToUseSdramForHeap && lastReturnedBlock==0) {
embeddedartists 0:6b68dac0d986 65 *block = (void*)SDRAM_BASE;
embeddedartists 0:6b68dac0d986 66 lastReturnedBlock = SDRAM_BASE;
embeddedartists 0:6b68dac0d986 67 return SDRAM_SIZE;
embeddedartists 0:6b68dac0d986 68 }
embeddedartists 0:6b68dac0d986 69 return 0;
embeddedartists 0:6b68dac0d986 70 }
embeddedartists 0:6b68dac0d986 71
embeddedartists 0:6b68dac0d986 72 // Overrides the WEAK function in sys_helper.cpp to allow reserving a specific
embeddedartists 0:6b68dac0d986 73 // amount of memory for the stack. Without this function it is possible to allocate
embeddedartists 0:6b68dac0d986 74 // so much of the internal RAM that there is no free memory for the stack which
embeddedartists 0:6b68dac0d986 75 // in turn causes the program to crash.
embeddedartists 0:6b68dac0d986 76 uint32_t __reserved_stack_size() {
embeddedartists 0:6b68dac0d986 77 return 0x3000; // Reserve 0x3000 bytes of the IRAM for the stack
embeddedartists 0:6b68dac0d986 78 }
embeddedartists 0:6b68dac0d986 79
embeddedartists 0:6b68dac0d986 80 #elif defined(TOOLCHAIN_GCC_CR) /* CodeRed's RedSuite or LPCXpresso IDE */
embeddedartists 0:6b68dac0d986 81
embeddedartists 0:6b68dac0d986 82 // NOTE: This way of overriding the implementation of malloc in NEWLIB
embeddedartists 0:6b68dac0d986 83 // will prevent the internal RAM from being used by malloc as
embeddedartists 0:6b68dac0d986 84 // it only exposes the SDRAM.
embeddedartists 0:6b68dac0d986 85
embeddedartists 0:6b68dac0d986 86 // Dynamic memory allocation related syscall.
embeddedartists 0:6b68dac0d986 87 extern "C" caddr_t _sbrk(int incr) {
embeddedartists 0:6b68dac0d986 88 static unsigned char* heap = (unsigned char*)SDRAM_BASE;
embeddedartists 0:6b68dac0d986 89 unsigned char* prev_heap = heap;
embeddedartists 0:6b68dac0d986 90 unsigned char* new_heap = heap + incr;
embeddedartists 0:6b68dac0d986 91
embeddedartists 0:6b68dac0d986 92 if (okToUseSdramForHeap && !initialized) {
embeddedartists 0:6b68dac0d986 93 sdram_init();
embeddedartists 0:6b68dac0d986 94 }
embeddedartists 0:6b68dac0d986 95 if (!okToUseSdramForHeap) {
embeddedartists 0:6b68dac0d986 96 //errno = ENOMEM;
embeddedartists 0:6b68dac0d986 97 return (caddr_t)-1;
embeddedartists 0:6b68dac0d986 98 }
embeddedartists 0:6b68dac0d986 99 if (new_heap >= (unsigned char*)(SDRAM_BASE + SDRAM_SIZE)) {
embeddedartists 0:6b68dac0d986 100 //errno = ENOMEM;
embeddedartists 0:6b68dac0d986 101 return (caddr_t)-1;
embeddedartists 0:6b68dac0d986 102 }
embeddedartists 0:6b68dac0d986 103
embeddedartists 0:6b68dac0d986 104 heap = new_heap;
embeddedartists 0:6b68dac0d986 105 return (caddr_t) prev_heap;
embeddedartists 0:6b68dac0d986 106 }
embeddedartists 0:6b68dac0d986 107 #endif
embeddedartists 0:6b68dac0d986 108
embeddedartists 0:6b68dac0d986 109 /******************************************************************************
embeddedartists 0:6b68dac0d986 110 * Local Functions
embeddedartists 0:6b68dac0d986 111 *****************************************************************************/
embeddedartists 0:6b68dac0d986 112
embeddedartists 0:6b68dac0d986 113 static void pinConfig(void)
embeddedartists 0:6b68dac0d986 114 {
embeddedartists 0:6b68dac0d986 115 LPC_IOCON->P3_0 |= 1; /* D0 @ P3.0 */
embeddedartists 0:6b68dac0d986 116 LPC_IOCON->P3_1 |= 1; /* D1 @ P3.1 */
embeddedartists 0:6b68dac0d986 117 LPC_IOCON->P3_2 |= 1; /* D2 @ P3.2 */
embeddedartists 0:6b68dac0d986 118 LPC_IOCON->P3_3 |= 1; /* D3 @ P3.3 */
embeddedartists 0:6b68dac0d986 119
embeddedartists 0:6b68dac0d986 120 LPC_IOCON->P3_4 |= 1; /* D4 @ P3.4 */
embeddedartists 0:6b68dac0d986 121 LPC_IOCON->P3_5 |= 1; /* D5 @ P3.5 */
embeddedartists 0:6b68dac0d986 122 LPC_IOCON->P3_6 |= 1; /* D6 @ P3.6 */
embeddedartists 0:6b68dac0d986 123 LPC_IOCON->P3_7 |= 1; /* D7 @ P3.7 */
embeddedartists 0:6b68dac0d986 124
embeddedartists 0:6b68dac0d986 125 LPC_IOCON->P3_8 |= 1; /* D8 @ P3.8 */
embeddedartists 0:6b68dac0d986 126 LPC_IOCON->P3_9 |= 1; /* D9 @ P3.9 */
embeddedartists 0:6b68dac0d986 127 LPC_IOCON->P3_10 |= 1; /* D10 @ P3.10 */
embeddedartists 0:6b68dac0d986 128 LPC_IOCON->P3_11 |= 1; /* D11 @ P3.11 */
embeddedartists 0:6b68dac0d986 129
embeddedartists 0:6b68dac0d986 130 LPC_IOCON->P3_12 |= 1; /* D12 @ P3.12 */
embeddedartists 0:6b68dac0d986 131 LPC_IOCON->P3_13 |= 1; /* D13 @ P3.13 */
embeddedartists 0:6b68dac0d986 132 LPC_IOCON->P3_14 |= 1; /* D14 @ P3.14 */
embeddedartists 0:6b68dac0d986 133 LPC_IOCON->P3_15 |= 1; /* D15 @ P3.15 */
embeddedartists 0:6b68dac0d986 134
embeddedartists 0:6b68dac0d986 135 LPC_IOCON->P3_16 |= 1; /* D16 @ P3.16 */
embeddedartists 0:6b68dac0d986 136 LPC_IOCON->P3_17 |= 1; /* D17 @ P3.17 */
embeddedartists 0:6b68dac0d986 137 LPC_IOCON->P3_18 |= 1; /* D18 @ P3.18 */
embeddedartists 0:6b68dac0d986 138 LPC_IOCON->P3_19 |= 1; /* D19 @ P3.19 */
embeddedartists 0:6b68dac0d986 139
embeddedartists 0:6b68dac0d986 140 LPC_IOCON->P3_20 |= 1; /* D20 @ P3.20 */
embeddedartists 0:6b68dac0d986 141 LPC_IOCON->P3_21 |= 1; /* D21 @ P3.21 */
embeddedartists 0:6b68dac0d986 142 LPC_IOCON->P3_22 |= 1; /* D22 @ P3.22 */
embeddedartists 0:6b68dac0d986 143 LPC_IOCON->P3_23 |= 1; /* D23 @ P3.23 */
embeddedartists 0:6b68dac0d986 144
embeddedartists 0:6b68dac0d986 145 LPC_IOCON->P3_24 |= 1; /* D24 @ P3.24 */
embeddedartists 0:6b68dac0d986 146 LPC_IOCON->P3_25 |= 1; /* D25 @ P3.25 */
embeddedartists 0:6b68dac0d986 147 LPC_IOCON->P3_26 |= 1; /* D26 @ P3.26 */
embeddedartists 0:6b68dac0d986 148 LPC_IOCON->P3_27 |= 1; /* D27 @ P3.27 */
embeddedartists 0:6b68dac0d986 149
embeddedartists 0:6b68dac0d986 150 LPC_IOCON->P3_28 |= 1; /* D28 @ P3.28 */
embeddedartists 0:6b68dac0d986 151 LPC_IOCON->P3_29 |= 1; /* D29 @ P3.29 */
embeddedartists 0:6b68dac0d986 152 LPC_IOCON->P3_30 |= 1; /* D30 @ P3.30 */
embeddedartists 0:6b68dac0d986 153 LPC_IOCON->P3_31 |= 1; /* D31 @ P3.31 */
embeddedartists 0:6b68dac0d986 154
embeddedartists 0:6b68dac0d986 155 LPC_IOCON->P4_0 |= 1; /* A0 @ P4.0 */
embeddedartists 0:6b68dac0d986 156 LPC_IOCON->P4_1 |= 1; /* A1 @ P4.1 */
embeddedartists 0:6b68dac0d986 157 LPC_IOCON->P4_2 |= 1; /* A2 @ P4.2 */
embeddedartists 0:6b68dac0d986 158 LPC_IOCON->P4_3 |= 1; /* A3 @ P4.3 */
embeddedartists 0:6b68dac0d986 159
embeddedartists 0:6b68dac0d986 160 LPC_IOCON->P4_4 |= 1; /* A4 @ P4.4 */
embeddedartists 0:6b68dac0d986 161 LPC_IOCON->P4_5 |= 1; /* A5 @ P4.5 */
embeddedartists 0:6b68dac0d986 162 LPC_IOCON->P4_6 |= 1; /* A6 @ P4.6 */
embeddedartists 0:6b68dac0d986 163 LPC_IOCON->P4_7 |= 1; /* A7 @ P4.7 */
embeddedartists 0:6b68dac0d986 164
embeddedartists 0:6b68dac0d986 165 LPC_IOCON->P4_8 |= 1; /* A8 @ P4.8 */
embeddedartists 0:6b68dac0d986 166 LPC_IOCON->P4_9 |= 1; /* A9 @ P4.9 */
embeddedartists 0:6b68dac0d986 167 LPC_IOCON->P4_10 |= 1; /* A10 @ P4.10 */
embeddedartists 0:6b68dac0d986 168 LPC_IOCON->P4_11 |= 1; /* A11 @ P4.11 */
embeddedartists 0:6b68dac0d986 169
embeddedartists 0:6b68dac0d986 170 LPC_IOCON->P4_12 |= 1; /* A12 @ P4.12 */
embeddedartists 0:6b68dac0d986 171 LPC_IOCON->P4_13 |= 1; /* A13 @ P4.13 */
embeddedartists 0:6b68dac0d986 172 LPC_IOCON->P4_14 |= 1; /* A14 @ P4.14 */
embeddedartists 0:6b68dac0d986 173 #if 0 // not used for SDRAM
embeddedartists 0:6b68dac0d986 174 LPC_IOCON->P4_15 |= 1; /* A15 @ P4.15 */
embeddedartists 0:6b68dac0d986 175
embeddedartists 0:6b68dac0d986 176 LPC_IOCON->P4_16 |= 1; /* A16 @ P4.16 */
embeddedartists 0:6b68dac0d986 177 LPC_IOCON->P4_17 |= 1; /* A17 @ P4.17 */
embeddedartists 0:6b68dac0d986 178 LPC_IOCON->P4_18 |= 1; /* A18 @ P4.18 */
embeddedartists 0:6b68dac0d986 179 LPC_IOCON->P4_19 |= 1; /* A19 @ P4.19 */
embeddedartists 0:6b68dac0d986 180
embeddedartists 0:6b68dac0d986 181 LPC_IOCON->P4_20 |= 1; /* A20 @ P4.20 */
embeddedartists 0:6b68dac0d986 182 LPC_IOCON->P4_21 |= 1; /* A21 @ P4.21 */
embeddedartists 0:6b68dac0d986 183 LPC_IOCON->P4_22 |= 1; /* A22 @ P4.22 */
embeddedartists 0:6b68dac0d986 184 LPC_IOCON->P4_23 |= 1; /* A23 @ P4.23 */
embeddedartists 0:6b68dac0d986 185 #endif
embeddedartists 0:6b68dac0d986 186
embeddedartists 0:6b68dac0d986 187 LPC_IOCON->P4_24 |= 1; /* OEN @ P4.24 */
embeddedartists 0:6b68dac0d986 188 LPC_IOCON->P4_25 |= 1; /* WEN @ P4.25 */
embeddedartists 0:6b68dac0d986 189 #if 0 // not used for SDRAM
embeddedartists 0:6b68dac0d986 190 LPC_IOCON->P4_26 |= 1; /* BLSN[0] @ P4.26 */
embeddedartists 0:6b68dac0d986 191 LPC_IOCON->P4_27 |= 1; /* BLSN[1] @ P4.27 */
embeddedartists 0:6b68dac0d986 192
embeddedartists 0:6b68dac0d986 193
embeddedartists 0:6b68dac0d986 194 LPC_IOCON->P4_28 |= 1; /* BLSN[2] @ P4.28 */
embeddedartists 0:6b68dac0d986 195 LPC_IOCON->P4_29 |= 1; /* BLSN[3] @ P4.29 */
embeddedartists 0:6b68dac0d986 196 LPC_IOCON->P4_30 |= 1; /* CSN[0] @ P4.30 */
embeddedartists 0:6b68dac0d986 197 LPC_IOCON->P4_31 |= 1; /* CSN[1] @ P4.31 */
embeddedartists 0:6b68dac0d986 198 #endif
embeddedartists 0:6b68dac0d986 199
embeddedartists 0:6b68dac0d986 200 LPC_IOCON->P2_14 |= 1; /* CSN[2] @ P2.14 */
embeddedartists 0:6b68dac0d986 201 LPC_IOCON->P2_15 |= 1; /* CSN[3] @ P2.15 */
embeddedartists 0:6b68dac0d986 202
embeddedartists 0:6b68dac0d986 203 LPC_IOCON->P2_16 |= 1; /* CASN @ P2.16 */
embeddedartists 0:6b68dac0d986 204 LPC_IOCON->P2_17 |= 1; /* RASN @ P2.17 */
embeddedartists 0:6b68dac0d986 205 LPC_IOCON->P2_18 |= 1; /* CLK[0] @ P2.18 */
embeddedartists 0:6b68dac0d986 206 #if 0 // not used for SDRAM
embeddedartists 0:6b68dac0d986 207 LPC_IOCON->P2_19 |= 1; /* CLK[1] @ P2.19 */
embeddedartists 0:6b68dac0d986 208 #endif
embeddedartists 0:6b68dac0d986 209
embeddedartists 0:6b68dac0d986 210 LPC_IOCON->P2_20 |= 1; /* DYCSN[0] @ P2.20 */
embeddedartists 0:6b68dac0d986 211 #if 0 // not used for SDRAM
embeddedartists 0:6b68dac0d986 212 LPC_IOCON->P2_21 |= 1; /* DYCSN[1] @ P2.21 */
embeddedartists 0:6b68dac0d986 213 LPC_IOCON->P2_22 |= 1; /* DYCSN[2] @ P2.22 */
embeddedartists 0:6b68dac0d986 214 LPC_IOCON->P2_23 |= 1; /* DYCSN[3] @ P2.23 */
embeddedartists 0:6b68dac0d986 215 #endif
embeddedartists 0:6b68dac0d986 216
embeddedartists 0:6b68dac0d986 217 LPC_IOCON->P2_24 |= 1; /* CKE[0] @ P2.24 */
embeddedartists 0:6b68dac0d986 218 #if 0 // not used for SDRAM
embeddedartists 0:6b68dac0d986 219 LPC_IOCON->P2_25 |= 1; /* CKE[1] @ P2.25 */
embeddedartists 0:6b68dac0d986 220 LPC_IOCON->P2_26 |= 1; /* CKE[2] @ P2.26 */
embeddedartists 0:6b68dac0d986 221 LPC_IOCON->P2_27 |= 1; /* CKE[3] @ P2.27 */
embeddedartists 0:6b68dac0d986 222 #endif
embeddedartists 0:6b68dac0d986 223
embeddedartists 0:6b68dac0d986 224 LPC_IOCON->P2_28 |= 1; /* DQM[0] @ P2.28 */
embeddedartists 0:6b68dac0d986 225 LPC_IOCON->P2_29 |= 1; /* DQM[1] @ P2.29 */
embeddedartists 0:6b68dac0d986 226 LPC_IOCON->P2_30 |= 1; /* DQM[2] @ P2.30 */
embeddedartists 0:6b68dac0d986 227 LPC_IOCON->P2_31 |= 1; /* DQM[3] @ P2.31 */
embeddedartists 0:6b68dac0d986 228 }
embeddedartists 0:6b68dac0d986 229
embeddedartists 0:6b68dac0d986 230
embeddedartists 0:6b68dac0d986 231 static uint32_t sdram_test( void )
embeddedartists 0:6b68dac0d986 232 {
embeddedartists 0:6b68dac0d986 233 volatile uint32_t *wr_ptr;
embeddedartists 0:6b68dac0d986 234 volatile uint16_t *short_wr_ptr;
embeddedartists 0:6b68dac0d986 235 uint32_t data;
embeddedartists 0:6b68dac0d986 236 uint32_t i, j;
embeddedartists 0:6b68dac0d986 237
embeddedartists 0:6b68dac0d986 238 wr_ptr = (uint32_t *)SDRAM_BASE;
embeddedartists 0:6b68dac0d986 239 short_wr_ptr = (uint16_t *)wr_ptr;
embeddedartists 0:6b68dac0d986 240 /* Clear content before 16 bit access test */
embeddedartists 0:6b68dac0d986 241 // for (i = 0; i < SDRAM_SIZE/4; i++)
embeddedartists 0:6b68dac0d986 242 // {
embeddedartists 0:6b68dac0d986 243 // *wr_ptr++ = 0;
embeddedartists 0:6b68dac0d986 244 // }
embeddedartists 0:6b68dac0d986 245
embeddedartists 0:6b68dac0d986 246 /* 16 bit write */
embeddedartists 0:6b68dac0d986 247 for (i = 0; i < SDRAM_SIZE/0x40000; i++)
embeddedartists 0:6b68dac0d986 248 {
embeddedartists 0:6b68dac0d986 249 for (j = 0; j < 0x100; j++)
embeddedartists 0:6b68dac0d986 250 {
embeddedartists 0:6b68dac0d986 251 *short_wr_ptr++ = (i + j);
embeddedartists 0:6b68dac0d986 252 *short_wr_ptr++ = (i + j) + 1;
embeddedartists 0:6b68dac0d986 253 }
embeddedartists 0:6b68dac0d986 254 }
embeddedartists 0:6b68dac0d986 255
embeddedartists 0:6b68dac0d986 256 /* Verifying */
embeddedartists 0:6b68dac0d986 257 wr_ptr = (uint32_t *)SDRAM_BASE;
embeddedartists 0:6b68dac0d986 258 for (i = 0; i < SDRAM_SIZE/0x40000; i++)
embeddedartists 0:6b68dac0d986 259 {
embeddedartists 0:6b68dac0d986 260 for (j = 0; j < 0x100; j++)
embeddedartists 0:6b68dac0d986 261 {
embeddedartists 0:6b68dac0d986 262 data = *wr_ptr;
embeddedartists 0:6b68dac0d986 263 if (data != (((((i + j) + 1) & 0xFFFF) << 16) | ((i + j) & 0xFFFF)))
embeddedartists 0:6b68dac0d986 264 {
embeddedartists 0:6b68dac0d986 265 return 0x0;
embeddedartists 0:6b68dac0d986 266 }
embeddedartists 0:6b68dac0d986 267 wr_ptr++;
embeddedartists 0:6b68dac0d986 268 }
embeddedartists 0:6b68dac0d986 269 }
embeddedartists 0:6b68dac0d986 270 return 0x1;
embeddedartists 0:6b68dac0d986 271 }
embeddedartists 0:6b68dac0d986 272
embeddedartists 0:6b68dac0d986 273 static uint32_t find_cmddly(void)
embeddedartists 0:6b68dac0d986 274 {
embeddedartists 0:6b68dac0d986 275 uint32_t cmddly, cmddlystart, cmddlyend, dwtemp;
embeddedartists 0:6b68dac0d986 276 uint32_t ppass = 0x0, pass = 0x0;
embeddedartists 0:6b68dac0d986 277
embeddedartists 0:6b68dac0d986 278 cmddly = 0x0;
embeddedartists 0:6b68dac0d986 279 cmddlystart = cmddlyend = 0xFF;
embeddedartists 0:6b68dac0d986 280
embeddedartists 0:6b68dac0d986 281 while (cmddly < 32)
embeddedartists 0:6b68dac0d986 282 {
embeddedartists 0:6b68dac0d986 283 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F;
embeddedartists 0:6b68dac0d986 284 LPC_SC->EMCDLYCTL = dwtemp | cmddly;
embeddedartists 0:6b68dac0d986 285
embeddedartists 0:6b68dac0d986 286 if (sdram_test() == 0x1)
embeddedartists 0:6b68dac0d986 287 {
embeddedartists 0:6b68dac0d986 288 /* Test passed */
embeddedartists 0:6b68dac0d986 289 if (cmddlystart == 0xFF)
embeddedartists 0:6b68dac0d986 290 {
embeddedartists 0:6b68dac0d986 291 cmddlystart = cmddly;
embeddedartists 0:6b68dac0d986 292 }
embeddedartists 0:6b68dac0d986 293 ppass = 0x1;
embeddedartists 0:6b68dac0d986 294 }
embeddedartists 0:6b68dac0d986 295 else
embeddedartists 0:6b68dac0d986 296 {
embeddedartists 0:6b68dac0d986 297 /* Test failed */
embeddedartists 0:6b68dac0d986 298 if (ppass == 1)
embeddedartists 0:6b68dac0d986 299 {
embeddedartists 0:6b68dac0d986 300 cmddlyend = cmddly;
embeddedartists 0:6b68dac0d986 301 pass = 0x1;
embeddedartists 0:6b68dac0d986 302 ppass = 0x0;
embeddedartists 0:6b68dac0d986 303 }
embeddedartists 0:6b68dac0d986 304 }
embeddedartists 0:6b68dac0d986 305
embeddedartists 0:6b68dac0d986 306 /* Try next value */
embeddedartists 0:6b68dac0d986 307 cmddly++;
embeddedartists 0:6b68dac0d986 308 }
embeddedartists 0:6b68dac0d986 309
embeddedartists 0:6b68dac0d986 310 /* If the test passed, the we can use the average of the min and max values to get an optimal DQSIN delay */
embeddedartists 0:6b68dac0d986 311 if (pass == 0x1)
embeddedartists 0:6b68dac0d986 312 {
embeddedartists 0:6b68dac0d986 313 cmddly = (cmddlystart + cmddlyend) / 2;
embeddedartists 0:6b68dac0d986 314 }
embeddedartists 0:6b68dac0d986 315 else if (ppass == 0x1)
embeddedartists 0:6b68dac0d986 316 {
embeddedartists 0:6b68dac0d986 317 cmddly = (cmddlystart + 0x1F) / 2;
embeddedartists 0:6b68dac0d986 318 }
embeddedartists 0:6b68dac0d986 319 else
embeddedartists 0:6b68dac0d986 320 {
embeddedartists 0:6b68dac0d986 321 /* A working value couldn't be found, just pick something safe so the system doesn't become unstable */
embeddedartists 0:6b68dac0d986 322 cmddly = 0x10;
embeddedartists 0:6b68dac0d986 323 }
embeddedartists 0:6b68dac0d986 324
embeddedartists 0:6b68dac0d986 325 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F;
embeddedartists 0:6b68dac0d986 326 LPC_SC->EMCDLYCTL = dwtemp | cmddly;
embeddedartists 0:6b68dac0d986 327
embeddedartists 0:6b68dac0d986 328 return (pass | ppass);
embeddedartists 0:6b68dac0d986 329 }
embeddedartists 0:6b68dac0d986 330
embeddedartists 0:6b68dac0d986 331 static uint32_t find_fbclkdly(void)
embeddedartists 0:6b68dac0d986 332 {
embeddedartists 0:6b68dac0d986 333 uint32_t fbclkdly, fbclkdlystart, fbclkdlyend, dwtemp;
embeddedartists 0:6b68dac0d986 334 uint32_t ppass = 0x0, pass = 0x0;
embeddedartists 0:6b68dac0d986 335
embeddedartists 0:6b68dac0d986 336 fbclkdly = 0x0;
embeddedartists 0:6b68dac0d986 337 fbclkdlystart = fbclkdlyend = 0xFF;
embeddedartists 0:6b68dac0d986 338
embeddedartists 0:6b68dac0d986 339 while (fbclkdly < 32)
embeddedartists 0:6b68dac0d986 340 {
embeddedartists 0:6b68dac0d986 341 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F00;
embeddedartists 0:6b68dac0d986 342 LPC_SC->EMCDLYCTL = dwtemp | (fbclkdly << 8);
embeddedartists 0:6b68dac0d986 343
embeddedartists 0:6b68dac0d986 344 if (sdram_test() == 0x1)
embeddedartists 0:6b68dac0d986 345 {
embeddedartists 0:6b68dac0d986 346 /* Test passed */
embeddedartists 0:6b68dac0d986 347 if (fbclkdlystart == 0xFF)
embeddedartists 0:6b68dac0d986 348 {
embeddedartists 0:6b68dac0d986 349 fbclkdlystart = fbclkdly;
embeddedartists 0:6b68dac0d986 350 }
embeddedartists 0:6b68dac0d986 351 ppass = 0x1;
embeddedartists 0:6b68dac0d986 352 }
embeddedartists 0:6b68dac0d986 353 else
embeddedartists 0:6b68dac0d986 354 {
embeddedartists 0:6b68dac0d986 355 /* Test failed */
embeddedartists 0:6b68dac0d986 356 if (ppass == 1)
embeddedartists 0:6b68dac0d986 357 {
embeddedartists 0:6b68dac0d986 358 fbclkdlyend = fbclkdly;
embeddedartists 0:6b68dac0d986 359 pass = 0x1;
embeddedartists 0:6b68dac0d986 360 ppass = 0x0;
embeddedartists 0:6b68dac0d986 361 }
embeddedartists 0:6b68dac0d986 362 }
embeddedartists 0:6b68dac0d986 363
embeddedartists 0:6b68dac0d986 364 /* Try next value */
embeddedartists 0:6b68dac0d986 365 fbclkdly++;
embeddedartists 0:6b68dac0d986 366 }
embeddedartists 0:6b68dac0d986 367
embeddedartists 0:6b68dac0d986 368 /* If the test passed, the we can use the average of the min and max values to get an optimal DQSIN delay */
embeddedartists 0:6b68dac0d986 369 if (pass == 0x1)
embeddedartists 0:6b68dac0d986 370 {
embeddedartists 0:6b68dac0d986 371 fbclkdly = (fbclkdlystart + fbclkdlyend) / 2;
embeddedartists 0:6b68dac0d986 372 }
embeddedartists 0:6b68dac0d986 373 else if (ppass == 0x1)
embeddedartists 0:6b68dac0d986 374 {
embeddedartists 0:6b68dac0d986 375 fbclkdly = (fbclkdlystart + 0x1F) / 2;
embeddedartists 0:6b68dac0d986 376 }
embeddedartists 0:6b68dac0d986 377 else
embeddedartists 0:6b68dac0d986 378 {
embeddedartists 0:6b68dac0d986 379 /* A working value couldn't be found, just pick something safe so the system doesn't become unstable */
embeddedartists 0:6b68dac0d986 380 fbclkdly = 0x10;
embeddedartists 0:6b68dac0d986 381 }
embeddedartists 0:6b68dac0d986 382
embeddedartists 0:6b68dac0d986 383 dwtemp = LPC_SC->EMCDLYCTL & ~0x1F00;
embeddedartists 0:6b68dac0d986 384 LPC_SC->EMCDLYCTL = dwtemp | (fbclkdly << 8);
embeddedartists 0:6b68dac0d986 385
embeddedartists 0:6b68dac0d986 386 return (pass | ppass);
embeddedartists 0:6b68dac0d986 387 }
embeddedartists 0:6b68dac0d986 388
embeddedartists 0:6b68dac0d986 389 static uint32_t calibration( void )
embeddedartists 0:6b68dac0d986 390 {
embeddedartists 0:6b68dac0d986 391 uint32_t dwtemp, i;
embeddedartists 0:6b68dac0d986 392 uint32_t cnt = 0;
embeddedartists 0:6b68dac0d986 393
embeddedartists 0:6b68dac0d986 394 for (i = 0; i < 10; i++)
embeddedartists 0:6b68dac0d986 395 {
embeddedartists 0:6b68dac0d986 396 dwtemp = LPC_SC->EMCCAL & ~0x4000;
embeddedartists 0:6b68dac0d986 397 LPC_SC->EMCCAL = dwtemp | 0x4000;
embeddedartists 0:6b68dac0d986 398
embeddedartists 0:6b68dac0d986 399 dwtemp = LPC_SC->EMCCAL;
embeddedartists 0:6b68dac0d986 400 while ((dwtemp & 0x8000) == 0x0000)
embeddedartists 0:6b68dac0d986 401 {
embeddedartists 0:6b68dac0d986 402 dwtemp = LPC_SC->EMCCAL;
embeddedartists 0:6b68dac0d986 403 }
embeddedartists 0:6b68dac0d986 404 cnt += (dwtemp & 0xFF);
embeddedartists 0:6b68dac0d986 405 }
embeddedartists 0:6b68dac0d986 406 return (cnt / 10);
embeddedartists 0:6b68dac0d986 407 }
embeddedartists 0:6b68dac0d986 408
embeddedartists 10:1ac4b213f0f7 409 static void allowExecutionOfCodeInSDRAM(void)
embeddedartists 10:1ac4b213f0f7 410 {
embeddedartists 10:1ac4b213f0f7 411 //----- Adjust MPU to allow execution of code from SDRAM
embeddedartists 10:1ac4b213f0f7 412
embeddedartists 10:1ac4b213f0f7 413 /* Disable MPU */
embeddedartists 10:1ac4b213f0f7 414 MPU->CTRL = 0x00;
embeddedartists 10:1ac4b213f0f7 415
embeddedartists 10:1ac4b213f0f7 416 /* Select to use the default memory map as base and only modify parts */
embeddedartists 10:1ac4b213f0f7 417 MPU->CTRL = 0x04; // PRIVDEFENA=1
embeddedartists 10:1ac4b213f0f7 418
embeddedartists 10:1ac4b213f0f7 419 #define _RBAR(_ADDR, _VALID, _REGION) \
embeddedartists 10:1ac4b213f0f7 420 ((_ADDR) | ((_VALID) << 4) | (_REGION))
embeddedartists 10:1ac4b213f0f7 421
embeddedartists 10:1ac4b213f0f7 422 #define _RASR(_XN, _AP, _TYPE, _SRD, _SIZE, _ENABLE) \
embeddedartists 10:1ac4b213f0f7 423 (((_XN) << 28) | ((_AP) << 24) | ((_TYPE) << 16) | ((_SRD) << 8) | ((_SIZE) << 1) | (_ENABLE))
embeddedartists 10:1ac4b213f0f7 424
embeddedartists 10:1ac4b213f0f7 425 #define AP_RW 0x03 // 011 = Full Access
embeddedartists 10:1ac4b213f0f7 426 #define MEM_TYPE_ERAM 0x07 // Normal, Sharable, Cached, Buffered, write-back & write allocate
embeddedartists 10:1ac4b213f0f7 427 #define SIZE_32M 0x18 // Region size in bytes = 2^(0x18+1) = 32MB
embeddedartists 10:1ac4b213f0f7 428
embeddedartists 10:1ac4b213f0f7 429 /* Setup MPU Region 4 for the SDRAM (0xA0000000 - 0xA1FFFFFF*/
embeddedartists 10:1ac4b213f0f7 430 MPU->RBAR = _RBAR(0xA0000000, 1, 4);
embeddedartists 10:1ac4b213f0f7 431 MPU->RASR = _RASR(0, AP_RW, MEM_TYPE_ERAM, 0, SIZE_32M, 1);
embeddedartists 10:1ac4b213f0f7 432
embeddedartists 10:1ac4b213f0f7 433 /* (Re-)Enable MPU */
embeddedartists 10:1ac4b213f0f7 434 MPU->CTRL |= 0x01;
embeddedartists 10:1ac4b213f0f7 435
embeddedartists 10:1ac4b213f0f7 436 //----- End of MPU adjustments
embeddedartists 10:1ac4b213f0f7 437 }
embeddedartists 10:1ac4b213f0f7 438
embeddedartists 0:6b68dac0d986 439 /******************************************************************************
embeddedartists 0:6b68dac0d986 440 * Public Functions
embeddedartists 0:6b68dac0d986 441 *****************************************************************************/
embeddedartists 0:6b68dac0d986 442
embeddedartists 0:6b68dac0d986 443
embeddedartists 0:6b68dac0d986 444 void adjust_timing( void )
embeddedartists 0:6b68dac0d986 445 {
embeddedartists 0:6b68dac0d986 446 uint32_t dwtemp, cmddly, fbclkdly;
embeddedartists 0:6b68dac0d986 447
embeddedartists 0:6b68dac0d986 448 /* Current value */
embeddedartists 0:6b68dac0d986 449 ringosccount[1] = calibration();
embeddedartists 0:6b68dac0d986 450
embeddedartists 0:6b68dac0d986 451 dwtemp = LPC_SC->EMCDLYCTL;
embeddedartists 0:6b68dac0d986 452 cmddly = ((dwtemp & 0x1F) * ringosccount[0] / ringosccount[1]) & 0x1F;
embeddedartists 0:6b68dac0d986 453 fbclkdly = ((dwtemp & 0x1F00) * ringosccount[0] / ringosccount[1]) & 0x1F00;
embeddedartists 0:6b68dac0d986 454 LPC_SC->EMCDLYCTL = (dwtemp & ~0x1F1F) | fbclkdly | cmddly;
embeddedartists 0:6b68dac0d986 455 }
embeddedartists 0:6b68dac0d986 456
embeddedartists 0:6b68dac0d986 457 /******************************************************************************
embeddedartists 0:6b68dac0d986 458 *
embeddedartists 0:6b68dac0d986 459 * Description:
embeddedartists 0:6b68dac0d986 460 * Initialize the SDRAM
embeddedartists 0:6b68dac0d986 461 *
embeddedartists 0:6b68dac0d986 462 *****************************************************************************/
embeddedartists 0:6b68dac0d986 463 uint32_t sdram_init (void)
embeddedartists 0:6b68dac0d986 464 {
embeddedartists 0:6b68dac0d986 465 uint32_t i;
embeddedartists 0:6b68dac0d986 466 uint32_t dwtemp = 0;
embeddedartists 0:6b68dac0d986 467 //uint16_t wtemp = 0;
embeddedartists 0:6b68dac0d986 468
embeddedartists 0:6b68dac0d986 469 if (initialized) {
embeddedartists 0:6b68dac0d986 470 return 0;
embeddedartists 0:6b68dac0d986 471 }
embeddedartists 0:6b68dac0d986 472
embeddedartists 0:6b68dac0d986 473 LPC_SC->PCONP |= 0x00000800;
embeddedartists 0:6b68dac0d986 474 LPC_SC->EMCDLYCTL = 0x00001010;
embeddedartists 0:6b68dac0d986 475 LPC_EMC->Control = 0x00000001;
embeddedartists 0:6b68dac0d986 476 LPC_EMC->Config = 0x00000000;
embeddedartists 0:6b68dac0d986 477
embeddedartists 0:6b68dac0d986 478 pinConfig(); //Full 32-bit Data bus, 24-bit Address
embeddedartists 0:6b68dac0d986 479
embeddedartists 0:6b68dac0d986 480 /* Configure memory layout, but MUST DISABLE BUFFERs during configuration */
embeddedartists 0:6b68dac0d986 481 /* 256MB, 8Mx32, 4 banks, row=12, column=9 */
embeddedartists 0:6b68dac0d986 482 LPC_EMC->DynamicConfig0 = 0x00004480;
embeddedartists 0:6b68dac0d986 483
embeddedartists 0:6b68dac0d986 484 /*Configure timing for ISSI IS4x32800D SDRAM*/
embeddedartists 0:6b68dac0d986 485
embeddedartists 0:6b68dac0d986 486 #if (SDRAM_SPEED==SDRAM_SPEED_48)
embeddedartists 0:6b68dac0d986 487 //Timing for 48MHz Bus
embeddedartists 0:6b68dac0d986 488 LPC_EMC->DynamicRasCas0 = 0x00000201; /* 1 RAS, 2 CAS latency */
embeddedartists 0:6b68dac0d986 489 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:6b68dac0d986 490 LPC_EMC->DynamicRP = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:6b68dac0d986 491 LPC_EMC->DynamicRAS = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 492 LPC_EMC->DynamicSREX = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 493 LPC_EMC->DynamicAPR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 494 LPC_EMC->DynamicDAL = 0x00000002; /* ( n ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 495 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 496 LPC_EMC->DynamicRC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 497 LPC_EMC->DynamicRFC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 498 LPC_EMC->DynamicXSR = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 499 LPC_EMC->DynamicRRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:6b68dac0d986 500 LPC_EMC->DynamicMRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:6b68dac0d986 501 #elif (SDRAM_SPEED==SDRAM_SPEED_50)
embeddedartists 0:6b68dac0d986 502 //Timing for 50MHz Bus (with 100MHz M3 Core)
embeddedartists 0:6b68dac0d986 503 LPC_EMC->DynamicRasCas0 = 0x00000201; /* 1 RAS, 2 CAS latency */
embeddedartists 0:6b68dac0d986 504 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:6b68dac0d986 505 LPC_EMC->DynamicRP = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:6b68dac0d986 506 LPC_EMC->DynamicRAS = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 507 LPC_EMC->DynamicSREX = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 508 LPC_EMC->DynamicAPR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 509 LPC_EMC->DynamicDAL = 0x00000002; /* ( n ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 510 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 511 LPC_EMC->DynamicRC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 512 LPC_EMC->DynamicRFC = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 513 LPC_EMC->DynamicXSR = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 514 LPC_EMC->DynamicRRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:6b68dac0d986 515 LPC_EMC->DynamicMRD = 0x00000000; /* ( n + 1 ) -> 1 clock cycles */
embeddedartists 0:6b68dac0d986 516 #elif (SDRAM_SPEED==SDRAM_SPEED_60)
embeddedartists 0:6b68dac0d986 517 //Timing for 60 MHz Bus (same as 72MHz)
embeddedartists 0:6b68dac0d986 518 LPC_EMC->DynamicRasCas0 = 0x00000202; /* 2 RAS, 2 CAS latency */
embeddedartists 0:6b68dac0d986 519 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:6b68dac0d986 520 LPC_EMC->DynamicRP = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 521 LPC_EMC->DynamicRAS = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 522 LPC_EMC->DynamicSREX = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:6b68dac0d986 523 LPC_EMC->DynamicAPR = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 524 LPC_EMC->DynamicDAL = 0x00000003; /* ( n ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 525 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 526 LPC_EMC->DynamicRC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:6b68dac0d986 527 LPC_EMC->DynamicRFC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:6b68dac0d986 528 LPC_EMC->DynamicXSR = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:6b68dac0d986 529 LPC_EMC->DynamicRRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 530 LPC_EMC->DynamicMRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 531 #elif (SDRAM_SPEED==SDRAM_SPEED_72)
embeddedartists 0:6b68dac0d986 532 //Timing for 72 MHz Bus
embeddedartists 0:6b68dac0d986 533 LPC_EMC->DynamicRasCas0 = 0x00000202; /* 2 RAS, 2 CAS latency */
embeddedartists 0:6b68dac0d986 534 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:6b68dac0d986 535 LPC_EMC->DynamicRP = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 536 LPC_EMC->DynamicRAS = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 537 LPC_EMC->DynamicSREX = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:6b68dac0d986 538 LPC_EMC->DynamicAPR = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 539 LPC_EMC->DynamicDAL = 0x00000003; /* ( n ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 540 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 541 LPC_EMC->DynamicRC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:6b68dac0d986 542 LPC_EMC->DynamicRFC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:6b68dac0d986 543 LPC_EMC->DynamicXSR = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:6b68dac0d986 544 LPC_EMC->DynamicRRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 545 LPC_EMC->DynamicMRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 546 #elif (SDRAM_SPEED==SDRAM_SPEED_80)
embeddedartists 0:6b68dac0d986 547 //Timing for 80 MHz Bus (same as 72MHz)
embeddedartists 0:6b68dac0d986 548 LPC_EMC->DynamicRasCas0 = 0x00000202; /* 2 RAS, 2 CAS latency */
embeddedartists 0:6b68dac0d986 549 LPC_EMC->DynamicReadConfig = 0x00000001; /* Command delayed strategy, using EMCCLKDELAY */
embeddedartists 0:6b68dac0d986 550 LPC_EMC->DynamicRP = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 551 LPC_EMC->DynamicRAS = 0x00000003; /* ( n + 1 ) -> 4 clock cycles */
embeddedartists 0:6b68dac0d986 552 LPC_EMC->DynamicSREX = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:6b68dac0d986 553 LPC_EMC->DynamicAPR = 0x00000002; /* ( n + 1 ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 554 LPC_EMC->DynamicDAL = 0x00000003; /* ( n ) -> 3 clock cycles */
embeddedartists 0:6b68dac0d986 555 LPC_EMC->DynamicWR = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 556 LPC_EMC->DynamicRC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:6b68dac0d986 557 LPC_EMC->DynamicRFC = 0x00000004; /* ( n + 1 ) -> 5 clock cycles */
embeddedartists 0:6b68dac0d986 558 LPC_EMC->DynamicXSR = 0x00000005; /* ( n + 1 ) -> 6 clock cycles */
embeddedartists 0:6b68dac0d986 559 LPC_EMC->DynamicRRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 560 LPC_EMC->DynamicMRD = 0x00000001; /* ( n + 1 ) -> 2 clock cycles */
embeddedartists 0:6b68dac0d986 561 #else
embeddedartists 0:6b68dac0d986 562 #error UNSUPPORTED SDRAM FREQ
embeddedartists 0:6b68dac0d986 563 #endif
embeddedartists 0:6b68dac0d986 564
embeddedartists 0:6b68dac0d986 565 LPC_EMC->DynamicControl = 0x00000183; /* Issue NOP command */
embeddedartists 0:6b68dac0d986 566 wait(0.2); /* wait 200ms */
embeddedartists 0:6b68dac0d986 567 LPC_EMC->DynamicControl = 0x00000103; /* Issue PALL command */
embeddedartists 0:6b68dac0d986 568 LPC_EMC->DynamicRefresh = 0x00000002; /* ( n * 16 ) -> 32 clock cycles */
embeddedartists 0:6b68dac0d986 569 for(i = 0; i < 0x80; i++); /* wait 128 AHB clock cycles */
embeddedartists 0:6b68dac0d986 570
embeddedartists 0:6b68dac0d986 571
embeddedartists 0:6b68dac0d986 572 #if (SDRAM_SPEED==SDRAM_SPEED_48)
embeddedartists 0:6b68dac0d986 573 //Timing for 48MHz Bus
embeddedartists 0:6b68dac0d986 574 LPC_EMC->DynamicRefresh = 0x0000002E; /* ( n * 16 ) -> 736 clock cycles -> 15.330uS at 48MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:6b68dac0d986 575 #elif (SDRAM_SPEED==SDRAM_SPEED_50)
embeddedartists 0:6b68dac0d986 576 //Timing for 50MHz Bus
embeddedartists 0:6b68dac0d986 577 LPC_EMC->DynamicRefresh = 0x0000003A; /* ( n * 16 ) -> 768 clock cycles -> 15.360uS at 50MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:6b68dac0d986 578 #elif (SDRAM_SPEED==SDRAM_SPEED_60)
embeddedartists 0:6b68dac0d986 579 //Timing for 60MHz Bus
embeddedartists 0:6b68dac0d986 580 LPC_EMC->DynamicRefresh = 0x0000003A; /* ( n * 16 ) -> 928 clock cycles -> 15.466uS at 60MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:6b68dac0d986 581 #elif (SDRAM_SPEED==SDRAM_SPEED_72)
embeddedartists 0:6b68dac0d986 582 //Timing for 72MHz Bus
embeddedartists 0:6b68dac0d986 583 LPC_EMC->DynamicRefresh = 0x00000046; /* ( n * 16 ) -> 1120 clock cycles -> 15.556uS at 72MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:6b68dac0d986 584 #elif (SDRAM_SPEED==SDRAM_SPEED_80)
embeddedartists 0:6b68dac0d986 585 //Timing for 80MHz Bus
embeddedartists 0:6b68dac0d986 586 LPC_EMC->DynamicRefresh = 0x0000004E; /* ( n * 16 ) -> 1248 clock cycles -> 15.600uS at 80MHz <= 15.625uS ( 64ms / 4096 row ) */
embeddedartists 0:6b68dac0d986 587 #else
embeddedartists 0:6b68dac0d986 588 #error UNSUPPORTED SDRAM FREQ
embeddedartists 0:6b68dac0d986 589 #endif
embeddedartists 0:6b68dac0d986 590
embeddedartists 0:6b68dac0d986 591 LPC_EMC->DynamicControl = 0x00000083; /* Issue MODE command */
embeddedartists 0:6b68dac0d986 592 //Timing for 48/60/72MHZ Bus
embeddedartists 0:6b68dac0d986 593 dwtemp = *((volatile uint32_t *)(SDRAM_BASE | (0x22<<(2+2+9)))); /* 4 burst, 2 CAS latency */
embeddedartists 0:6b68dac0d986 594 dwtemp = dwtemp;
embeddedartists 0:6b68dac0d986 595 LPC_EMC->DynamicControl = 0x00000000; /* Issue NORMAL command */
embeddedartists 0:6b68dac0d986 596 //[re]enable buffers
embeddedartists 0:6b68dac0d986 597 LPC_EMC->DynamicConfig0 = 0x00084480; /* 256MB, 8Mx32, 4 banks, row=12, column=9 */
embeddedartists 0:6b68dac0d986 598
embeddedartists 0:6b68dac0d986 599 /* Nominal value */
embeddedartists 0:6b68dac0d986 600 ringosccount[0] = calibration();
embeddedartists 0:6b68dac0d986 601
embeddedartists 0:6b68dac0d986 602 if (find_cmddly() == 0x0)
embeddedartists 0:6b68dac0d986 603 {
embeddedartists 0:6b68dac0d986 604 //while (1); /* fatal error */
embeddedartists 0:6b68dac0d986 605 return 1;//FALSE;
embeddedartists 0:6b68dac0d986 606 }
embeddedartists 0:6b68dac0d986 607
embeddedartists 0:6b68dac0d986 608 if (find_fbclkdly() == 0x0)
embeddedartists 0:6b68dac0d986 609 {
embeddedartists 0:6b68dac0d986 610 //while (1); /* fatal error */
embeddedartists 0:6b68dac0d986 611 return 1;//FALSE;
embeddedartists 0:6b68dac0d986 612 }
embeddedartists 0:6b68dac0d986 613
embeddedartists 0:6b68dac0d986 614 adjust_timing();
embeddedartists 0:6b68dac0d986 615
embeddedartists 10:1ac4b213f0f7 616 allowExecutionOfCodeInSDRAM();
embeddedartists 10:1ac4b213f0f7 617
embeddedartists 0:6b68dac0d986 618 initialized = true;
embeddedartists 0:6b68dac0d986 619
embeddedartists 0:6b68dac0d986 620 return 0;//TRUE;
embeddedartists 0:6b68dac0d986 621 }
embeddedartists 0:6b68dac0d986 622
embeddedartists 0:6b68dac0d986 623 void sdram_disableMallocSdram()
embeddedartists 0:6b68dac0d986 624 {
embeddedartists 0:6b68dac0d986 625 okToUseSdramForHeap = false;
embeddedartists 0:6b68dac0d986 626 }