CC1101-Defines.h

00001 #ifndef CC1101_DEFINES_H
00002 #define CC1101_DEFINES_H
00003 
00004 
00005 /**
00006  * Defines for TI CCXXX1 Radio Transceivers
00007  */
00008 
00009 // REGISTERS
00010 #define CCXXX1_IOCFG2       0x00        // GDO2 output pin configuration
00011 #define CCXXX1_IOCFG1       0x01        // GDO1 output pin configuration
00012 #define CCXXX1_FIFOTHR      0x03        // RX FIFO and TX FIFO thresholds
00013 #define CCXXX1_SYNC1        0x04        // Sync word, high byte
00014 #define CCXXX1_SYNC0        0x05        // Sync word, low byte
00015 #define CCXXX1_IOCFG0       0x02        // GDO0 output pin configuration
00016 #define CCXXX1_FIFOTHR      0x03        // RX FIFO and TX FIFO thresholds
00017 #define CCXXX1_SYNC1        0x04        // Sync word, high byte
00018 #define CCXXX1_SYNC0        0x05        // Sync word, low byte
00019 #define CCXXX1_PCKLEN       0x06        // Packet length
00020 #define CCXXX1_PCKCTRL1     0x07        // Packet automation control
00021 #define CCXXX1_PCKCTRL0     0x08        // Packet automation control
00022 #define CCXXX1_ADDR         0x09        // Device address
00023 #define CCXXX1_CHANNR       0x0A        // Channel number
00024 #define CCXXX1_FSCTRL1      0x0B        // Frequency synthesizer control
00025 #define CCXXX1_FSCTRL0      0x0C        // Frequency synthesizer control
00026 #define CCXXX1_FREQ2        0x0D        // Frequency control word, high byte
00027 #define CCXXX1_FREQ1        0x0E        // Frequency control word, middle byte
00028 #define CCXXX1_FREQ0        0x0F        // Frequency control word, low byte
00029 #define CCXXX1_MDMCFG4      0x10        // Modem configuration
00030 #define CCXXX1_MDMCFG3      0x11        // Modem configuration
00031 #define CCXXX1_MDMCFG2      0x12        // Modem configuration
00032 #define CCXXX1_MDMCFG1      0x13        // Modem configuration
00033 #define CCXXX1_MDMCFG0      0x14        // Modem configuration
00034 #define CCXXX1_DEVIATN      0x15        // Modem deviation setting
00035 #define CCXXX1_MCSM2        0x16        // Main Radio Control State Machine configuration
00036 #define CCXXX1_MCSM1        0x17        // Main Radio Control State Machine configuration
00037 #define CCXXX1_MCSM0        0x18        // Main Radio Control State Machine configuration
00038 #define CCXXX1_FOCCFG       0x19        // Frequency Offset Compensation configuration
00039 #define CCXXX1_BSCFG        0x1A        // Bit Synchronization configuration
00040 #define CCXXX1_AGCCTRL2     0x1B        // AGC control
00041 #define CCXXX1_AGCCTRL1     0x1C        // AGC control
00042 #define CCXXX1_AGCCTRL0     0x1D        // AGC control
00043 #define CCXXX1_WOREVT1      0x1E        // High byte Event 0 timeout
00044 #define CCXXX1_WOREVT0      0x1F        // Low byte Event 0 timeout
00045 #define CCXXX1_WORCTRL      0x20        // Wake On Radio control
00046 #define CCXXX1_FREND1       0x21        // Front end RX configuration
00047 #define CCXXX1_FREND0       0x22        // Front end TX configuration
00048 #define CCXXX1_FSCAL3       0x23        // Frequency synthesizer calibration
00049 #define CCXXX1_FSCAL2       0x24        // Frequency synthesizer calibration
00050 #define CCXXX1_FSCAL1       0x25        // Frequency synthesizer calibration
00051 #define CCXXX1_FSCAL0       0x26        // Frequency synthesizer calibration
00052 #define CCXXX1_RCCTRL1      0x27        // RC oscillator configuration
00053 #define CCXXX1_RCCTRL0      0x28        // RC oscillator configuration
00054 #define CCXXX1_FSTEST       0x29        // Frequency synthesizer calibration control
00055 #define CCXXX1_PTEST        0x2A        // Production test
00056 #define CCXXX1_AGCTEST      0x2B        // AGC test
00057 #define CCXXX1_TEST2        0x2C        // Various test settings
00058 #define CCXXX1_TEST1        0x2D        // Various test settings
00059 #define CCXXX1_TEST0        0x2E        // Various test settings
00060 
00061 // STROBE COMMANDS
00062 #define CCXXX1_SRES         0x30        // Reset chip.
00063 #define CCXXX1_SFSTXON      0x31        // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
00064 #define CCXXX1_SXOFF        0x32        // Turn off crystal oscillator.
00065 #define CCXXX1_SCAL         0x33        // Calibrate frequency synthesizer and turn it off
00066 #define CCXXX1_SRX          0x34        // Enable RX. Perform calibration first if coming from IDLE and
00067 #define CCXXX1_STX          0x35        // In IDLE state: Enable TX. Perform calibration first if
00068 #define CCXXX1_SIDLE        0x36        // Exit RX / TX, turn off frequency synthesizer and exit
00069 #define CCXXX1_SAFC         0x37        // Perform AFC adjustment of the frequency synthesizer
00070 #define CCXXX1_SWOR         0x38        // Start automatic RX polling sequence (Wake-on-Radio)
00071 #define CCXXX1_SPWD         0x39        // Enter power down mode when CSn goes high.
00072 #define CCXXX1_SFRX         0x3A        // Flush the RX FIFO buffer.
00073 #define CCXXX1_SFTX         0x3B        // Flush the TX FIFO buffer.
00074 #define CCXXX1_SWORRST      0x3C        // Reset real time clock.
00075 
00076 // READ ONLY REGISTERS
00077 #define CCXXX1_SNOP             0x3D        // No operation. May be used to pad strobe commands to two bytes for simpler software.
00078 #define CCXXX1_PARTNUM          0x30
00079 #define CCXXX1_VERSION          0x31
00080 #define CCXXX1_FREQEST          0x32
00081 #define CCXXX1_LQI              0x33
00082 #define CCXXX1_RSSI             0x34
00083 #define CCXXX1_MARCSTATE        0x35
00084 #define CCXXX1_WORTIME1         0x36
00085 #define CCXXX1_WORTIME0         0x37
00086 #define CCXXX1_PKTSTATUS        0x38
00087 #define CCXXX1_VCO_VC_DAC       0x39
00088 #define CCXXX1_TXBYTES          0x3A
00089 #define CCXXX1_RXBYTES          0x3B
00090 #define CCXXX1_RCCTRL1_STATUS   0x3C
00091 #define CCXXX1_RCCTRL0_STATUS   0x3D
00092 
00093 // POWER REGISTERS
00094 #define CCXXX1_PATABLE          0x3E
00095 #define CCXXX1_TXFIFO           0x3F
00096 #define CCXXX1_RXFIFO           0x3F
00097 
00098 // BURST/SINGLE MODIFIERS
00099 #define CCXXX1_WRITE_BURST     0x40
00100 #define CCXXX1_READ_SINGLE     0x80
00101 #define CCXXX1_READ_BURST      0xC0
00102 
00103 // GENERAL DEFINES
00104 #define CCXXX1_RXFIFO_MASK     0x7F
00105 
00106 // CHIP STATUS
00107 #define CHIP_RDY                        0x80
00108 #define CHIP_STATE_MASK                 0x70
00109 #define CHIP_STATE_IDLE                 0x00
00110 #define CHIP_STATE_RX                   0x10
00111 #define CHIP_STATE_TX                   0x20
00112 #define CHIP_STATE_FSTON                0x30
00113 #define CHIP_STATE_CALIBRATE            0x40
00114 #define CHIP_STATE_SETTLING             0x50
00115 #define CHIP_STATE_RXFIFO_OVERFLOW      0x60
00116 #define CHIP_STATE_TXFIFO_UNDERFLOW     0x70
00117 #define FIFO_BYTES_MASK                 0x0F
00118 
00119 // FREQUENCY DEFINITIONS
00120 // #define _902MHZ_ 901833462
00121 // #define _316KHZ_ 316406
00122 #define CCXXX1_IF_FREQUENCY     316406  // 316 kHz
00123 #define CCXXX1_BASE_FREQUENCY   901833462
00124 #define CCXXX1_EXPECTED_VERSION_NUMBER  0x04
00125 #define CCXXX1_CRYSTAL_FREQUENCY    27000000    // 27 MHz
00126 
00127 
00128 // RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
00129 typedef struct rf_settings_t {
00130     uint8_t FSCTRL1;   // Frequency synthesizer control.
00131     uint8_t IOCFG0;    // GDO0 output pin configuration
00132     uint8_t FSCTRL0;   // Frequency synthesizer control.
00133     uint8_t FREQ2;     // Frequency control word, high byte.
00134     uint8_t FREQ1;     // Frequency control word, middle byte.
00135     uint8_t FREQ0;     // Frequency control word, low byte.
00136     uint8_t MDMCFG4;   // Modem configuration.
00137     uint8_t MDMCFG3;   // Modem configuration.
00138     uint8_t MDMCFG2;   // Modem configuration.
00139     uint8_t MDMCFG1;   // Modem configuration.
00140     uint8_t MDMCFG0;   // Modem configuration.
00141     uint8_t CHANNR;    // Channel number.
00142     uint8_t DEVIATN;   // Modem deviation setting (when FSK modulation is enabled).
00143     uint8_t FREND1;    // Front end RX configuration.
00144     uint8_t FREND0;    // Front end RX configuration.
00145     uint8_t MCSM0;     // Main Radio Control State Machine configuration.
00146     uint8_t MCSM1;     // Main Radio Control State Machine configuration.
00147     uint8_t MCSM2;     // Main Radio Control State Machine configuration.
00148     uint8_t FOCCFG;    // Frequency Offset Compensation Configuration.
00149     uint8_t BSCFG;     // Bit synchronization Configuration.
00150     uint8_t AGCCTRL2;  // AGC control.
00151     uint8_t AGCCTRL1;  // AGC control.
00152     uint8_t AGCCTRL0;  // AGC control.
00153     uint8_t FSCAL3;    // Frequency synthesizer calibration.
00154     uint8_t FSCAL2;    // Frequency synthesizer calibration.
00155     uint8_t FSCAL1;    // Frequency synthesizer calibration.
00156     uint8_t FSCAL0;    // Frequency synthesizer calibration.
00157     uint8_t FSTEST;    // Frequency synthesizer calibration control
00158     uint8_t TEST2;     // Various test settings.
00159     uint8_t TEST1;     // Various test settings.
00160     uint8_t TEST0;     // Various test settings.
00161     uint8_t FIFOTHR;   // RXFIFO and TXFIFO thresholds.
00162     uint8_t IOCFG2;    // GDO2 output pin configuration
00163     uint8_t IOCFG1;    // GDO1 output pin configuration
00164     uint8_t PCKCTRL1;  // Packet automation control.
00165     uint8_t PCKCTRL0;  // Packet automation control.
00166     uint8_t ADDR;      // Device address.
00167     uint8_t PCKLEN;    // Packet length.
00168 } rf_settings_t;
00169 
00170 /** Enumerations for state types of the CC1101 */
00171 enum radio_state_t {
00172     RADIO_IDLE = 0,
00173     RADIO_RX = 1,
00174     RADIO_TX = 2,
00175     RADIO_FSTXON = 3,
00176     RADIO_CALIBRATE = 4,
00177     RADIO_SETTLING = 5,
00178     RADIO_RXFIFO_OVERFLOW = 6,
00179     RADIO_TXFIFO_OVERFLOW = 7
00180 };
00181 
00182 /** Enumerations for packet format settings of the CC1101 */
00183 enum pck_format_t {
00184     FORMAT_DEFAULT = 0,
00185     FORMAT_SYNC_SERIAL = 1,
00186     FORMAT_RAND_TX = 2,
00187     FORMAT_ASYC_SERIAL = 3
00188 };
00189 
00190 /** Enumerations for packet length types of the CC1101 */
00191 enum pck_length_type_t {
00192     PACKET_FIXED = 0,
00193     PACKET_VARIABLE = 1,
00194     PACKET_INFINITE = 2
00195 };
00196 
00197 /** Enumerations for packet address checking types of the CC1101 */
00198 enum pck_addr_chk_t {
00199     ADDR_OFF = 0,
00200     ADDR_CHK = 1,
00201     ADDR_CHK_AND_BCAST = 2,
00202     ADDR_CHK_AND_BCAST_ALL = 3
00203 };
00204 
00205 /** Data structure for managing how the CC1101 handels packets */
00206 typedef struct pck_ctrl_t {
00207     bool    whitening_en;
00208     bool    crc_en;
00209     bool    autoflush_en;
00210     bool    status_field_en;
00211     uint8_t preamble_thresh;
00212     uint8_t size;
00213     pck_format_t        format_type;
00214     pck_length_type_t   length_type;
00215     pck_addr_chk_t      addr_check;
00216 } pck_ctrl_t;
00217 
00218 /** Enumerations for modulation types of the CC1101 */
00219 enum mod_format_t {
00220     MOD_TWO_FSK = 0,
00221     MOD_GFSK = 1,
00222     MOD_ASK = 3,
00223     MOD_FOUR_FSK = 4,
00224     MOD_MSK = 7
00225 };
00226 
00227 /** Enumerations for signal syncronization of the CC1101 */
00228 enum sync_mode_t {
00229     SYNC_NONE = 0,
00230     SYNC_LOW_ALLOW_ONE = 1,
00231     SYNC_LOW_ALLOW_NONE = 2,
00232     SYNC_HIGH_ALLOW_TWO = 3,
00233     SYNC_JUST_CARRIER_SENSE = 4,
00234     SYNC_LOW_ALLOW_ONE_CS = 5,
00235     SYNC_LOW_ALLOW_NONE_CS = 6,
00236     SYNC_HIGH_ALLOW_TWO_CS = 7
00237 };
00238 
00239 /** Enumerations for preamble byte sizes of the CC1101 */
00240 enum pream_bytes_t {
00241     PREAM_TWO = 0,
00242     PREAM_THREE = 1,
00243     PREAM_FOUR = 2,
00244     PREAM_SIX = 3,
00245     PREAM_EIGHT = 4,
00246     PREAM_TWELVE = 5,
00247     PREAM_SIXTEEN = 6,
00248     PREAM_TWENTY_FOUR = 7
00249 };
00250 
00251 /** Data structure for managing how the CC1101 modulates/demodulates signals */
00252 typedef struct modem_t {
00253     bool    dc_filter_off_en;
00254     bool    manchester_encode_en;
00255     bool    fec_en;
00256     uint8_t data_rate_exp;
00257     uint8_t data_rate_mtsa;
00258     uint8_t channel_bw;
00259     uint8_t channel_bw_exp;
00260     uint8_t channel_space_exp;
00261     uint8_t channel_space_mtsa;
00262     mod_format_t    mod_type;
00263     sync_mode_t     sync_mode;
00264     pream_bytes_t   preamble_bytes;
00265 } modem_t;
00266 
00267 #endif  // CC1101_DEFINES_H