Jonathan Jones / Mbed 2 deprecated Radios

Radio Structures in OOP

Dependencies:   mbed mbed-rtos

drivers/CC1101/CC1101-Defines.h@6:4a3dbfbc30f1, 2015-01-15 (annotated)

Committer:
jjones646
Date:
Thu Jan 15 07:15:33 2015 +0000
Revision:
6:4a3dbfbc30f1
Parent:
3:dc7e9c6bc26c 
socket interface confirmed working.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jjones646 3:dc7e9c6bc26c 1 #ifndef CC1101_DEFINES_H
jjones646 3:dc7e9c6bc26c 2 #define CC1101_DEFINES_H
jjones646 3:dc7e9c6bc26c 3
jjones646 3:dc7e9c6bc26c 4
jjones646 3:dc7e9c6bc26c 5 /**
jjones646 3:dc7e9c6bc26c 6 * Defines for TI CCXXX1 Radio Transceivers
jjones646 3:dc7e9c6bc26c 7 */
jjones646 3:dc7e9c6bc26c 8
jjones646 3:dc7e9c6bc26c 9 // REGISTERS
jjones646 3:dc7e9c6bc26c 10 #define CCXXX1_IOCFG2 0x00 // GDO2 output pin configuration
jjones646 3:dc7e9c6bc26c 11 #define CCXXX1_IOCFG1 0x01 // GDO1 output pin configuration
jjones646 3:dc7e9c6bc26c 12 #define CCXXX1_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
jjones646 3:dc7e9c6bc26c 13 #define CCXXX1_SYNC1 0x04 // Sync word, high byte
jjones646 3:dc7e9c6bc26c 14 #define CCXXX1_SYNC0 0x05 // Sync word, low byte
jjones646 3:dc7e9c6bc26c 15 #define CCXXX1_IOCFG0 0x02 // GDO0 output pin configuration
jjones646 3:dc7e9c6bc26c 16 #define CCXXX1_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds
jjones646 3:dc7e9c6bc26c 17 #define CCXXX1_SYNC1 0x04 // Sync word, high byte
jjones646 3:dc7e9c6bc26c 18 #define CCXXX1_SYNC0 0x05 // Sync word, low byte
jjones646 3:dc7e9c6bc26c 19 #define CCXXX1_PCKLEN 0x06 // Packet length
jjones646 3:dc7e9c6bc26c 20 #define CCXXX1_PCKCTRL1 0x07 // Packet automation control
jjones646 3:dc7e9c6bc26c 21 #define CCXXX1_PCKCTRL0 0x08 // Packet automation control
jjones646 3:dc7e9c6bc26c 22 #define CCXXX1_ADDR 0x09 // Device address
jjones646 3:dc7e9c6bc26c 23 #define CCXXX1_CHANNR 0x0A // Channel number
jjones646 3:dc7e9c6bc26c 24 #define CCXXX1_FSCTRL1 0x0B // Frequency synthesizer control
jjones646 3:dc7e9c6bc26c 25 #define CCXXX1_FSCTRL0 0x0C // Frequency synthesizer control
jjones646 3:dc7e9c6bc26c 26 #define CCXXX1_FREQ2 0x0D // Frequency control word, high byte
jjones646 3:dc7e9c6bc26c 27 #define CCXXX1_FREQ1 0x0E // Frequency control word, middle byte
jjones646 3:dc7e9c6bc26c 28 #define CCXXX1_FREQ0 0x0F // Frequency control word, low byte
jjones646 3:dc7e9c6bc26c 29 #define CCXXX1_MDMCFG4 0x10 // Modem configuration
jjones646 3:dc7e9c6bc26c 30 #define CCXXX1_MDMCFG3 0x11 // Modem configuration
jjones646 3:dc7e9c6bc26c 31 #define CCXXX1_MDMCFG2 0x12 // Modem configuration
jjones646 3:dc7e9c6bc26c 32 #define CCXXX1_MDMCFG1 0x13 // Modem configuration
jjones646 3:dc7e9c6bc26c 33 #define CCXXX1_MDMCFG0 0x14 // Modem configuration
jjones646 3:dc7e9c6bc26c 34 #define CCXXX1_DEVIATN 0x15 // Modem deviation setting
jjones646 3:dc7e9c6bc26c 35 #define CCXXX1_MCSM2 0x16 // Main Radio Control State Machine configuration
jjones646 3:dc7e9c6bc26c 36 #define CCXXX1_MCSM1 0x17 // Main Radio Control State Machine configuration
jjones646 3:dc7e9c6bc26c 37 #define CCXXX1_MCSM0 0x18 // Main Radio Control State Machine configuration
jjones646 3:dc7e9c6bc26c 38 #define CCXXX1_FOCCFG 0x19 // Frequency Offset Compensation configuration
jjones646 3:dc7e9c6bc26c 39 #define CCXXX1_BSCFG 0x1A // Bit Synchronization configuration
jjones646 3:dc7e9c6bc26c 40 #define CCXXX1_AGCCTRL2 0x1B // AGC control
jjones646 3:dc7e9c6bc26c 41 #define CCXXX1_AGCCTRL1 0x1C // AGC control
jjones646 3:dc7e9c6bc26c 42 #define CCXXX1_AGCCTRL0 0x1D // AGC control
jjones646 3:dc7e9c6bc26c 43 #define CCXXX1_WOREVT1 0x1E // High byte Event 0 timeout
jjones646 3:dc7e9c6bc26c 44 #define CCXXX1_WOREVT0 0x1F // Low byte Event 0 timeout
jjones646 3:dc7e9c6bc26c 45 #define CCXXX1_WORCTRL 0x20 // Wake On Radio control
jjones646 3:dc7e9c6bc26c 46 #define CCXXX1_FREND1 0x21 // Front end RX configuration
jjones646 3:dc7e9c6bc26c 47 #define CCXXX1_FREND0 0x22 // Front end TX configuration
jjones646 3:dc7e9c6bc26c 48 #define CCXXX1_FSCAL3 0x23 // Frequency synthesizer calibration
jjones646 3:dc7e9c6bc26c 49 #define CCXXX1_FSCAL2 0x24 // Frequency synthesizer calibration
jjones646 3:dc7e9c6bc26c 50 #define CCXXX1_FSCAL1 0x25 // Frequency synthesizer calibration
jjones646 3:dc7e9c6bc26c 51 #define CCXXX1_FSCAL0 0x26 // Frequency synthesizer calibration
jjones646 3:dc7e9c6bc26c 52 #define CCXXX1_RCCTRL1 0x27 // RC oscillator configuration
jjones646 3:dc7e9c6bc26c 53 #define CCXXX1_RCCTRL0 0x28 // RC oscillator configuration
jjones646 3:dc7e9c6bc26c 54 #define CCXXX1_FSTEST 0x29 // Frequency synthesizer calibration control
jjones646 3:dc7e9c6bc26c 55 #define CCXXX1_PTEST 0x2A // Production test
jjones646 3:dc7e9c6bc26c 56 #define CCXXX1_AGCTEST 0x2B // AGC test
jjones646 3:dc7e9c6bc26c 57 #define CCXXX1_TEST2 0x2C // Various test settings
jjones646 3:dc7e9c6bc26c 58 #define CCXXX1_TEST1 0x2D // Various test settings
jjones646 3:dc7e9c6bc26c 59 #define CCXXX1_TEST0 0x2E // Various test settings
jjones646 3:dc7e9c6bc26c 60
jjones646 3:dc7e9c6bc26c 61 // STROBE COMMANDS
jjones646 3:dc7e9c6bc26c 62 #define CCXXX1_SRES 0x30 // Reset chip.
jjones646 3:dc7e9c6bc26c 63 #define CCXXX1_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
jjones646 3:dc7e9c6bc26c 64 #define CCXXX1_SXOFF 0x32 // Turn off crystal oscillator.
jjones646 3:dc7e9c6bc26c 65 #define CCXXX1_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
jjones646 3:dc7e9c6bc26c 66 #define CCXXX1_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
jjones646 3:dc7e9c6bc26c 67 #define CCXXX1_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
jjones646 3:dc7e9c6bc26c 68 #define CCXXX1_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
jjones646 3:dc7e9c6bc26c 69 #define CCXXX1_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
jjones646 3:dc7e9c6bc26c 70 #define CCXXX1_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
jjones646 3:dc7e9c6bc26c 71 #define CCXXX1_SPWD 0x39 // Enter power down mode when CSn goes high.
jjones646 3:dc7e9c6bc26c 72 #define CCXXX1_SFRX 0x3A // Flush the RX FIFO buffer.
jjones646 3:dc7e9c6bc26c 73 #define CCXXX1_SFTX 0x3B // Flush the TX FIFO buffer.
jjones646 3:dc7e9c6bc26c 74 #define CCXXX1_SWORRST 0x3C // Reset real time clock.
jjones646 3:dc7e9c6bc26c 75
jjones646 3:dc7e9c6bc26c 76 // READ ONLY REGISTERS
jjones646 3:dc7e9c6bc26c 77 #define CCXXX1_SNOP 0x3D // No operation. May be used to pad strobe commands to two bytes for simpler software.
jjones646 3:dc7e9c6bc26c 78 #define CCXXX1_PARTNUM 0x30
jjones646 3:dc7e9c6bc26c 79 #define CCXXX1_VERSION 0x31
jjones646 3:dc7e9c6bc26c 80 #define CCXXX1_FREQEST 0x32
jjones646 3:dc7e9c6bc26c 81 #define CCXXX1_LQI 0x33
jjones646 3:dc7e9c6bc26c 82 #define CCXXX1_RSSI 0x34
jjones646 3:dc7e9c6bc26c 83 #define CCXXX1_MARCSTATE 0x35
jjones646 3:dc7e9c6bc26c 84 #define CCXXX1_WORTIME1 0x36
jjones646 3:dc7e9c6bc26c 85 #define CCXXX1_WORTIME0 0x37
jjones646 3:dc7e9c6bc26c 86 #define CCXXX1_PKTSTATUS 0x38
jjones646 3:dc7e9c6bc26c 87 #define CCXXX1_VCO_VC_DAC 0x39
jjones646 3:dc7e9c6bc26c 88 #define CCXXX1_TXBYTES 0x3A
jjones646 3:dc7e9c6bc26c 89 #define CCXXX1_RXBYTES 0x3B
jjones646 3:dc7e9c6bc26c 90 #define CCXXX1_RCCTRL1_STATUS 0x3C
jjones646 3:dc7e9c6bc26c 91 #define CCXXX1_RCCTRL0_STATUS 0x3D
jjones646 3:dc7e9c6bc26c 92
jjones646 3:dc7e9c6bc26c 93 // POWER REGISTERS
jjones646 3:dc7e9c6bc26c 94 #define CCXXX1_PATABLE 0x3E
jjones646 3:dc7e9c6bc26c 95 #define CCXXX1_TXFIFO 0x3F
jjones646 3:dc7e9c6bc26c 96 #define CCXXX1_RXFIFO 0x3F
jjones646 3:dc7e9c6bc26c 97
jjones646 3:dc7e9c6bc26c 98 // BURST/SINGLE MODIFIERS
jjones646 3:dc7e9c6bc26c 99 #define CCXXX1_WRITE_BURST 0x40
jjones646 3:dc7e9c6bc26c 100 #define CCXXX1_READ_SINGLE 0x80
jjones646 3:dc7e9c6bc26c 101 #define CCXXX1_READ_BURST 0xC0
jjones646 3:dc7e9c6bc26c 102
jjones646 3:dc7e9c6bc26c 103 // GENERAL DEFINES
jjones646 3:dc7e9c6bc26c 104 #define CCXXX1_RXFIFO_MASK 0x7F
jjones646 3:dc7e9c6bc26c 105
jjones646 3:dc7e9c6bc26c 106 // CHIP STATUS
jjones646 3:dc7e9c6bc26c 107 #define CHIP_RDY 0x80
jjones646 3:dc7e9c6bc26c 108 #define CHIP_STATE_MASK 0x70
jjones646 3:dc7e9c6bc26c 109 #define CHIP_STATE_IDLE 0x00
jjones646 3:dc7e9c6bc26c 110 #define CHIP_STATE_RX 0x10
jjones646 3:dc7e9c6bc26c 111 #define CHIP_STATE_TX 0x20
jjones646 3:dc7e9c6bc26c 112 #define CHIP_STATE_FSTON 0x30
jjones646 3:dc7e9c6bc26c 113 #define CHIP_STATE_CALIBRATE 0x40
jjones646 3:dc7e9c6bc26c 114 #define CHIP_STATE_SETTLING 0x50
jjones646 3:dc7e9c6bc26c 115 #define CHIP_STATE_RXFIFO_OVERFLOW 0x60
jjones646 3:dc7e9c6bc26c 116 #define CHIP_STATE_TXFIFO_UNDERFLOW 0x70
jjones646 3:dc7e9c6bc26c 117 #define FIFO_BYTES_MASK 0x0F
jjones646 3:dc7e9c6bc26c 118
jjones646 3:dc7e9c6bc26c 119 // FREQUENCY DEFINITIONS
jjones646 3:dc7e9c6bc26c 120 // #define _902MHZ_ 901833462
jjones646 3:dc7e9c6bc26c 121 // #define _316KHZ_ 316406
jjones646 3:dc7e9c6bc26c 122 #define CCXXX1_IF_FREQUENCY 316406 // 316 kHz
jjones646 3:dc7e9c6bc26c 123 #define CCXXX1_BASE_FREQUENCY 901833462
jjones646 3:dc7e9c6bc26c 124 #define CCXXX1_EXPECTED_VERSION_NUMBER 0x04
jjones646 3:dc7e9c6bc26c 125 #define CCXXX1_CRYSTAL_FREQUENCY 27000000 // 27 MHz
jjones646 3:dc7e9c6bc26c 126
jjones646 3:dc7e9c6bc26c 127
jjones646 3:dc7e9c6bc26c 128 // RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers
jjones646 3:dc7e9c6bc26c 129 typedef struct rf_settings_t {
jjones646 3:dc7e9c6bc26c 130 uint8_t FSCTRL1; // Frequency synthesizer control.
jjones646 3:dc7e9c6bc26c 131 uint8_t IOCFG0; // GDO0 output pin configuration
jjones646 3:dc7e9c6bc26c 132 uint8_t FSCTRL0; // Frequency synthesizer control.
jjones646 3:dc7e9c6bc26c 133 uint8_t FREQ2; // Frequency control word, high byte.
jjones646 3:dc7e9c6bc26c 134 uint8_t FREQ1; // Frequency control word, middle byte.
jjones646 3:dc7e9c6bc26c 135 uint8_t FREQ0; // Frequency control word, low byte.
jjones646 3:dc7e9c6bc26c 136 uint8_t MDMCFG4; // Modem configuration.
jjones646 3:dc7e9c6bc26c 137 uint8_t MDMCFG3; // Modem configuration.
jjones646 3:dc7e9c6bc26c 138 uint8_t MDMCFG2; // Modem configuration.
jjones646 3:dc7e9c6bc26c 139 uint8_t MDMCFG1; // Modem configuration.
jjones646 3:dc7e9c6bc26c 140 uint8_t MDMCFG0; // Modem configuration.
jjones646 3:dc7e9c6bc26c 141 uint8_t CHANNR; // Channel number.
jjones646 3:dc7e9c6bc26c 142 uint8_t DEVIATN; // Modem deviation setting (when FSK modulation is enabled).
jjones646 3:dc7e9c6bc26c 143 uint8_t FREND1; // Front end RX configuration.
jjones646 3:dc7e9c6bc26c 144 uint8_t FREND0; // Front end RX configuration.
jjones646 3:dc7e9c6bc26c 145 uint8_t MCSM0; // Main Radio Control State Machine configuration.
jjones646 3:dc7e9c6bc26c 146 uint8_t MCSM1; // Main Radio Control State Machine configuration.
jjones646 3:dc7e9c6bc26c 147 uint8_t MCSM2; // Main Radio Control State Machine configuration.
jjones646 3:dc7e9c6bc26c 148 uint8_t FOCCFG; // Frequency Offset Compensation Configuration.
jjones646 3:dc7e9c6bc26c 149 uint8_t BSCFG; // Bit synchronization Configuration.
jjones646 3:dc7e9c6bc26c 150 uint8_t AGCCTRL2; // AGC control.
jjones646 3:dc7e9c6bc26c 151 uint8_t AGCCTRL1; // AGC control.
jjones646 3:dc7e9c6bc26c 152 uint8_t AGCCTRL0; // AGC control.
jjones646 3:dc7e9c6bc26c 153 uint8_t FSCAL3; // Frequency synthesizer calibration.
jjones646 3:dc7e9c6bc26c 154 uint8_t FSCAL2; // Frequency synthesizer calibration.
jjones646 3:dc7e9c6bc26c 155 uint8_t FSCAL1; // Frequency synthesizer calibration.
jjones646 3:dc7e9c6bc26c 156 uint8_t FSCAL0; // Frequency synthesizer calibration.
jjones646 3:dc7e9c6bc26c 157 uint8_t FSTEST; // Frequency synthesizer calibration control
jjones646 3:dc7e9c6bc26c 158 uint8_t TEST2; // Various test settings.
jjones646 3:dc7e9c6bc26c 159 uint8_t TEST1; // Various test settings.
jjones646 3:dc7e9c6bc26c 160 uint8_t TEST0; // Various test settings.
jjones646 3:dc7e9c6bc26c 161 uint8_t FIFOTHR; // RXFIFO and TXFIFO thresholds.
jjones646 3:dc7e9c6bc26c 162 uint8_t IOCFG2; // GDO2 output pin configuration
jjones646 3:dc7e9c6bc26c 163 uint8_t IOCFG1; // GDO1 output pin configuration
jjones646 3:dc7e9c6bc26c 164 uint8_t PCKCTRL1; // Packet automation control.
jjones646 3:dc7e9c6bc26c 165 uint8_t PCKCTRL0; // Packet automation control.
jjones646 3:dc7e9c6bc26c 166 uint8_t ADDR; // Device address.
jjones646 3:dc7e9c6bc26c 167 uint8_t PCKLEN; // Packet length.
jjones646 3:dc7e9c6bc26c 168 } rf_settings_t;
jjones646 3:dc7e9c6bc26c 169
jjones646 3:dc7e9c6bc26c 170 /** Enumerations for state types of the CC1101 */
jjones646 3:dc7e9c6bc26c 171 enum radio_state_t {
jjones646 3:dc7e9c6bc26c 172 RADIO_IDLE = 0,
jjones646 3:dc7e9c6bc26c 173 RADIO_RX = 1,
jjones646 3:dc7e9c6bc26c 174 RADIO_TX = 2,
jjones646 3:dc7e9c6bc26c 175 RADIO_FSTXON = 3,
jjones646 3:dc7e9c6bc26c 176 RADIO_CALIBRATE = 4,
jjones646 3:dc7e9c6bc26c 177 RADIO_SETTLING = 5,
jjones646 3:dc7e9c6bc26c 178 RADIO_RXFIFO_OVERFLOW = 6,
jjones646 3:dc7e9c6bc26c 179 RADIO_TXFIFO_OVERFLOW = 7
jjones646 3:dc7e9c6bc26c 180 };
jjones646 3:dc7e9c6bc26c 181
jjones646 3:dc7e9c6bc26c 182 /** Enumerations for packet format settings of the CC1101 */
jjones646 3:dc7e9c6bc26c 183 enum pck_format_t {
jjones646 3:dc7e9c6bc26c 184 FORMAT_DEFAULT = 0,
jjones646 3:dc7e9c6bc26c 185 FORMAT_SYNC_SERIAL = 1,
jjones646 3:dc7e9c6bc26c 186 FORMAT_RAND_TX = 2,
jjones646 3:dc7e9c6bc26c 187 FORMAT_ASYC_SERIAL = 3
jjones646 3:dc7e9c6bc26c 188 };
jjones646 3:dc7e9c6bc26c 189
jjones646 3:dc7e9c6bc26c 190 /** Enumerations for packet length types of the CC1101 */
jjones646 3:dc7e9c6bc26c 191 enum pck_length_type_t {
jjones646 3:dc7e9c6bc26c 192 PACKET_FIXED = 0,
jjones646 3:dc7e9c6bc26c 193 PACKET_VARIABLE = 1,
jjones646 3:dc7e9c6bc26c 194 PACKET_INFINITE = 2
jjones646 3:dc7e9c6bc26c 195 };
jjones646 3:dc7e9c6bc26c 196
jjones646 3:dc7e9c6bc26c 197 /** Enumerations for packet address checking types of the CC1101 */
jjones646 3:dc7e9c6bc26c 198 enum pck_addr_chk_t {
jjones646 3:dc7e9c6bc26c 199 ADDR_OFF = 0,
jjones646 3:dc7e9c6bc26c 200 ADDR_CHK = 1,
jjones646 3:dc7e9c6bc26c 201 ADDR_CHK_AND_BCAST = 2,
jjones646 3:dc7e9c6bc26c 202 ADDR_CHK_AND_BCAST_ALL = 3
jjones646 3:dc7e9c6bc26c 203 };
jjones646 3:dc7e9c6bc26c 204
jjones646 3:dc7e9c6bc26c 205 /** Data structure for managing how the CC1101 handels packets */
jjones646 3:dc7e9c6bc26c 206 typedef struct pck_ctrl_t {
jjones646 3:dc7e9c6bc26c 207 bool whitening_en;
jjones646 3:dc7e9c6bc26c 208 bool crc_en;
jjones646 3:dc7e9c6bc26c 209 bool autoflush_en;
jjones646 3:dc7e9c6bc26c 210 bool status_field_en;
jjones646 3:dc7e9c6bc26c 211 uint8_t preamble_thresh;
jjones646 3:dc7e9c6bc26c 212 uint8_t size;
jjones646 3:dc7e9c6bc26c 213 pck_format_t format_type;
jjones646 3:dc7e9c6bc26c 214 pck_length_type_t length_type;
jjones646 3:dc7e9c6bc26c 215 pck_addr_chk_t addr_check;
jjones646 3:dc7e9c6bc26c 216 } pck_ctrl_t;
jjones646 3:dc7e9c6bc26c 217
jjones646 3:dc7e9c6bc26c 218 /** Enumerations for modulation types of the CC1101 */
jjones646 3:dc7e9c6bc26c 219 enum mod_format_t {
jjones646 3:dc7e9c6bc26c 220 MOD_TWO_FSK = 0,
jjones646 3:dc7e9c6bc26c 221 MOD_GFSK = 1,
jjones646 3:dc7e9c6bc26c 222 MOD_ASK = 3,
jjones646 3:dc7e9c6bc26c 223 MOD_FOUR_FSK = 4,
jjones646 3:dc7e9c6bc26c 224 MOD_MSK = 7
jjones646 3:dc7e9c6bc26c 225 };
jjones646 3:dc7e9c6bc26c 226
jjones646 3:dc7e9c6bc26c 227 /** Enumerations for signal syncronization of the CC1101 */
jjones646 3:dc7e9c6bc26c 228 enum sync_mode_t {
jjones646 3:dc7e9c6bc26c 229 SYNC_NONE = 0,
jjones646 3:dc7e9c6bc26c 230 SYNC_LOW_ALLOW_ONE = 1,
jjones646 3:dc7e9c6bc26c 231 SYNC_LOW_ALLOW_NONE = 2,
jjones646 3:dc7e9c6bc26c 232 SYNC_HIGH_ALLOW_TWO = 3,
jjones646 3:dc7e9c6bc26c 233 SYNC_JUST_CARRIER_SENSE = 4,
jjones646 3:dc7e9c6bc26c 234 SYNC_LOW_ALLOW_ONE_CS = 5,
jjones646 3:dc7e9c6bc26c 235 SYNC_LOW_ALLOW_NONE_CS = 6,
jjones646 3:dc7e9c6bc26c 236 SYNC_HIGH_ALLOW_TWO_CS = 7
jjones646 3:dc7e9c6bc26c 237 };
jjones646 3:dc7e9c6bc26c 238
jjones646 3:dc7e9c6bc26c 239 /** Enumerations for preamble byte sizes of the CC1101 */
jjones646 3:dc7e9c6bc26c 240 enum pream_bytes_t {
jjones646 3:dc7e9c6bc26c 241 PREAM_TWO = 0,
jjones646 3:dc7e9c6bc26c 242 PREAM_THREE = 1,
jjones646 3:dc7e9c6bc26c 243 PREAM_FOUR = 2,
jjones646 3:dc7e9c6bc26c 244 PREAM_SIX = 3,
jjones646 3:dc7e9c6bc26c 245 PREAM_EIGHT = 4,
jjones646 3:dc7e9c6bc26c 246 PREAM_TWELVE = 5,
jjones646 3:dc7e9c6bc26c 247 PREAM_SIXTEEN = 6,
jjones646 3:dc7e9c6bc26c 248 PREAM_TWENTY_FOUR = 7
jjones646 3:dc7e9c6bc26c 249 };
jjones646 3:dc7e9c6bc26c 250
jjones646 3:dc7e9c6bc26c 251 /** Data structure for managing how the CC1101 modulates/demodulates signals */
jjones646 3:dc7e9c6bc26c 252 typedef struct modem_t {
jjones646 3:dc7e9c6bc26c 253 bool dc_filter_off_en;
jjones646 3:dc7e9c6bc26c 254 bool manchester_encode_en;
jjones646 3:dc7e9c6bc26c 255 bool fec_en;
jjones646 3:dc7e9c6bc26c 256 uint8_t data_rate_exp;
jjones646 3:dc7e9c6bc26c 257 uint8_t data_rate_mtsa;
jjones646 3:dc7e9c6bc26c 258 uint8_t channel_bw;
jjones646 3:dc7e9c6bc26c 259 uint8_t channel_bw_exp;
jjones646 3:dc7e9c6bc26c 260 uint8_t channel_space_exp;
jjones646 3:dc7e9c6bc26c 261 uint8_t channel_space_mtsa;
jjones646 3:dc7e9c6bc26c 262 mod_format_t mod_type;
jjones646 3:dc7e9c6bc26c 263 sync_mode_t sync_mode;
jjones646 3:dc7e9c6bc26c 264 pream_bytes_t preamble_bytes;
jjones646 3:dc7e9c6bc26c 265 } modem_t;
jjones646 3:dc7e9c6bc26c 266
jjones646 3:dc7e9c6bc26c 267 #endif // CC1101_DEFINES_H