jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

Files at this revision

API Documentation at this revision

Revision 27:fe3dddcd448c, committed 2020-07-25

Comitter:
jimherd
Date:
Sat Jul 25 23:14:10 2020 +0000
Parent:
26:1837bc6df8ef
Commit message:
Made 'hard_check_bus' routine public.

Changed in this revision

FPGA_bus.cpp Show annotated file Show diff for this revision Revisions of this file
FPGA_bus.h Show annotated file Show diff for this revision Revisions of this file 
--- a/FPGA_bus.cpp	Tue Jul 07 11:03:34 2020 +0000
+++ b/FPGA_bus.cpp	Sat Jul 25 23:14:10 2020 +0000
@@ -50,9 +50,9 @@
 void FPGA_bus:: do_reset(void)
 {
     async_uP_reset = LOW;       // generate low reset pulse
-    wait_us(20);
+    wait_us(FPGA_RESET_PULSE_WIDTH);
     async_uP_reset = HIGH;
-    wait_us(20);
+    wait_us(FPGA_RESET_PULSE_WIDTH);
 }
  
 //////////////////////////////////////////////////////////////////////////

--- a/FPGA_bus.h	Tue Jul 07 11:03:34 2020 +0000
+++ b/FPGA_bus.h	Sat Jul 25 23:14:10 2020 +0000
@@ -74,10 +74,11 @@
 //////////////////////////////////////////////////////////////////////////
 // FPGA constants
 
-#define     nS_IN_uS                1000
-#define     FPGA_CLOCK_PERIOD_nS      20
+#define     nS_IN_uS                          1000
+#define     FPGA_CLOCK_PERIOD_nS                20
 #define     uS_DELAY_BEFORE_TEST_HANDSHAKE      25
-#define     HANDSHAKE_TIMEOUT_COUNT      10000
+#define     HANDSHAKE_TIMEOUT_COUNT          10000
+#define     FPGA_RESET_PULSE_WIDTH              20    // microseconds
 
 //////////////////////////////////////////////////////////////////////////
 // error codes
@@ -187,6 +188,7 @@
      uint32_t read_count_measure(uint32_t channel);
      uint32_t get_SYS_data(void);
      int32_t  soft_check_bus(void);
+     int32_t  hard_check_bus(void);
 //
 // data
 //   
@@ -227,7 +229,6 @@
                         uint32_t register_data);
     void     do_read(received_packet_t   *buffer);
     void     do_reset(void);
-    int32_t  hard_check_bus(void);
     void     update_FPGA_register_pointers(void);
 //
 // Hardware digital I/O lines