jim herd / FPGA_bus

Comms between MAX 10 FPGA and ST uP

Diff: FPGA_bus.cpp

Revision:
27:fe3dddcd448c
Parent:
25:9cdeb5267a47
--- a/FPGA_bus.cpp	Tue Jul 07 11:03:34 2020 +0000
+++ b/FPGA_bus.cpp	Sat Jul 25 23:14:10 2020 +0000
@@ -50,9 +50,9 @@
 void FPGA_bus:: do_reset(void)
 {
     async_uP_reset = LOW;       // generate low reset pulse
-    wait_us(20);
+    wait_us(FPGA_RESET_PULSE_WIDTH);
     async_uP_reset = HIGH;
-    wait_us(20);
+    wait_us(FPGA_RESET_PULSE_WIDTH);
 }
  
 //////////////////////////////////////////////////////////////////////////