Comms between MAX 10 FPGA and ST uP
Diff: FPGA_bus.h
- Revision:
- 2:fd5c862b86db
- Parent:
- 1:b819a72b3b5d
- Child:
- 4:e5d36eee9245
diff -r b819a72b3b5d -r fd5c862b86db FPGA_bus.h --- a/FPGA_bus.h Wed Apr 17 14:32:22 2019 +0000 +++ b/FPGA_bus.h Wed Apr 17 15:58:52 2019 +0000 @@ -32,6 +32,7 @@ #define RC_BASE ((NOS_QE_REGISTERS * NOS_QE_CHANNELS) + QE_BASE) #define NOS_RC_CHANNELS 8 +#define GLOBAL_RC_ENABLE 0x80000000 #define PWM_ch0 (PWM_BASE + (0 * NOS_PWM_REGISTERS)) #define PWM_ch1 (PWM_BASE + (1 * NOS_PWM_REGISTERS)) @@ -112,6 +113,7 @@ void set_RC_duty(uint32_t duty_uS); void set_RC_pulse(uint32_t channel, uint32_t pulse_uS); void enable_RC_channel(uint32_t channel); + void disable_RC_channel(uint32_t channel); int32_t global_FPGA_unit_error_flag;