Diff: FPGA_bus.h

Revision:

17:928b755cba80

Parent:

16:d69a36a541c5

Child:

18:62462a30d513

--- a/FPGA_bus.h	Sat May 23 11:58:57 2020 +0000
+++ b/FPGA_bus.h	Sat May 23 23:28:13 2020 +0000
@@ -6,6 +6,8 @@
  * Version 0.1 : initial release
  */
 #include "mbed.h"
+
+extern Serial pc;
  
 #ifndef  FPGA_bus_H
 #define  FPGA_bus_H
@@ -133,7 +135,7 @@
 enum {PWM_OFF=0x0, PWM_ON=0x1};
 enum {INT_H_BRIDGE_OFF=0x0, INT_H_BRIDGE_ON=0x10000};
 enum {EXT_H_BRIDGE_OFF=0x0, EXT_H_BRIDGE_ON=0x20000};
-enum {MOTOR_COAST=0x0, MOTOR_FORWARD=0x40000, MOTOR_BACKWARD=0x80000, MOTOR_BRAKE=0xC0000};
+enum {MOTOR_COAST=0x0, MOTOR_FORWARD=0x400000, MOTOR_BACKWARD=0x800000, MOTOR_BRAKE=0xC00000};
 enum {MODE_PWM_CONTROL=0x0, MODE_DIR_CONTROL=0x200000};
 enum {NO_SWAP=0x0, YES_SWAP=0x800000};
 enum {PWM_BRAKE_DWELL=0x0, PWM_COAST_DWELL=0x1000000};
@@ -214,9 +216,8 @@
         uint8_t number_of_PWM_channels;
         uint8_t number_of_QE_channels;
         uint8_t number_of_RC_channels;
-        uint8_t PWM_period_value[NOS_PWM_CHANNELS];
-        uint8_t PWM_duty_value[NOS_PWM_CHANNELS];
-        uint8_t pad1;
+        uint32_t PWM_period_value[NOS_PWM_CHANNELS];
+        uint32_t PWM_duty_value[NOS_PWM_CHANNELS];
     } sys_data;
 };