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TARGET_NUCLEO_F072RB/core_cm0.h@0:666850d06c9f, 2015-08-20 (annotated)

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jhon309
Date:
Thu Aug 20 00:37:14 2015 +0000
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0:666850d06c9f
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jhon309 0:666850d06c9f 1 /**************************************************************************//**
jhon309 0:666850d06c9f 2 * @file core_cm0.h
jhon309 0:666850d06c9f 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
jhon309 0:666850d06c9f 4 * @version V3.20
jhon309 0:666850d06c9f 5 * @date 25. February 2013
jhon309 0:666850d06c9f 6 *
jhon309 0:666850d06c9f 7 * @note
jhon309 0:666850d06c9f 8 *
jhon309 0:666850d06c9f 9 ******************************************************************************/
jhon309 0:666850d06c9f 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
jhon309 0:666850d06c9f 11
jhon309 0:666850d06c9f 12 All rights reserved.
jhon309 0:666850d06c9f 13 Redistribution and use in source and binary forms, with or without
jhon309 0:666850d06c9f 14 modification, are permitted provided that the following conditions are met:
jhon309 0:666850d06c9f 15 - Redistributions of source code must retain the above copyright
jhon309 0:666850d06c9f 16 notice, this list of conditions and the following disclaimer.
jhon309 0:666850d06c9f 17 - Redistributions in binary form must reproduce the above copyright
jhon309 0:666850d06c9f 18 notice, this list of conditions and the following disclaimer in the
jhon309 0:666850d06c9f 19 documentation and/or other materials provided with the distribution.
jhon309 0:666850d06c9f 20 - Neither the name of ARM nor the names of its contributors may be used
jhon309 0:666850d06c9f 21 to endorse or promote products derived from this software without
jhon309 0:666850d06c9f 22 specific prior written permission.
jhon309 0:666850d06c9f 23 *
jhon309 0:666850d06c9f 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
jhon309 0:666850d06c9f 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
jhon309 0:666850d06c9f 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
jhon309 0:666850d06c9f 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
jhon309 0:666850d06c9f 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
jhon309 0:666850d06c9f 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
jhon309 0:666850d06c9f 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
jhon309 0:666850d06c9f 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
jhon309 0:666850d06c9f 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
jhon309 0:666850d06c9f 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
jhon309 0:666850d06c9f 34 POSSIBILITY OF SUCH DAMAGE.
jhon309 0:666850d06c9f 35 ---------------------------------------------------------------------------*/
jhon309 0:666850d06c9f 36
jhon309 0:666850d06c9f 37
jhon309 0:666850d06c9f 38 #if defined ( __ICCARM__ )
jhon309 0:666850d06c9f 39 #pragma system_include /* treat file as system include file for MISRA check */
jhon309 0:666850d06c9f 40 #endif
jhon309 0:666850d06c9f 41
jhon309 0:666850d06c9f 42 #ifdef __cplusplus
jhon309 0:666850d06c9f 43 extern "C" {
jhon309 0:666850d06c9f 44 #endif
jhon309 0:666850d06c9f 45
jhon309 0:666850d06c9f 46 #ifndef __CORE_CM0_H_GENERIC
jhon309 0:666850d06c9f 47 #define __CORE_CM0_H_GENERIC
jhon309 0:666850d06c9f 48
jhon309 0:666850d06c9f 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
jhon309 0:666850d06c9f 50 CMSIS violates the following MISRA-C:2004 rules:
jhon309 0:666850d06c9f 51
jhon309 0:666850d06c9f 52 \li Required Rule 8.5, object/function definition in header file.<br>
jhon309 0:666850d06c9f 53 Function definitions in header files are used to allow 'inlining'.
jhon309 0:666850d06c9f 54
jhon309 0:666850d06c9f 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
jhon309 0:666850d06c9f 56 Unions are used for effective representation of core registers.
jhon309 0:666850d06c9f 57
jhon309 0:666850d06c9f 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
jhon309 0:666850d06c9f 59 Function-like macros are used to allow more efficient code.
jhon309 0:666850d06c9f 60 */
jhon309 0:666850d06c9f 61
jhon309 0:666850d06c9f 62
jhon309 0:666850d06c9f 63 /*******************************************************************************
jhon309 0:666850d06c9f 64 * CMSIS definitions
jhon309 0:666850d06c9f 65 ******************************************************************************/
jhon309 0:666850d06c9f 66 /** \ingroup Cortex_M0
jhon309 0:666850d06c9f 67 @{
jhon309 0:666850d06c9f 68 */
jhon309 0:666850d06c9f 69
jhon309 0:666850d06c9f 70 /* CMSIS CM0 definitions */
jhon309 0:666850d06c9f 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
jhon309 0:666850d06c9f 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
jhon309 0:666850d06c9f 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
jhon309 0:666850d06c9f 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
jhon309 0:666850d06c9f 75
jhon309 0:666850d06c9f 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
jhon309 0:666850d06c9f 77
jhon309 0:666850d06c9f 78
jhon309 0:666850d06c9f 79 #if defined ( __CC_ARM )
jhon309 0:666850d06c9f 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
jhon309 0:666850d06c9f 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
jhon309 0:666850d06c9f 82 #define __STATIC_INLINE static __inline
jhon309 0:666850d06c9f 83
jhon309 0:666850d06c9f 84 #elif defined ( __ICCARM__ )
jhon309 0:666850d06c9f 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
jhon309 0:666850d06c9f 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
jhon309 0:666850d06c9f 87 #define __STATIC_INLINE static inline
jhon309 0:666850d06c9f 88
jhon309 0:666850d06c9f 89 #elif defined ( __GNUC__ )
jhon309 0:666850d06c9f 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
jhon309 0:666850d06c9f 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
jhon309 0:666850d06c9f 92 #define __STATIC_INLINE static inline
jhon309 0:666850d06c9f 93
jhon309 0:666850d06c9f 94 #elif defined ( __TASKING__ )
jhon309 0:666850d06c9f 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
jhon309 0:666850d06c9f 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
jhon309 0:666850d06c9f 97 #define __STATIC_INLINE static inline
jhon309 0:666850d06c9f 98
jhon309 0:666850d06c9f 99 #endif
jhon309 0:666850d06c9f 100
jhon309 0:666850d06c9f 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
jhon309 0:666850d06c9f 102 */
jhon309 0:666850d06c9f 103 #define __FPU_USED 0
jhon309 0:666850d06c9f 104
jhon309 0:666850d06c9f 105 #if defined ( __CC_ARM )
jhon309 0:666850d06c9f 106 #if defined __TARGET_FPU_VFP
jhon309 0:666850d06c9f 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:666850d06c9f 108 #endif
jhon309 0:666850d06c9f 109
jhon309 0:666850d06c9f 110 #elif defined ( __ICCARM__ )
jhon309 0:666850d06c9f 111 #if defined __ARMVFP__
jhon309 0:666850d06c9f 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:666850d06c9f 113 #endif
jhon309 0:666850d06c9f 114
jhon309 0:666850d06c9f 115 #elif defined ( __GNUC__ )
jhon309 0:666850d06c9f 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
jhon309 0:666850d06c9f 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:666850d06c9f 118 #endif
jhon309 0:666850d06c9f 119
jhon309 0:666850d06c9f 120 #elif defined ( __TASKING__ )
jhon309 0:666850d06c9f 121 #if defined __FPU_VFP__
jhon309 0:666850d06c9f 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
jhon309 0:666850d06c9f 123 #endif
jhon309 0:666850d06c9f 124 #endif
jhon309 0:666850d06c9f 125
jhon309 0:666850d06c9f 126 #include <stdint.h> /* standard types definitions */
jhon309 0:666850d06c9f 127 #include <core_cmInstr.h> /* Core Instruction Access */
jhon309 0:666850d06c9f 128 #include <core_cmFunc.h> /* Core Function Access */
jhon309 0:666850d06c9f 129
jhon309 0:666850d06c9f 130 #endif /* __CORE_CM0_H_GENERIC */
jhon309 0:666850d06c9f 131
jhon309 0:666850d06c9f 132 #ifndef __CMSIS_GENERIC
jhon309 0:666850d06c9f 133
jhon309 0:666850d06c9f 134 #ifndef __CORE_CM0_H_DEPENDANT
jhon309 0:666850d06c9f 135 #define __CORE_CM0_H_DEPENDANT
jhon309 0:666850d06c9f 136
jhon309 0:666850d06c9f 137 /* check device defines and use defaults */
jhon309 0:666850d06c9f 138 #if defined __CHECK_DEVICE_DEFINES
jhon309 0:666850d06c9f 139 #ifndef __CM0_REV
jhon309 0:666850d06c9f 140 #define __CM0_REV 0x0000
jhon309 0:666850d06c9f 141 #warning "__CM0_REV not defined in device header file; using default!"
jhon309 0:666850d06c9f 142 #endif
jhon309 0:666850d06c9f 143
jhon309 0:666850d06c9f 144 #ifndef __NVIC_PRIO_BITS
jhon309 0:666850d06c9f 145 #define __NVIC_PRIO_BITS 2
jhon309 0:666850d06c9f 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
jhon309 0:666850d06c9f 147 #endif
jhon309 0:666850d06c9f 148
jhon309 0:666850d06c9f 149 #ifndef __Vendor_SysTickConfig
jhon309 0:666850d06c9f 150 #define __Vendor_SysTickConfig 0
jhon309 0:666850d06c9f 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
jhon309 0:666850d06c9f 152 #endif
jhon309 0:666850d06c9f 153 #endif
jhon309 0:666850d06c9f 154
jhon309 0:666850d06c9f 155 /* IO definitions (access restrictions to peripheral registers) */
jhon309 0:666850d06c9f 156 /**
jhon309 0:666850d06c9f 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
jhon309 0:666850d06c9f 158
jhon309 0:666850d06c9f 159 <strong>IO Type Qualifiers</strong> are used
jhon309 0:666850d06c9f 160 \li to specify the access to peripheral variables.
jhon309 0:666850d06c9f 161 \li for automatic generation of peripheral register debug information.
jhon309 0:666850d06c9f 162 */
jhon309 0:666850d06c9f 163 #ifdef __cplusplus
jhon309 0:666850d06c9f 164 #define __I volatile /*!< Defines 'read only' permissions */
jhon309 0:666850d06c9f 165 #else
jhon309 0:666850d06c9f 166 #define __I volatile const /*!< Defines 'read only' permissions */
jhon309 0:666850d06c9f 167 #endif
jhon309 0:666850d06c9f 168 #define __O volatile /*!< Defines 'write only' permissions */
jhon309 0:666850d06c9f 169 #define __IO volatile /*!< Defines 'read / write' permissions */
jhon309 0:666850d06c9f 170
jhon309 0:666850d06c9f 171 /*@} end of group Cortex_M0 */
jhon309 0:666850d06c9f 172
jhon309 0:666850d06c9f 173
jhon309 0:666850d06c9f 174
jhon309 0:666850d06c9f 175 /*******************************************************************************
jhon309 0:666850d06c9f 176 * Register Abstraction
jhon309 0:666850d06c9f 177 Core Register contain:
jhon309 0:666850d06c9f 178 - Core Register
jhon309 0:666850d06c9f 179 - Core NVIC Register
jhon309 0:666850d06c9f 180 - Core SCB Register
jhon309 0:666850d06c9f 181 - Core SysTick Register
jhon309 0:666850d06c9f 182 ******************************************************************************/
jhon309 0:666850d06c9f 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
jhon309 0:666850d06c9f 184 \brief Type definitions and defines for Cortex-M processor based devices.
jhon309 0:666850d06c9f 185 */
jhon309 0:666850d06c9f 186
jhon309 0:666850d06c9f 187 /** \ingroup CMSIS_core_register
jhon309 0:666850d06c9f 188 \defgroup CMSIS_CORE Status and Control Registers
jhon309 0:666850d06c9f 189 \brief Core Register type definitions.
jhon309 0:666850d06c9f 190 @{
jhon309 0:666850d06c9f 191 */
jhon309 0:666850d06c9f 192
jhon309 0:666850d06c9f 193 /** \brief Union type to access the Application Program Status Register (APSR).
jhon309 0:666850d06c9f 194 */
jhon309 0:666850d06c9f 195 typedef union
jhon309 0:666850d06c9f 196 {
jhon309 0:666850d06c9f 197 struct
jhon309 0:666850d06c9f 198 {
jhon309 0:666850d06c9f 199 #if (__CORTEX_M != 0x04)
jhon309 0:666850d06c9f 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
jhon309 0:666850d06c9f 201 #else
jhon309 0:666850d06c9f 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
jhon309 0:666850d06c9f 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:666850d06c9f 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
jhon309 0:666850d06c9f 205 #endif
jhon309 0:666850d06c9f 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:666850d06c9f 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:666850d06c9f 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:666850d06c9f 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:666850d06c9f 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:666850d06c9f 211 } b; /*!< Structure used for bit access */
jhon309 0:666850d06c9f 212 uint32_t w; /*!< Type used for word access */
jhon309 0:666850d06c9f 213 } APSR_Type;
jhon309 0:666850d06c9f 214
jhon309 0:666850d06c9f 215
jhon309 0:666850d06c9f 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
jhon309 0:666850d06c9f 217 */
jhon309 0:666850d06c9f 218 typedef union
jhon309 0:666850d06c9f 219 {
jhon309 0:666850d06c9f 220 struct
jhon309 0:666850d06c9f 221 {
jhon309 0:666850d06c9f 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:666850d06c9f 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
jhon309 0:666850d06c9f 224 } b; /*!< Structure used for bit access */
jhon309 0:666850d06c9f 225 uint32_t w; /*!< Type used for word access */
jhon309 0:666850d06c9f 226 } IPSR_Type;
jhon309 0:666850d06c9f 227
jhon309 0:666850d06c9f 228
jhon309 0:666850d06c9f 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
jhon309 0:666850d06c9f 230 */
jhon309 0:666850d06c9f 231 typedef union
jhon309 0:666850d06c9f 232 {
jhon309 0:666850d06c9f 233 struct
jhon309 0:666850d06c9f 234 {
jhon309 0:666850d06c9f 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
jhon309 0:666850d06c9f 236 #if (__CORTEX_M != 0x04)
jhon309 0:666850d06c9f 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
jhon309 0:666850d06c9f 238 #else
jhon309 0:666850d06c9f 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
jhon309 0:666850d06c9f 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
jhon309 0:666850d06c9f 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
jhon309 0:666850d06c9f 242 #endif
jhon309 0:666850d06c9f 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
jhon309 0:666850d06c9f 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
jhon309 0:666850d06c9f 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
jhon309 0:666850d06c9f 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
jhon309 0:666850d06c9f 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
jhon309 0:666850d06c9f 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
jhon309 0:666850d06c9f 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
jhon309 0:666850d06c9f 250 } b; /*!< Structure used for bit access */
jhon309 0:666850d06c9f 251 uint32_t w; /*!< Type used for word access */
jhon309 0:666850d06c9f 252 } xPSR_Type;
jhon309 0:666850d06c9f 253
jhon309 0:666850d06c9f 254
jhon309 0:666850d06c9f 255 /** \brief Union type to access the Control Registers (CONTROL).
jhon309 0:666850d06c9f 256 */
jhon309 0:666850d06c9f 257 typedef union
jhon309 0:666850d06c9f 258 {
jhon309 0:666850d06c9f 259 struct
jhon309 0:666850d06c9f 260 {
jhon309 0:666850d06c9f 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
jhon309 0:666850d06c9f 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
jhon309 0:666850d06c9f 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
jhon309 0:666850d06c9f 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
jhon309 0:666850d06c9f 265 } b; /*!< Structure used for bit access */
jhon309 0:666850d06c9f 266 uint32_t w; /*!< Type used for word access */
jhon309 0:666850d06c9f 267 } CONTROL_Type;
jhon309 0:666850d06c9f 268
jhon309 0:666850d06c9f 269 /*@} end of group CMSIS_CORE */
jhon309 0:666850d06c9f 270
jhon309 0:666850d06c9f 271
jhon309 0:666850d06c9f 272 /** \ingroup CMSIS_core_register
jhon309 0:666850d06c9f 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
jhon309 0:666850d06c9f 274 \brief Type definitions for the NVIC Registers
jhon309 0:666850d06c9f 275 @{
jhon309 0:666850d06c9f 276 */
jhon309 0:666850d06c9f 277
jhon309 0:666850d06c9f 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
jhon309 0:666850d06c9f 279 */
jhon309 0:666850d06c9f 280 typedef struct
jhon309 0:666850d06c9f 281 {
jhon309 0:666850d06c9f 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
jhon309 0:666850d06c9f 283 uint32_t RESERVED0[31];
jhon309 0:666850d06c9f 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
jhon309 0:666850d06c9f 285 uint32_t RSERVED1[31];
jhon309 0:666850d06c9f 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
jhon309 0:666850d06c9f 287 uint32_t RESERVED2[31];
jhon309 0:666850d06c9f 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
jhon309 0:666850d06c9f 289 uint32_t RESERVED3[31];
jhon309 0:666850d06c9f 290 uint32_t RESERVED4[64];
jhon309 0:666850d06c9f 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
jhon309 0:666850d06c9f 292 } NVIC_Type;
jhon309 0:666850d06c9f 293
jhon309 0:666850d06c9f 294 /*@} end of group CMSIS_NVIC */
jhon309 0:666850d06c9f 295
jhon309 0:666850d06c9f 296
jhon309 0:666850d06c9f 297 /** \ingroup CMSIS_core_register
jhon309 0:666850d06c9f 298 \defgroup CMSIS_SCB System Control Block (SCB)
jhon309 0:666850d06c9f 299 \brief Type definitions for the System Control Block Registers
jhon309 0:666850d06c9f 300 @{
jhon309 0:666850d06c9f 301 */
jhon309 0:666850d06c9f 302
jhon309 0:666850d06c9f 303 /** \brief Structure type to access the System Control Block (SCB).
jhon309 0:666850d06c9f 304 */
jhon309 0:666850d06c9f 305 typedef struct
jhon309 0:666850d06c9f 306 {
jhon309 0:666850d06c9f 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
jhon309 0:666850d06c9f 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
jhon309 0:666850d06c9f 309 uint32_t RESERVED0;
jhon309 0:666850d06c9f 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
jhon309 0:666850d06c9f 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
jhon309 0:666850d06c9f 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
jhon309 0:666850d06c9f 313 uint32_t RESERVED1;
jhon309 0:666850d06c9f 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
jhon309 0:666850d06c9f 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
jhon309 0:666850d06c9f 316 } SCB_Type;
jhon309 0:666850d06c9f 317
jhon309 0:666850d06c9f 318 /* SCB CPUID Register Definitions */
jhon309 0:666850d06c9f 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
jhon309 0:666850d06c9f 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
jhon309 0:666850d06c9f 321
jhon309 0:666850d06c9f 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
jhon309 0:666850d06c9f 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
jhon309 0:666850d06c9f 324
jhon309 0:666850d06c9f 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
jhon309 0:666850d06c9f 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
jhon309 0:666850d06c9f 327
jhon309 0:666850d06c9f 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
jhon309 0:666850d06c9f 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
jhon309 0:666850d06c9f 330
jhon309 0:666850d06c9f 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
jhon309 0:666850d06c9f 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
jhon309 0:666850d06c9f 333
jhon309 0:666850d06c9f 334 /* SCB Interrupt Control State Register Definitions */
jhon309 0:666850d06c9f 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
jhon309 0:666850d06c9f 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
jhon309 0:666850d06c9f 337
jhon309 0:666850d06c9f 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
jhon309 0:666850d06c9f 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
jhon309 0:666850d06c9f 340
jhon309 0:666850d06c9f 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
jhon309 0:666850d06c9f 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
jhon309 0:666850d06c9f 343
jhon309 0:666850d06c9f 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
jhon309 0:666850d06c9f 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
jhon309 0:666850d06c9f 346
jhon309 0:666850d06c9f 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
jhon309 0:666850d06c9f 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
jhon309 0:666850d06c9f 349
jhon309 0:666850d06c9f 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
jhon309 0:666850d06c9f 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
jhon309 0:666850d06c9f 352
jhon309 0:666850d06c9f 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
jhon309 0:666850d06c9f 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
jhon309 0:666850d06c9f 355
jhon309 0:666850d06c9f 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
jhon309 0:666850d06c9f 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
jhon309 0:666850d06c9f 358
jhon309 0:666850d06c9f 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
jhon309 0:666850d06c9f 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
jhon309 0:666850d06c9f 361
jhon309 0:666850d06c9f 362 /* SCB Application Interrupt and Reset Control Register Definitions */
jhon309 0:666850d06c9f 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
jhon309 0:666850d06c9f 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
jhon309 0:666850d06c9f 365
jhon309 0:666850d06c9f 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
jhon309 0:666850d06c9f 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
jhon309 0:666850d06c9f 368
jhon309 0:666850d06c9f 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
jhon309 0:666850d06c9f 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
jhon309 0:666850d06c9f 371
jhon309 0:666850d06c9f 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
jhon309 0:666850d06c9f 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
jhon309 0:666850d06c9f 374
jhon309 0:666850d06c9f 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
jhon309 0:666850d06c9f 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
jhon309 0:666850d06c9f 377
jhon309 0:666850d06c9f 378 /* SCB System Control Register Definitions */
jhon309 0:666850d06c9f 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
jhon309 0:666850d06c9f 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
jhon309 0:666850d06c9f 381
jhon309 0:666850d06c9f 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
jhon309 0:666850d06c9f 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
jhon309 0:666850d06c9f 384
jhon309 0:666850d06c9f 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
jhon309 0:666850d06c9f 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
jhon309 0:666850d06c9f 387
jhon309 0:666850d06c9f 388 /* SCB Configuration Control Register Definitions */
jhon309 0:666850d06c9f 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
jhon309 0:666850d06c9f 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
jhon309 0:666850d06c9f 391
jhon309 0:666850d06c9f 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
jhon309 0:666850d06c9f 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
jhon309 0:666850d06c9f 394
jhon309 0:666850d06c9f 395 /* SCB System Handler Control and State Register Definitions */
jhon309 0:666850d06c9f 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
jhon309 0:666850d06c9f 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
jhon309 0:666850d06c9f 398
jhon309 0:666850d06c9f 399 /*@} end of group CMSIS_SCB */
jhon309 0:666850d06c9f 400
jhon309 0:666850d06c9f 401
jhon309 0:666850d06c9f 402 /** \ingroup CMSIS_core_register
jhon309 0:666850d06c9f 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
jhon309 0:666850d06c9f 404 \brief Type definitions for the System Timer Registers.
jhon309 0:666850d06c9f 405 @{
jhon309 0:666850d06c9f 406 */
jhon309 0:666850d06c9f 407
jhon309 0:666850d06c9f 408 /** \brief Structure type to access the System Timer (SysTick).
jhon309 0:666850d06c9f 409 */
jhon309 0:666850d06c9f 410 typedef struct
jhon309 0:666850d06c9f 411 {
jhon309 0:666850d06c9f 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
jhon309 0:666850d06c9f 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
jhon309 0:666850d06c9f 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
jhon309 0:666850d06c9f 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
jhon309 0:666850d06c9f 416 } SysTick_Type;
jhon309 0:666850d06c9f 417
jhon309 0:666850d06c9f 418 /* SysTick Control / Status Register Definitions */
jhon309 0:666850d06c9f 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
jhon309 0:666850d06c9f 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
jhon309 0:666850d06c9f 421
jhon309 0:666850d06c9f 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
jhon309 0:666850d06c9f 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
jhon309 0:666850d06c9f 424
jhon309 0:666850d06c9f 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
jhon309 0:666850d06c9f 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
jhon309 0:666850d06c9f 427
jhon309 0:666850d06c9f 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
jhon309 0:666850d06c9f 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
jhon309 0:666850d06c9f 430
jhon309 0:666850d06c9f 431 /* SysTick Reload Register Definitions */
jhon309 0:666850d06c9f 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
jhon309 0:666850d06c9f 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
jhon309 0:666850d06c9f 434
jhon309 0:666850d06c9f 435 /* SysTick Current Register Definitions */
jhon309 0:666850d06c9f 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
jhon309 0:666850d06c9f 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
jhon309 0:666850d06c9f 438
jhon309 0:666850d06c9f 439 /* SysTick Calibration Register Definitions */
jhon309 0:666850d06c9f 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
jhon309 0:666850d06c9f 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
jhon309 0:666850d06c9f 442
jhon309 0:666850d06c9f 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
jhon309 0:666850d06c9f 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
jhon309 0:666850d06c9f 445
jhon309 0:666850d06c9f 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
jhon309 0:666850d06c9f 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
jhon309 0:666850d06c9f 448
jhon309 0:666850d06c9f 449 /*@} end of group CMSIS_SysTick */
jhon309 0:666850d06c9f 450
jhon309 0:666850d06c9f 451
jhon309 0:666850d06c9f 452 /** \ingroup CMSIS_core_register
jhon309 0:666850d06c9f 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
jhon309 0:666850d06c9f 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
jhon309 0:666850d06c9f 455 are only accessible over DAP and not via processor. Therefore
jhon309 0:666850d06c9f 456 they are not covered by the Cortex-M0 header file.
jhon309 0:666850d06c9f 457 @{
jhon309 0:666850d06c9f 458 */
jhon309 0:666850d06c9f 459 /*@} end of group CMSIS_CoreDebug */
jhon309 0:666850d06c9f 460
jhon309 0:666850d06c9f 461
jhon309 0:666850d06c9f 462 /** \ingroup CMSIS_core_register
jhon309 0:666850d06c9f 463 \defgroup CMSIS_core_base Core Definitions
jhon309 0:666850d06c9f 464 \brief Definitions for base addresses, unions, and structures.
jhon309 0:666850d06c9f 465 @{
jhon309 0:666850d06c9f 466 */
jhon309 0:666850d06c9f 467
jhon309 0:666850d06c9f 468 /* Memory mapping of Cortex-M0 Hardware */
jhon309 0:666850d06c9f 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
jhon309 0:666850d06c9f 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
jhon309 0:666850d06c9f 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
jhon309 0:666850d06c9f 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
jhon309 0:666850d06c9f 473
jhon309 0:666850d06c9f 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
jhon309 0:666850d06c9f 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
jhon309 0:666850d06c9f 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
jhon309 0:666850d06c9f 477
jhon309 0:666850d06c9f 478
jhon309 0:666850d06c9f 479 /*@} */
jhon309 0:666850d06c9f 480
jhon309 0:666850d06c9f 481
jhon309 0:666850d06c9f 482
jhon309 0:666850d06c9f 483 /*******************************************************************************
jhon309 0:666850d06c9f 484 * Hardware Abstraction Layer
jhon309 0:666850d06c9f 485 Core Function Interface contains:
jhon309 0:666850d06c9f 486 - Core NVIC Functions
jhon309 0:666850d06c9f 487 - Core SysTick Functions
jhon309 0:666850d06c9f 488 - Core Register Access Functions
jhon309 0:666850d06c9f 489 ******************************************************************************/
jhon309 0:666850d06c9f 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
jhon309 0:666850d06c9f 491 */
jhon309 0:666850d06c9f 492
jhon309 0:666850d06c9f 493
jhon309 0:666850d06c9f 494
jhon309 0:666850d06c9f 495 /* ########################## NVIC functions #################################### */
jhon309 0:666850d06c9f 496 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:666850d06c9f 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
jhon309 0:666850d06c9f 498 \brief Functions that manage interrupts and exceptions via the NVIC.
jhon309 0:666850d06c9f 499 @{
jhon309 0:666850d06c9f 500 */
jhon309 0:666850d06c9f 501
jhon309 0:666850d06c9f 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
jhon309 0:666850d06c9f 503 /* The following MACROS handle generation of the register offset and byte masks */
jhon309 0:666850d06c9f 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
jhon309 0:666850d06c9f 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
jhon309 0:666850d06c9f 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
jhon309 0:666850d06c9f 507
jhon309 0:666850d06c9f 508
jhon309 0:666850d06c9f 509 /** \brief Enable External Interrupt
jhon309 0:666850d06c9f 510
jhon309 0:666850d06c9f 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:666850d06c9f 512
jhon309 0:666850d06c9f 513 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:666850d06c9f 514 */
jhon309 0:666850d06c9f 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
jhon309 0:666850d06c9f 516 {
jhon309 0:666850d06c9f 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:666850d06c9f 518 }
jhon309 0:666850d06c9f 519
jhon309 0:666850d06c9f 520
jhon309 0:666850d06c9f 521 /** \brief Disable External Interrupt
jhon309 0:666850d06c9f 522
jhon309 0:666850d06c9f 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
jhon309 0:666850d06c9f 524
jhon309 0:666850d06c9f 525 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:666850d06c9f 526 */
jhon309 0:666850d06c9f 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
jhon309 0:666850d06c9f 528 {
jhon309 0:666850d06c9f 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:666850d06c9f 530 }
jhon309 0:666850d06c9f 531
jhon309 0:666850d06c9f 532
jhon309 0:666850d06c9f 533 /** \brief Get Pending Interrupt
jhon309 0:666850d06c9f 534
jhon309 0:666850d06c9f 535 The function reads the pending register in the NVIC and returns the pending bit
jhon309 0:666850d06c9f 536 for the specified interrupt.
jhon309 0:666850d06c9f 537
jhon309 0:666850d06c9f 538 \param [in] IRQn Interrupt number.
jhon309 0:666850d06c9f 539
jhon309 0:666850d06c9f 540 \return 0 Interrupt status is not pending.
jhon309 0:666850d06c9f 541 \return 1 Interrupt status is pending.
jhon309 0:666850d06c9f 542 */
jhon309 0:666850d06c9f 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
jhon309 0:666850d06c9f 544 {
jhon309 0:666850d06c9f 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
jhon309 0:666850d06c9f 546 }
jhon309 0:666850d06c9f 547
jhon309 0:666850d06c9f 548
jhon309 0:666850d06c9f 549 /** \brief Set Pending Interrupt
jhon309 0:666850d06c9f 550
jhon309 0:666850d06c9f 551 The function sets the pending bit of an external interrupt.
jhon309 0:666850d06c9f 552
jhon309 0:666850d06c9f 553 \param [in] IRQn Interrupt number. Value cannot be negative.
jhon309 0:666850d06c9f 554 */
jhon309 0:666850d06c9f 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
jhon309 0:666850d06c9f 556 {
jhon309 0:666850d06c9f 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
jhon309 0:666850d06c9f 558 }
jhon309 0:666850d06c9f 559
jhon309 0:666850d06c9f 560
jhon309 0:666850d06c9f 561 /** \brief Clear Pending Interrupt
jhon309 0:666850d06c9f 562
jhon309 0:666850d06c9f 563 The function clears the pending bit of an external interrupt.
jhon309 0:666850d06c9f 564
jhon309 0:666850d06c9f 565 \param [in] IRQn External interrupt number. Value cannot be negative.
jhon309 0:666850d06c9f 566 */
jhon309 0:666850d06c9f 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
jhon309 0:666850d06c9f 568 {
jhon309 0:666850d06c9f 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
jhon309 0:666850d06c9f 570 }
jhon309 0:666850d06c9f 571
jhon309 0:666850d06c9f 572
jhon309 0:666850d06c9f 573 /** \brief Set Interrupt Priority
jhon309 0:666850d06c9f 574
jhon309 0:666850d06c9f 575 The function sets the priority of an interrupt.
jhon309 0:666850d06c9f 576
jhon309 0:666850d06c9f 577 \note The priority cannot be set for every core interrupt.
jhon309 0:666850d06c9f 578
jhon309 0:666850d06c9f 579 \param [in] IRQn Interrupt number.
jhon309 0:666850d06c9f 580 \param [in] priority Priority to set.
jhon309 0:666850d06c9f 581 */
jhon309 0:666850d06c9f 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
jhon309 0:666850d06c9f 583 {
jhon309 0:666850d06c9f 584 if(IRQn < 0) {
jhon309 0:666850d06c9f 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:666850d06c9f 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:666850d06c9f 587 else {
jhon309 0:666850d06c9f 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
jhon309 0:666850d06c9f 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
jhon309 0:666850d06c9f 590 }
jhon309 0:666850d06c9f 591
jhon309 0:666850d06c9f 592
jhon309 0:666850d06c9f 593 /** \brief Get Interrupt Priority
jhon309 0:666850d06c9f 594
jhon309 0:666850d06c9f 595 The function reads the priority of an interrupt. The interrupt
jhon309 0:666850d06c9f 596 number can be positive to specify an external (device specific)
jhon309 0:666850d06c9f 597 interrupt, or negative to specify an internal (core) interrupt.
jhon309 0:666850d06c9f 598
jhon309 0:666850d06c9f 599
jhon309 0:666850d06c9f 600 \param [in] IRQn Interrupt number.
jhon309 0:666850d06c9f 601 \return Interrupt Priority. Value is aligned automatically to the implemented
jhon309 0:666850d06c9f 602 priority bits of the microcontroller.
jhon309 0:666850d06c9f 603 */
jhon309 0:666850d06c9f 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
jhon309 0:666850d06c9f 605 {
jhon309 0:666850d06c9f 606
jhon309 0:666850d06c9f 607 if(IRQn < 0) {
jhon309 0:666850d06c9f 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
jhon309 0:666850d06c9f 609 else {
jhon309 0:666850d06c9f 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
jhon309 0:666850d06c9f 611 }
jhon309 0:666850d06c9f 612
jhon309 0:666850d06c9f 613
jhon309 0:666850d06c9f 614 /** \brief System Reset
jhon309 0:666850d06c9f 615
jhon309 0:666850d06c9f 616 The function initiates a system reset request to reset the MCU.
jhon309 0:666850d06c9f 617 */
jhon309 0:666850d06c9f 618 __STATIC_INLINE void NVIC_SystemReset(void)
jhon309 0:666850d06c9f 619 {
jhon309 0:666850d06c9f 620 __DSB(); /* Ensure all outstanding memory accesses included
jhon309 0:666850d06c9f 621 buffered write are completed before reset */
jhon309 0:666850d06c9f 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
jhon309 0:666850d06c9f 623 SCB_AIRCR_SYSRESETREQ_Msk);
jhon309 0:666850d06c9f 624 __DSB(); /* Ensure completion of memory access */
jhon309 0:666850d06c9f 625 while(1); /* wait until reset */
jhon309 0:666850d06c9f 626 }
jhon309 0:666850d06c9f 627
jhon309 0:666850d06c9f 628 /*@} end of CMSIS_Core_NVICFunctions */
jhon309 0:666850d06c9f 629
jhon309 0:666850d06c9f 630
jhon309 0:666850d06c9f 631
jhon309 0:666850d06c9f 632 /* ################################## SysTick function ############################################ */
jhon309 0:666850d06c9f 633 /** \ingroup CMSIS_Core_FunctionInterface
jhon309 0:666850d06c9f 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
jhon309 0:666850d06c9f 635 \brief Functions that configure the System.
jhon309 0:666850d06c9f 636 @{
jhon309 0:666850d06c9f 637 */
jhon309 0:666850d06c9f 638
jhon309 0:666850d06c9f 639 #if (__Vendor_SysTickConfig == 0)
jhon309 0:666850d06c9f 640
jhon309 0:666850d06c9f 641 /** \brief System Tick Configuration
jhon309 0:666850d06c9f 642
jhon309 0:666850d06c9f 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
jhon309 0:666850d06c9f 644 Counter is in free running mode to generate periodic interrupts.
jhon309 0:666850d06c9f 645
jhon309 0:666850d06c9f 646 \param [in] ticks Number of ticks between two interrupts.
jhon309 0:666850d06c9f 647
jhon309 0:666850d06c9f 648 \return 0 Function succeeded.
jhon309 0:666850d06c9f 649 \return 1 Function failed.
jhon309 0:666850d06c9f 650
jhon309 0:666850d06c9f 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
jhon309 0:666850d06c9f 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
jhon309 0:666850d06c9f 653 must contain a vendor-specific implementation of this function.
jhon309 0:666850d06c9f 654
jhon309 0:666850d06c9f 655 */
jhon309 0:666850d06c9f 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
jhon309 0:666850d06c9f 657 {
jhon309 0:666850d06c9f 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
jhon309 0:666850d06c9f 659
jhon309 0:666850d06c9f 660 SysTick->LOAD = ticks - 1; /* set reload register */
jhon309 0:666850d06c9f 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
jhon309 0:666850d06c9f 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
jhon309 0:666850d06c9f 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
jhon309 0:666850d06c9f 664 SysTick_CTRL_TICKINT_Msk |
jhon309 0:666850d06c9f 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
jhon309 0:666850d06c9f 666 return (0); /* Function successful */
jhon309 0:666850d06c9f 667 }
jhon309 0:666850d06c9f 668
jhon309 0:666850d06c9f 669 #endif
jhon309 0:666850d06c9f 670
jhon309 0:666850d06c9f 671 /*@} end of CMSIS_Core_SysTickFunctions */
jhon309 0:666850d06c9f 672
jhon309 0:666850d06c9f 673
jhon309 0:666850d06c9f 674
jhon309 0:666850d06c9f 675
jhon309 0:666850d06c9f 676 #endif /* __CORE_CM0_H_DEPENDANT */
jhon309 0:666850d06c9f 677
jhon309 0:666850d06c9f 678 #endif /* __CMSIS_GENERIC */
jhon309 0:666850d06c9f 679
jhon309 0:666850d06c9f 680 #ifdef __cplusplus
jhon309 0:666850d06c9f 681 }
jhon309 0:666850d06c9f 682 #endif