jeong chanmi / WIZnetInterface_

modify for blynk

Fork of WIZnetInterface by WIZnet

arch/int/W7500x_toe.cpp@25:48abbe1d9bab, 2015-10-05 (annotated)

Committer:
hjjeon
Date:
Mon Oct 05 05:34:44 2015 +0000
Revision:
25:48abbe1d9bab
Parent:
19:d8773cd4edc5 
Add defines about W7500P

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Soohwan Kim 0:6f28332c466f 1 /* Copyright (C) 2012 mbed.org, MIT License
Soohwan Kim 0:6f28332c466f 2 *
Soohwan Kim 0:6f28332c466f 3 * and associated documentation files (the "Software"), to deal in the Software without restriction,
Soohwan Kim 0:6f28332c466f 4 * including without limitation the rights to use, copy, modify, merge, publish, distribute,
Soohwan Kim 0:6f28332c466f 5 * sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is
Soohwan Kim 0:6f28332c466f 6 * furnished to do so, subject to the following conditions:
Soohwan Kim 0:6f28332c466f 7 *
Soohwan Kim 0:6f28332c466f 8 * The above copyright notice and this permission notice shall be included in all copies or
Soohwan Kim 0:6f28332c466f 9 * substantial portions of the Software.
Soohwan Kim 0:6f28332c466f 10 *
Soohwan Kim 0:6f28332c466f 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
Soohwan Kim 0:6f28332c466f 12 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
Soohwan Kim 0:6f28332c466f 13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
Soohwan Kim 0:6f28332c466f 14 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
Soohwan Kim 0:6f28332c466f 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
Soohwan Kim 0:6f28332c466f 16 */
embeddist 3:f8c6efc8bf83 17 #include "eth_arch.h"
hjjeon 25:48abbe1d9bab 18 #if defined(TARGET_WIZwiki_W7500) || defined(TARGET_WIZwiki_W7500P)
hjjeon 25:48abbe1d9bab 19
Soohwan Kim 0:6f28332c466f 20
Soohwan Kim 0:6f28332c466f 21 #include "mbed.h"
Soohwan Kim 0:6f28332c466f 22 #include "mbed_debug.h"
Soohwan Kim 0:6f28332c466f 23 #include "DNSClient.h"
Soohwan Kim 0:6f28332c466f 24
Soohwan Kim 0:6f28332c466f 25
Soohwan Kim 0:6f28332c466f 26 /*
Soohwan Kim 0:6f28332c466f 27 * MDIO via GPIO
Soohwan Kim 0:6f28332c466f 28 * mdio via gpio is supported and related functions as follows.
Soohwan Kim 0:6f28332c466f 29 * - mdio_init(),mdio_read(),mdio_write()
Soohwan Kim 0:6f28332c466f 30 * - input_MDIO(),output_MDIO(),turnaroud_MDIO(),idle_MDIO()
Soohwan Kim 0:6f28332c466f 31 * called by ethernet_link() and ethernet_set_link()
Soohwan Kim 0:6f28332c466f 32 */
hjjeon 25:48abbe1d9bab 33
hjjeon 25:48abbe1d9bab 34 #if defined TARGET_WIZwiki_W7500
hjjeon 25:48abbe1d9bab 35
Soohwan Kim 0:6f28332c466f 36 #define MDIO GPIO_Pin_14
Soohwan Kim 0:6f28332c466f 37 #define MDC GPIO_Pin_15
Soohwan Kim 0:6f28332c466f 38 #define GPIO_MDC GPIOB
Soohwan Kim 0:6f28332c466f 39 #define PHY_ADDR_IP101G 0x07
Soohwan Kim 0:6f28332c466f 40 #define PHY_ADDR PHY_ADDR_IP101G
Soohwan Kim 0:6f28332c466f 41 #define SVAL 0x2 //right shift val = 2
Soohwan Kim 0:6f28332c466f 42 #define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register)
Soohwan Kim 0:6f28332c466f 43 #define PHYREG_STATUS 0x1 //Status Register address (Status basic register)
Soohwan Kim 0:6f28332c466f 44 #define CNTL_DUPLEX (0x01ul<< 7)
Soohwan Kim 0:6f28332c466f 45 #define CNTL_AUTONEGO (0x01ul<<11)
Soohwan Kim 0:6f28332c466f 46 #define CNTL_SPEED (0x01ul<<12)
Soohwan Kim 0:6f28332c466f 47 #define MDC_WAIT (1)
hjjeon 25:48abbe1d9bab 48
hjjeon 25:48abbe1d9bab 49 #elif TARGET_WIZwiki_W7500P
hjjeon 25:48abbe1d9bab 50
hjjeon 25:48abbe1d9bab 51 #define MDIO GPIO_Pin_15
hjjeon 25:48abbe1d9bab 52 #define MDC GPIO_Pin_14
hjjeon 25:48abbe1d9bab 53 #define GPIO_MDC GPIOB
hjjeon 25:48abbe1d9bab 54 #define PHY_ADDR_IP101G 0x01
hjjeon 25:48abbe1d9bab 55 #define PHY_ADDR PHY_ADDR_IP101G
hjjeon 25:48abbe1d9bab 56 #define SVAL 0x2 //right shift val = 2
hjjeon 25:48abbe1d9bab 57 #define PHYREG_CONTROL 0x0 //Control Register address (Contorl basic register)
hjjeon 25:48abbe1d9bab 58 #define PHYREG_STATUS 0x1 //Status Register address (Status basic register)
hjjeon 25:48abbe1d9bab 59 #define CNTL_DUPLEX (0x01ul<< 7)
hjjeon 25:48abbe1d9bab 60 #define CNTL_AUTONEGO (0x01ul<<11)
hjjeon 25:48abbe1d9bab 61 #define CNTL_SPEED (0x01ul<<12)
hjjeon 25:48abbe1d9bab 62 #define MDC_WAIT (1)
hjjeon 25:48abbe1d9bab 63
hjjeon 25:48abbe1d9bab 64 #endif
hjjeon 25:48abbe1d9bab 65
Soohwan Kim 0:6f28332c466f 66 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO);
Soohwan Kim 0:6f28332c466f 67 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val);
Soohwan Kim 0:6f28332c466f 68 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr);
Soohwan Kim 0:6f28332c466f 69
Soohwan Kim 0:6f28332c466f 70 WIZnet_Chip* WIZnet_Chip::inst;
Soohwan Kim 0:6f28332c466f 71
Soohwan Kim 0:6f28332c466f 72 WIZnet_Chip::WIZnet_Chip()
Soohwan Kim 0:6f28332c466f 73 {
Soohwan Kim 0:6f28332c466f 74 inst = this;
Soohwan Kim 0:6f28332c466f 75 }
Soohwan Kim 0:6f28332c466f 76
Soohwan Kim 8:4c02de1dbf3a 77 bool WIZnet_Chip::setmac()
Soohwan Kim 8:4c02de1dbf3a 78 {
Soohwan Kim 8:4c02de1dbf3a 79
Soohwan Kim 8:4c02de1dbf3a 80 for (int i =0; i < 6; i++) reg_wr<uint8_t>(SHAR+i, mac[i]);
Soohwan Kim 8:4c02de1dbf3a 81
Soohwan Kim 8:4c02de1dbf3a 82 return true;
Soohwan Kim 8:4c02de1dbf3a 83 }
Soohwan Kim 8:4c02de1dbf3a 84
Soohwan Kim 0:6f28332c466f 85 // Set the IP
Soohwan Kim 0:6f28332c466f 86 bool WIZnet_Chip::setip()
Soohwan Kim 0:6f28332c466f 87 {
Soohwan Kim 0:6f28332c466f 88 reg_wr<uint32_t>(SIPR, ip);
Soohwan Kim 0:6f28332c466f 89 reg_wr<uint32_t>(GAR, gateway);
Soohwan Kim 0:6f28332c466f 90 reg_wr<uint32_t>(SUBR, netmask);
Soohwan Kim 0:6f28332c466f 91 return true;
Soohwan Kim 0:6f28332c466f 92 }
Soohwan Kim 0:6f28332c466f 93
Soohwan Kim 0:6f28332c466f 94 bool WIZnet_Chip::setProtocol(int socket, Protocol p)
Soohwan Kim 0:6f28332c466f 95 {
Soohwan Kim 0:6f28332c466f 96 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 97 return false;
Soohwan Kim 0:6f28332c466f 98 }
Soohwan Kim 0:6f28332c466f 99 sreg<uint8_t>(socket, Sn_MR, p);
Soohwan Kim 0:6f28332c466f 100 return true;
Soohwan Kim 0:6f28332c466f 101 }
Soohwan Kim 0:6f28332c466f 102
Soohwan Kim 0:6f28332c466f 103 bool WIZnet_Chip::connect(int socket, const char * host, int port, int timeout_ms)
Soohwan Kim 0:6f28332c466f 104 {
Soohwan Kim 0:6f28332c466f 105 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 106 return false;
Soohwan Kim 0:6f28332c466f 107 }
Soohwan Kim 0:6f28332c466f 108 sreg<uint8_t>(socket, Sn_MR, TCP);
Soohwan Kim 0:6f28332c466f 109 scmd(socket, OPEN);
Soohwan Kim 0:6f28332c466f 110 sreg_ip(socket, Sn_DIPR, host);
Soohwan Kim 0:6f28332c466f 111 sreg<uint16_t>(socket, Sn_DPORT, port);
Soohwan Kim 0:6f28332c466f 112 sreg<uint16_t>(socket, Sn_PORT, new_port());
Soohwan Kim 0:6f28332c466f 113 scmd(socket, CONNECT);
Soohwan Kim 0:6f28332c466f 114 Timer t;
Soohwan Kim 0:6f28332c466f 115 t.reset();
Soohwan Kim 0:6f28332c466f 116 t.start();
Soohwan Kim 0:6f28332c466f 117 while(!is_connected(socket)) {
Soohwan Kim 0:6f28332c466f 118 if (t.read_ms() > timeout_ms) {
Soohwan Kim 0:6f28332c466f 119 return false;
Soohwan Kim 0:6f28332c466f 120 }
Soohwan Kim 0:6f28332c466f 121 }
Soohwan Kim 0:6f28332c466f 122 return true;
Soohwan Kim 0:6f28332c466f 123 }
Soohwan Kim 0:6f28332c466f 124
Soohwan Kim 0:6f28332c466f 125 bool WIZnet_Chip::gethostbyname(const char* host, uint32_t* ip)
Soohwan Kim 0:6f28332c466f 126 {
Soohwan Kim 0:6f28332c466f 127 uint32_t addr = str_to_ip(host);
Soohwan Kim 0:6f28332c466f 128 char buf[17];
Soohwan Kim 0:6f28332c466f 129 snprintf(buf, sizeof(buf), "%d.%d.%d.%d",
Soohwan Kim 0:6f28332c466f 130 (uint8_t)((addr>>24)&0xff),
Soohwan Kim 0:6f28332c466f 131 (uint8_t)((addr>>16)&0xff),
Soohwan Kim 0:6f28332c466f 132 (uint8_t)((addr>>8)&0xff),
Soohwan Kim 0:6f28332c466f 133 (uint8_t)(addr&0xff));
Soohwan Kim 0:6f28332c466f 134 if (strcmp(buf, host) == 0) {
Soohwan Kim 0:6f28332c466f 135 *ip = addr;
Soohwan Kim 0:6f28332c466f 136 return true;
Soohwan Kim 0:6f28332c466f 137 }
Soohwan Kim 0:6f28332c466f 138 DNSClient client;
Soohwan Kim 0:6f28332c466f 139 if(client.lookup(host)) {
Soohwan Kim 0:6f28332c466f 140 *ip = client.ip;
Soohwan Kim 0:6f28332c466f 141 return true;
Soohwan Kim 0:6f28332c466f 142 }
Soohwan Kim 0:6f28332c466f 143 return false;
Soohwan Kim 0:6f28332c466f 144 }
Soohwan Kim 0:6f28332c466f 145
Soohwan Kim 0:6f28332c466f 146
Soohwan Kim 0:6f28332c466f 147 bool WIZnet_Chip::is_connected(int socket)
Soohwan Kim 0:6f28332c466f 148 {
Soohwan Kim 0:6f28332c466f 149 /*
Soohwan Kim 0:6f28332c466f 150 if (sreg<uint8_t>(socket, Sn_SR) == SOCK_ESTABLISHED) {
Soohwan Kim 0:6f28332c466f 151 return true;
Soohwan Kim 0:6f28332c466f 152 }
Soohwan Kim 0:6f28332c466f 153 */
Soohwan Kim 0:6f28332c466f 154 uint8_t tmpSn_SR;
Soohwan Kim 0:6f28332c466f 155 tmpSn_SR = sreg<uint8_t>(socket, Sn_SR);
Soohwan Kim 0:6f28332c466f 156 // packet sending is possible, when state is SOCK_CLOSE_WAIT.
Soohwan Kim 0:6f28332c466f 157 if ((tmpSn_SR == SOCK_ESTABLISHED) || (tmpSn_SR == SOCK_CLOSE_WAIT)) {
Soohwan Kim 0:6f28332c466f 158 return true;
Soohwan Kim 0:6f28332c466f 159 }
Soohwan Kim 0:6f28332c466f 160 return false;
Soohwan Kim 0:6f28332c466f 161 }
Soohwan Kim 0:6f28332c466f 162 // Reset the chip & set the buffer
Soohwan Kim 0:6f28332c466f 163 void WIZnet_Chip::reset()
Soohwan Kim 0:6f28332c466f 164 {
Soohwan Kim 0:6f28332c466f 165 /* S/W Reset PHY */
Soohwan Kim 0:6f28332c466f 166 mdio_write(GPIO_MDC, PHYREG_CONTROL, 0x8000);
Soohwan Kim 0:6f28332c466f 167 wait_ms(10);//for S/W reset
Soohwan Kim 0:6f28332c466f 168 wait_ms(10);//for MDC I/F RDY
Soohwan Kim 0:6f28332c466f 169
embeddist 15:24a9f2df2145 170 mdio_init(GPIO_MDC, MDC, MDIO);
embeddist 15:24a9f2df2145 171
Soohwan Kim 0:6f28332c466f 172 /* S/W Reset WZTOE */
Soohwan Kim 0:6f28332c466f 173 reg_wr<uint8_t>(MR, MR_RST);
Soohwan Kim 0:6f28332c466f 174 // set PAD strengh and pull-up for TXD[3:0] and TXE
Soohwan Kim 0:6f28332c466f 175 #ifdef __DEF_USED_IC101AG__ //For using IC+101AG
hjjeon 25:48abbe1d9bab 176
hjjeon 25:48abbe1d9bab 177 #if defined(TARGET_WIZwiki_W7500)
hjjeon 25:48abbe1d9bab 178
Soohwan Kim 0:6f28332c466f 179 *(volatile uint32_t *)(0x41003068) = 0x64; //TXD0
Soohwan Kim 0:6f28332c466f 180 *(volatile uint32_t *)(0x4100306C) = 0x64; //TXD1
Soohwan Kim 0:6f28332c466f 181 *(volatile uint32_t *)(0x41003070) = 0x64; //TXD2
Soohwan Kim 0:6f28332c466f 182 *(volatile uint32_t *)(0x41003074) = 0x64; //TXD3
Soohwan Kim 0:6f28332c466f 183 *(volatile uint32_t *)(0x41003050) = 0x64; //TXE
hjjeon 25:48abbe1d9bab 184 #endif
hjjeon 25:48abbe1d9bab 185
Soohwan Kim 0:6f28332c466f 186 #endif
hjjeon 25:48abbe1d9bab 187
Soohwan Kim 0:6f28332c466f 188 // set ticker counter
Soohwan Kim 0:6f28332c466f 189 reg_wr<uint32_t>(TIC100US, (SystemCoreClock/10000));
Soohwan Kim 0:6f28332c466f 190 // write MAC address inside the WZTOE MAC address register
Soohwan Kim 0:6f28332c466f 191 reg_wr_mac(SHAR, mac);
Soohwan Kim 0:6f28332c466f 192 /*
Soohwan Kim 0:6f28332c466f 193 * set RX and TX buffer size
Soohwan Kim 0:6f28332c466f 194 * for (int socket = 0; socket < MAX_SOCK_NUM; socket++) {
Soohwan Kim 0:6f28332c466f 195 * sreg<uint8_t>(socket, Sn_RXBUF_SIZE, 2);
Soohwan Kim 0:6f28332c466f 196 * sreg<uint8_t>(socket, Sn_TXBUF_SIZE, 2);
Soohwan Kim 0:6f28332c466f 197 * }
Soohwan Kim 0:6f28332c466f 198 */
Soohwan Kim 0:6f28332c466f 199 }
Soohwan Kim 0:6f28332c466f 200
Soohwan Kim 0:6f28332c466f 201
Soohwan Kim 0:6f28332c466f 202 bool WIZnet_Chip::close(int socket)
Soohwan Kim 0:6f28332c466f 203 {
Soohwan Kim 0:6f28332c466f 204 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 205 return false;
Soohwan Kim 0:6f28332c466f 206 }
Soohwan Kim 0:6f28332c466f 207 // if SOCK_CLOSED, return
Soohwan Kim 0:6f28332c466f 208 if (sreg<uint8_t>(socket, Sn_SR) == SOCK_CLOSED) {
Soohwan Kim 0:6f28332c466f 209 return true;
Soohwan Kim 0:6f28332c466f 210 }
Soohwan Kim 0:6f28332c466f 211 // if SOCK_ESTABLISHED, send FIN-Packet to peer
Soohwan Kim 0:6f28332c466f 212 if (sreg<uint8_t>(socket, Sn_MR) == TCP) {
Soohwan Kim 0:6f28332c466f 213 scmd(socket, DISCON);
Soohwan Kim 0:6f28332c466f 214 }
Soohwan Kim 0:6f28332c466f 215 // close socket
Soohwan Kim 0:6f28332c466f 216 scmd(socket, CLOSE);
Soohwan Kim 0:6f28332c466f 217 // clear Socket Interrupt Register
Soohwan Kim 0:6f28332c466f 218 sreg<uint8_t>(socket, Sn_ICR, 0xff);
Soohwan Kim 0:6f28332c466f 219 return true;
Soohwan Kim 0:6f28332c466f 220 }
Soohwan Kim 0:6f28332c466f 221
Soohwan Kim 0:6f28332c466f 222 int WIZnet_Chip::wait_readable(int socket, int wait_time_ms, int req_size)
Soohwan Kim 0:6f28332c466f 223 {
Soohwan Kim 0:6f28332c466f 224 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 225 return -1;
Soohwan Kim 0:6f28332c466f 226 }
Soohwan Kim 0:6f28332c466f 227 Timer t;
Soohwan Kim 0:6f28332c466f 228 t.reset();
Soohwan Kim 0:6f28332c466f 229 t.start();
Soohwan Kim 0:6f28332c466f 230 while(1) {
Soohwan Kim 0:6f28332c466f 231 int size = sreg<uint16_t>(socket, Sn_RX_RSR);
Soohwan Kim 0:6f28332c466f 232 if (size > req_size) {
Soohwan Kim 0:6f28332c466f 233 return size;
Soohwan Kim 0:6f28332c466f 234 }
Soohwan Kim 0:6f28332c466f 235 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 236 break;
Soohwan Kim 0:6f28332c466f 237 }
Soohwan Kim 0:6f28332c466f 238 }
Soohwan Kim 0:6f28332c466f 239 return -1;
Soohwan Kim 0:6f28332c466f 240 }
Soohwan Kim 0:6f28332c466f 241
Soohwan Kim 0:6f28332c466f 242 int WIZnet_Chip::wait_writeable(int socket, int wait_time_ms, int req_size)
Soohwan Kim 0:6f28332c466f 243 {
Soohwan Kim 0:6f28332c466f 244 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 245 return -1;
Soohwan Kim 0:6f28332c466f 246 }
Soohwan Kim 0:6f28332c466f 247 Timer t;
Soohwan Kim 0:6f28332c466f 248 t.reset();
Soohwan Kim 0:6f28332c466f 249 t.start();
Soohwan Kim 0:6f28332c466f 250 while(1) {
Soohwan Kim 0:6f28332c466f 251 int size = sreg<uint16_t>(socket, Sn_TX_FSR);
Soohwan Kim 0:6f28332c466f 252 if (size > req_size) {
Soohwan Kim 0:6f28332c466f 253 return size;
Soohwan Kim 0:6f28332c466f 254 }
Soohwan Kim 0:6f28332c466f 255 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 256 break;
Soohwan Kim 0:6f28332c466f 257 }
Soohwan Kim 0:6f28332c466f 258 }
Soohwan Kim 0:6f28332c466f 259 return -1;
Soohwan Kim 0:6f28332c466f 260 }
Soohwan Kim 0:6f28332c466f 261
Soohwan Kim 0:6f28332c466f 262 int WIZnet_Chip::send(int socket, const char * str, int len)
Soohwan Kim 0:6f28332c466f 263 {
Soohwan Kim 0:6f28332c466f 264 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 265 return -1;
Soohwan Kim 0:6f28332c466f 266 }
Soohwan Kim 0:6f28332c466f 267
Soohwan Kim 0:6f28332c466f 268 uint16_t ptr = sreg<uint16_t>(socket, Sn_TX_WR);
Soohwan Kim 0:6f28332c466f 269 uint32_t sn_tx_base = W7500x_TXMEM_BASE + (uint32_t)(socket<<18);
Soohwan Kim 0:6f28332c466f 270
Soohwan Kim 0:6f28332c466f 271 for(int i=0; i<len; i++)
Soohwan Kim 0:6f28332c466f 272 *(volatile uint8_t *)(sn_tx_base + ((ptr+i)&0xFFFF)) = str[i];
Soohwan Kim 0:6f28332c466f 273
Soohwan Kim 0:6f28332c466f 274 sreg<uint16_t>(socket, Sn_TX_WR, ptr + len);
Soohwan Kim 0:6f28332c466f 275 scmd(socket, SEND);
Soohwan Kim 0:6f28332c466f 276
Soohwan Kim 0:6f28332c466f 277 uint8_t tmp_Sn_IR;
Soohwan Kim 0:6f28332c466f 278 while (( (tmp_Sn_IR = sreg<uint8_t>(socket, Sn_IR)) & INT_SEND_OK) != INT_SEND_OK) {
Soohwan Kim 0:6f28332c466f 279 // @Jul.10, 2014 fix contant name, and udp sendto function.
Soohwan Kim 0:6f28332c466f 280 switch (sreg<uint8_t>(socket, Sn_SR)) {
Soohwan Kim 0:6f28332c466f 281 case SOCK_CLOSED :
Soohwan Kim 0:6f28332c466f 282 close(socket);
Soohwan Kim 0:6f28332c466f 283 return 0;
Soohwan Kim 0:6f28332c466f 284 //break;
Soohwan Kim 0:6f28332c466f 285 case SOCK_UDP :
Soohwan Kim 0:6f28332c466f 286 // ARP timeout is possible.
Soohwan Kim 0:6f28332c466f 287 if ((tmp_Sn_IR & INT_TIMEOUT) == INT_TIMEOUT) {
Soohwan Kim 0:6f28332c466f 288 sreg<uint8_t>(socket, Sn_ICR, INT_TIMEOUT);
Soohwan Kim 0:6f28332c466f 289 return 0;
Soohwan Kim 0:6f28332c466f 290 }
Soohwan Kim 0:6f28332c466f 291 break;
Soohwan Kim 0:6f28332c466f 292 default :
Soohwan Kim 0:6f28332c466f 293 break;
Soohwan Kim 0:6f28332c466f 294 }
Soohwan Kim 0:6f28332c466f 295 }
Soohwan Kim 0:6f28332c466f 296
Soohwan Kim 0:6f28332c466f 297 sreg<uint8_t>(socket, Sn_ICR, INT_SEND_OK);
Soohwan Kim 0:6f28332c466f 298
Soohwan Kim 0:6f28332c466f 299 return len;
Soohwan Kim 0:6f28332c466f 300 }
Soohwan Kim 0:6f28332c466f 301
Soohwan Kim 0:6f28332c466f 302 int WIZnet_Chip::recv(int socket, char* buf, int len)
Soohwan Kim 0:6f28332c466f 303 {
Soohwan Kim 0:6f28332c466f 304 if (socket < 0) {
Soohwan Kim 0:6f28332c466f 305 return -1;
Soohwan Kim 0:6f28332c466f 306 }
Soohwan Kim 0:6f28332c466f 307 uint16_t ptr = sreg<uint16_t>(socket, Sn_RX_RD);
Soohwan Kim 0:6f28332c466f 308 uint32_t sn_rx_base = W7500x_RXMEM_BASE + (uint32_t)(socket<<18);
Soohwan Kim 0:6f28332c466f 309
Soohwan Kim 0:6f28332c466f 310 for(int i=0; i<len; i++)
Soohwan Kim 0:6f28332c466f 311 buf[i] = *(volatile uint8_t *)(sn_rx_base + ((ptr+i)&0xFFFF));
Soohwan Kim 0:6f28332c466f 312
Soohwan Kim 0:6f28332c466f 313 sreg<uint16_t>(socket, Sn_RX_RD, ptr + len);
Soohwan Kim 0:6f28332c466f 314 scmd(socket, RECV);
Soohwan Kim 0:6f28332c466f 315
Soohwan Kim 0:6f28332c466f 316 return len;
Soohwan Kim 0:6f28332c466f 317 }
Soohwan Kim 0:6f28332c466f 318
Soohwan Kim 0:6f28332c466f 319 int WIZnet_Chip::new_socket()
Soohwan Kim 0:6f28332c466f 320 {
Soohwan Kim 0:6f28332c466f 321 for(int s = 0; s < MAX_SOCK_NUM; s++) {
Soohwan Kim 0:6f28332c466f 322 if (sreg<uint8_t>(s, Sn_SR) == SOCK_CLOSED) {
Soohwan Kim 0:6f28332c466f 323 return s;
Soohwan Kim 0:6f28332c466f 324 }
Soohwan Kim 0:6f28332c466f 325 }
Soohwan Kim 0:6f28332c466f 326 return -1;
Soohwan Kim 0:6f28332c466f 327 }
Soohwan Kim 0:6f28332c466f 328
Soohwan Kim 0:6f28332c466f 329 uint16_t WIZnet_Chip::new_port()
Soohwan Kim 0:6f28332c466f 330 {
Soohwan Kim 0:6f28332c466f 331 uint16_t port = rand();
Soohwan Kim 0:6f28332c466f 332 port |= 49152;
Soohwan Kim 0:6f28332c466f 333 return port;
Soohwan Kim 0:6f28332c466f 334 }
Soohwan Kim 0:6f28332c466f 335
Soohwan Kim 0:6f28332c466f 336 bool WIZnet_Chip::link(int wait_time_ms)
Soohwan Kim 0:6f28332c466f 337 {
Soohwan Kim 0:6f28332c466f 338 Timer t;
Soohwan Kim 0:6f28332c466f 339 t.reset();
Soohwan Kim 0:6f28332c466f 340 t.start();
Soohwan Kim 0:6f28332c466f 341 while(1) {
Soohwan Kim 0:6f28332c466f 342 int is_link = ethernet_link();
hjjeon 19:d8773cd4edc5 343
Soohwan Kim 0:6f28332c466f 344 if (is_link) {
Soohwan Kim 0:6f28332c466f 345 return true;
Soohwan Kim 0:6f28332c466f 346 }
Soohwan Kim 0:6f28332c466f 347 if (wait_time_ms != (-1) && t.read_ms() > wait_time_ms) {
Soohwan Kim 0:6f28332c466f 348 break;
Soohwan Kim 0:6f28332c466f 349 }
Soohwan Kim 0:6f28332c466f 350 }
Soohwan Kim 0:6f28332c466f 351 return 0;
Soohwan Kim 0:6f28332c466f 352 }
Soohwan Kim 0:6f28332c466f 353
Soohwan Kim 0:6f28332c466f 354 void WIZnet_Chip::set_link(PHYMode phymode)
Soohwan Kim 0:6f28332c466f 355 {
Soohwan Kim 0:6f28332c466f 356 int speed = -1;
Soohwan Kim 0:6f28332c466f 357 int duplex = 0;
Soohwan Kim 0:6f28332c466f 358
Soohwan Kim 0:6f28332c466f 359 switch(phymode) {
Soohwan Kim 0:6f28332c466f 360 case AutoNegotiate : speed = -1; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 361 case HalfDuplex10 : speed = 0; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 362 case FullDuplex10 : speed = 0; duplex = 1; break;
Soohwan Kim 0:6f28332c466f 363 case HalfDuplex100 : speed = 1; duplex = 0; break;
Soohwan Kim 0:6f28332c466f 364 case FullDuplex100 : speed = 1; duplex = 1; break;
Soohwan Kim 0:6f28332c466f 365 }
Soohwan Kim 0:6f28332c466f 366
Soohwan Kim 0:6f28332c466f 367 ethernet_set_link(speed, duplex);
Soohwan Kim 0:6f28332c466f 368 }
Soohwan Kim 0:6f28332c466f 369
Soohwan Kim 0:6f28332c466f 370 uint32_t str_to_ip(const char* str)
Soohwan Kim 0:6f28332c466f 371 {
Soohwan Kim 0:6f28332c466f 372 uint32_t ip = 0;
Soohwan Kim 0:6f28332c466f 373 char* p = (char*)str;
Soohwan Kim 0:6f28332c466f 374 for(int i = 0; i < 4; i++) {
Soohwan Kim 0:6f28332c466f 375 ip |= atoi(p);
Soohwan Kim 0:6f28332c466f 376 p = strchr(p, '.');
Soohwan Kim 0:6f28332c466f 377 if (p == NULL) {
Soohwan Kim 0:6f28332c466f 378 break;
Soohwan Kim 0:6f28332c466f 379 }
Soohwan Kim 0:6f28332c466f 380 ip <<= 8;
Soohwan Kim 0:6f28332c466f 381 p++;
Soohwan Kim 0:6f28332c466f 382 }
Soohwan Kim 0:6f28332c466f 383 return ip;
Soohwan Kim 0:6f28332c466f 384 }
Soohwan Kim 0:6f28332c466f 385
Soohwan Kim 0:6f28332c466f 386 void printfBytes(char* str, uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 387 {
Soohwan Kim 0:6f28332c466f 388 printf("%s %d:", str, len);
Soohwan Kim 0:6f28332c466f 389 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 390 printf(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 391 }
Soohwan Kim 0:6f28332c466f 392 printf("\n");
Soohwan Kim 0:6f28332c466f 393 }
Soohwan Kim 0:6f28332c466f 394
Soohwan Kim 0:6f28332c466f 395 void printHex(uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 396 {
Soohwan Kim 0:6f28332c466f 397 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 398 if ((i%16) == 0) {
Soohwan Kim 0:6f28332c466f 399 printf("%p", buf+i);
Soohwan Kim 0:6f28332c466f 400 }
Soohwan Kim 0:6f28332c466f 401 printf(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 402 if ((i%16) == 15) {
Soohwan Kim 0:6f28332c466f 403 printf("\n");
Soohwan Kim 0:6f28332c466f 404 }
Soohwan Kim 0:6f28332c466f 405 }
Soohwan Kim 0:6f28332c466f 406 printf("\n");
Soohwan Kim 0:6f28332c466f 407 }
Soohwan Kim 0:6f28332c466f 408
Soohwan Kim 0:6f28332c466f 409 void debug_hex(uint8_t* buf, int len)
Soohwan Kim 0:6f28332c466f 410 {
Soohwan Kim 0:6f28332c466f 411 for(int i = 0; i < len; i++) {
Soohwan Kim 0:6f28332c466f 412 if ((i%16) == 0) {
Soohwan Kim 0:6f28332c466f 413 debug("%p", buf+i);
Soohwan Kim 0:6f28332c466f 414 }
Soohwan Kim 0:6f28332c466f 415 debug(" %02x", buf[i]);
Soohwan Kim 0:6f28332c466f 416 if ((i%16) == 15) {
Soohwan Kim 0:6f28332c466f 417 debug("\n");
Soohwan Kim 0:6f28332c466f 418 }
Soohwan Kim 0:6f28332c466f 419 }
Soohwan Kim 0:6f28332c466f 420 debug("\n");
Soohwan Kim 0:6f28332c466f 421 }
Soohwan Kim 0:6f28332c466f 422
Soohwan Kim 0:6f28332c466f 423 void WIZnet_Chip::scmd(int socket, Command cmd)
Soohwan Kim 0:6f28332c466f 424 {
Soohwan Kim 0:6f28332c466f 425 sreg<uint8_t>(socket, Sn_CR, cmd);
Soohwan Kim 0:6f28332c466f 426 while(sreg<uint8_t>(socket, Sn_CR));
Soohwan Kim 0:6f28332c466f 427 }
Soohwan Kim 0:6f28332c466f 428
Soohwan Kim 0:6f28332c466f 429
Soohwan Kim 0:6f28332c466f 430 void mdio_init(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin_MDC, uint16_t GPIO_Pin_MDIO)
Soohwan Kim 0:6f28332c466f 431 {
Soohwan Kim 0:6f28332c466f 432 /* Set GPIOs for MDIO and MDC */
Soohwan Kim 0:6f28332c466f 433 GPIO_InitTypeDef MDIO_InitDef;
Soohwan Kim 0:6f28332c466f 434 HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDIO, PAD_AF1);
Soohwan Kim 0:6f28332c466f 435 HAL_PAD_AFConfig(PAD_PB, GPIO_Pin_MDC, PAD_AF1);
Soohwan Kim 0:6f28332c466f 436 MDIO_InitDef.GPIO_Pin = GPIO_Pin_MDC | GPIO_Pin_MDIO;
Soohwan Kim 0:6f28332c466f 437 MDIO_InitDef.GPIO_Mode = GPIO_Mode_OUT;
Soohwan Kim 0:6f28332c466f 438 HAL_GPIO_Init(GPIOx, &MDIO_InitDef);
Soohwan Kim 0:6f28332c466f 439 }
Soohwan Kim 0:6f28332c466f 440
Soohwan Kim 0:6f28332c466f 441 void output_MDIO(GPIO_TypeDef* GPIOx, uint32_t val, uint32_t n)
Soohwan Kim 0:6f28332c466f 442 {
Soohwan Kim 0:6f28332c466f 443 for(val <<= (32-n); n; val<<=1, n--)
Soohwan Kim 0:6f28332c466f 444 {
Soohwan Kim 0:6f28332c466f 445 if(val & 0x80000000)
Soohwan Kim 0:6f28332c466f 446 HAL_GPIO_SetBits(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 447 else
Soohwan Kim 0:6f28332c466f 448 HAL_GPIO_ResetBits(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 449
Soohwan Kim 0:6f28332c466f 450 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 451 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 452 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 453 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 454 }
Soohwan Kim 0:6f28332c466f 455 }
Soohwan Kim 0:6f28332c466f 456
Soohwan Kim 0:6f28332c466f 457 uint32_t input_MDIO( GPIO_TypeDef* GPIOx )
Soohwan Kim 0:6f28332c466f 458 {
Soohwan Kim 0:6f28332c466f 459 uint32_t i, val=0;
Soohwan Kim 0:6f28332c466f 460 for(i=0; i<16; i++)
Soohwan Kim 0:6f28332c466f 461 {
Soohwan Kim 0:6f28332c466f 462 val <<=1;
Soohwan Kim 0:6f28332c466f 463 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 464 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 465 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 466 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 467 val |= HAL_GPIO_ReadInputDataBit(GPIOx, MDIO);
Soohwan Kim 0:6f28332c466f 468 }
Soohwan Kim 0:6f28332c466f 469 return (val);
Soohwan Kim 0:6f28332c466f 470 }
Soohwan Kim 0:6f28332c466f 471
Soohwan Kim 0:6f28332c466f 472 void turnaround_MDIO( GPIO_TypeDef* GPIOx)
Soohwan Kim 0:6f28332c466f 473 {
Soohwan Kim 0:6f28332c466f 474 GPIOx->OUTENCLR = MDIO ;
Soohwan Kim 0:6f28332c466f 475 HAL_GPIO_SetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 476 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 477 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 478 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 479 }
Soohwan Kim 0:6f28332c466f 480
Soohwan Kim 0:6f28332c466f 481 void idle_MDIO( GPIO_TypeDef* GPIOx )
Soohwan Kim 0:6f28332c466f 482 {
Soohwan Kim 0:6f28332c466f 483 GPIOx->OUTENSET = MDIO ;
Soohwan Kim 0:6f28332c466f 484 HAL_GPIO_SetBits(GPIOx,MDC);
Soohwan Kim 0:6f28332c466f 485 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 486 HAL_GPIO_ResetBits(GPIOx, MDC);
Soohwan Kim 0:6f28332c466f 487 wait_ms(MDC_WAIT);
Soohwan Kim 0:6f28332c466f 488 }
Soohwan Kim 0:6f28332c466f 489
Soohwan Kim 0:6f28332c466f 490 uint32_t mdio_read(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr)
Soohwan Kim 0:6f28332c466f 491 {
Soohwan Kim 0:6f28332c466f 492 output_MDIO(GPIOx, 0xFFFFFFFF, 32);
Soohwan Kim 0:6f28332c466f 493 output_MDIO(GPIOx, 0x06, 4);
Soohwan Kim 0:6f28332c466f 494 output_MDIO(GPIOx, PHY_ADDR, 5);
Soohwan Kim 0:6f28332c466f 495 output_MDIO(GPIOx, PhyRegAddr, 5);
Soohwan Kim 0:6f28332c466f 496 turnaround_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 497 uint32_t val = input_MDIO(GPIOx );
Soohwan Kim 0:6f28332c466f 498 idle_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 499 return val;
Soohwan Kim 0:6f28332c466f 500 }
Soohwan Kim 0:6f28332c466f 501
Soohwan Kim 0:6f28332c466f 502 void mdio_write(GPIO_TypeDef* GPIOx, uint32_t PhyRegAddr, uint32_t val)
Soohwan Kim 0:6f28332c466f 503 {
Soohwan Kim 0:6f28332c466f 504 output_MDIO(GPIOx, 0xFFFFFFFF, 32);
Soohwan Kim 0:6f28332c466f 505 output_MDIO(GPIOx, 0x05, 4);
Soohwan Kim 0:6f28332c466f 506 output_MDIO(GPIOx, PHY_ADDR, 5);
Soohwan Kim 0:6f28332c466f 507 output_MDIO(GPIOx, PhyRegAddr, 5);
Soohwan Kim 0:6f28332c466f 508 output_MDIO(GPIOx, 0x02, 2);
Soohwan Kim 0:6f28332c466f 509 output_MDIO(GPIOx, val, 16);
Soohwan Kim 0:6f28332c466f 510 idle_MDIO(GPIOx);
Soohwan Kim 0:6f28332c466f 511 }
Soohwan Kim 0:6f28332c466f 512
embeddist 14:2101ab5ee40f 513 int WIZnet_Chip::ethernet_link(void) {
Soohwan Kim 0:6f28332c466f 514 return ((mdio_read(GPIO_MDC, PHYREG_STATUS)>>SVAL)&0x01);
Soohwan Kim 0:6f28332c466f 515 }
Soohwan Kim 0:6f28332c466f 516
embeddist 14:2101ab5ee40f 517 void WIZnet_Chip::ethernet_set_link(int speed, int duplex) {
Soohwan Kim 0:6f28332c466f 518 uint32_t val=0;
Soohwan Kim 0:6f28332c466f 519 if((speed < 0) || (speed > 1)) {
Soohwan Kim 0:6f28332c466f 520 val = CNTL_AUTONEGO;
Soohwan Kim 0:6f28332c466f 521 } else {
Soohwan Kim 0:6f28332c466f 522 val = ((CNTL_SPEED&(speed<<11))|(CNTL_DUPLEX&(duplex<<7)));
Soohwan Kim 0:6f28332c466f 523 }
Soohwan Kim 0:6f28332c466f 524 mdio_write(GPIO_MDC, PHYREG_CONTROL, val);
Soohwan Kim 0:6f28332c466f 525 }
embeddist 14:2101ab5ee40f 526
embeddist 14:2101ab5ee40f 527 void WIZnet_Chip::reg_rd_mac(uint16_t addr, uint8_t* data)
embeddist 14:2101ab5ee40f 528 {
embeddist 14:2101ab5ee40f 529 data[0] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+3));
embeddist 14:2101ab5ee40f 530 data[1] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+2));
embeddist 14:2101ab5ee40f 531 data[2] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+1));
embeddist 14:2101ab5ee40f 532 data[3] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+0));
embeddist 14:2101ab5ee40f 533 data[4] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+7));
embeddist 14:2101ab5ee40f 534 data[5] = *(volatile uint8_t *)(W7500x_WZTOE_BASE + (uint32_t)(addr+6));
embeddist 14:2101ab5ee40f 535 }
embeddist 14:2101ab5ee40f 536
embeddist 14:2101ab5ee40f 537 void WIZnet_Chip::reg_wr_ip(uint16_t addr, uint8_t cb, const char* ip)
embeddist 14:2101ab5ee40f 538 {
embeddist 14:2101ab5ee40f 539 uint8_t buf[4]={0,};
embeddist 14:2101ab5ee40f 540 uint32_t wr_ip = 0;
embeddist 14:2101ab5ee40f 541 char* p = (char*)ip;
embeddist 14:2101ab5ee40f 542
embeddist 14:2101ab5ee40f 543 for(int i = 0; i < 4; i++) {
embeddist 14:2101ab5ee40f 544 wr_ip = (wr_ip<<8);
embeddist 14:2101ab5ee40f 545 buf[i] = atoi(p);
embeddist 14:2101ab5ee40f 546 wr_ip |= buf[i];
embeddist 14:2101ab5ee40f 547 p = strchr(p, '.');
embeddist 14:2101ab5ee40f 548 if (p == NULL) break;
embeddist 14:2101ab5ee40f 549 p++;
embeddist 14:2101ab5ee40f 550 }
embeddist 14:2101ab5ee40f 551 *(volatile uint32_t *)(W7500x_WZTOE_BASE + (uint32_t)((cb<<16)+addr)) = wr_ip;
embeddist 14:2101ab5ee40f 552 }
embeddist 14:2101ab5ee40f 553
embeddist 14:2101ab5ee40f 554 void WIZnet_Chip::sreg_ip(int socket, uint16_t addr, const char* ip) {
embeddist 14:2101ab5ee40f 555 reg_wr_ip(addr, (uint8_t)(0x01+(socket<<2)), ip);
embeddist 14:2101ab5ee40f 556 }
embeddist 14:2101ab5ee40f 557
Soohwan Kim 0:6f28332c466f 558 #endif
Soohwan Kim 0:6f28332c466f 559