Jerry Bradshaw / Mbed OS HSP_Release

This is a mbed 5.2 Release

Dependencies:   USBDevice

Fork of mbed-os-test by Jerry Bradshaw

HSP/Interfaces/QuadSpiInterface.cpp@0:e4a10ed6eb92, 2016-10-25 (annotated)

Committer:
jbradshaw
Date:
Tue Oct 25 15:22:11 2016 +0000
Revision:
0:e4a10ed6eb92
tewt

Who changed what in which revision?

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jbradshaw 0:e4a10ed6eb92 1 /*******************************************************************************
jbradshaw 0:e4a10ed6eb92 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
jbradshaw 0:e4a10ed6eb92 3 *
jbradshaw 0:e4a10ed6eb92 4 * Permission is hereby granted, free of charge, to any person obtaining a
jbradshaw 0:e4a10ed6eb92 5 * copy of this software and associated documentation files (the "Software"),
jbradshaw 0:e4a10ed6eb92 6 * to deal in the Software without restriction, including without limitation
jbradshaw 0:e4a10ed6eb92 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
jbradshaw 0:e4a10ed6eb92 8 * and/or sell copies of the Software, and to permit persons to whom the
jbradshaw 0:e4a10ed6eb92 9 * Software is furnished to do so, subject to the following conditions:
jbradshaw 0:e4a10ed6eb92 10 *
jbradshaw 0:e4a10ed6eb92 11 * The above copyright notice and this permission notice shall be included
jbradshaw 0:e4a10ed6eb92 12 * in all copies or substantial portions of the Software.
jbradshaw 0:e4a10ed6eb92 13 *
jbradshaw 0:e4a10ed6eb92 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
jbradshaw 0:e4a10ed6eb92 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
jbradshaw 0:e4a10ed6eb92 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
jbradshaw 0:e4a10ed6eb92 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
jbradshaw 0:e4a10ed6eb92 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
jbradshaw 0:e4a10ed6eb92 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
jbradshaw 0:e4a10ed6eb92 20 * OTHER DEALINGS IN THE SOFTWARE.
jbradshaw 0:e4a10ed6eb92 21 *
jbradshaw 0:e4a10ed6eb92 22 * Except as contained in this notice, the name of Maxim Integrated
jbradshaw 0:e4a10ed6eb92 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
jbradshaw 0:e4a10ed6eb92 24 * Products, Inc. Branding Policy.
jbradshaw 0:e4a10ed6eb92 25 *
jbradshaw 0:e4a10ed6eb92 26 * The mere transfer of this software does not imply any licenses
jbradshaw 0:e4a10ed6eb92 27 * of trade secrets, proprietary technology, copyrights, patents,
jbradshaw 0:e4a10ed6eb92 28 * trademarks, maskwork rights, or any other form of intellectual
jbradshaw 0:e4a10ed6eb92 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
jbradshaw 0:e4a10ed6eb92 30 * ownership rights.
jbradshaw 0:e4a10ed6eb92 31 *******************************************************************************
jbradshaw 0:e4a10ed6eb92 32 */
jbradshaw 0:e4a10ed6eb92 33 #include "QuadSpiInterface.h"
jbradshaw 0:e4a10ed6eb92 34
jbradshaw 0:e4a10ed6eb92 35 /**
jbradshaw 0:e4a10ed6eb92 36 * @brief Constructor that accepts pin names for the QUAD SPI interface
jbradshaw 0:e4a10ed6eb92 37 * @param mosi master out slave in pin name
jbradshaw 0:e4a10ed6eb92 38 * @param miso master in slave out pin name
jbradshaw 0:e4a10ed6eb92 39 * @param sclk serial clock pin name
jbradshaw 0:e4a10ed6eb92 40 * @param cs chip select pin name
jbradshaw 0:e4a10ed6eb92 41 */
jbradshaw 0:e4a10ed6eb92 42 QuadSpiInterface::QuadSpiInterface(PinName mosi, PinName miso, PinName sclk,
jbradshaw 0:e4a10ed6eb92 43 PinName cs)
jbradshaw 0:e4a10ed6eb92 44 : spi(mosi, miso, sclk), csPin(cs) {
jbradshaw 0:e4a10ed6eb92 45
jbradshaw 0:e4a10ed6eb92 46 }
jbradshaw 0:e4a10ed6eb92 47
jbradshaw 0:e4a10ed6eb92 48 /**
jbradshaw 0:e4a10ed6eb92 49 * @brief Transmit and recieve QUAD SPI data
jbradshaw 0:e4a10ed6eb92 50 * @param tx_buf pointer to transmit byte buffer
jbradshaw 0:e4a10ed6eb92 51 * @param tx_size number of bytes to transmit
jbradshaw 0:e4a10ed6eb92 52 * @param rx_buf pointer to the recieve buffer
jbradshaw 0:e4a10ed6eb92 53 * @param rx_size number of bytes to recieve
jbradshaw 0:e4a10ed6eb92 54 * @param last flag to indicate if this is the last QUAD SPI transaction for the
jbradshaw 0:e4a10ed6eb92 55 * current chip select cycle
jbradshaw 0:e4a10ed6eb92 56 */
jbradshaw 0:e4a10ed6eb92 57 int QuadSpiInterface::SPI_Transmit(const uint8_t *tx_buf, uint32_t tx_size,
jbradshaw 0:e4a10ed6eb92 58 uint8_t *rx_buf, uint32_t rx_size,
jbradshaw 0:e4a10ed6eb92 59 int last) {
jbradshaw 0:e4a10ed6eb92 60 uint32_t i;
jbradshaw 0:e4a10ed6eb92 61 int result = 0;
jbradshaw 0:e4a10ed6eb92 62 int index = 0;
jbradshaw 0:e4a10ed6eb92 63 // lower chip select
jbradshaw 0:e4a10ed6eb92 64 csPin = 0;
jbradshaw 0:e4a10ed6eb92 65 // write bytes out QUAD SPI
jbradshaw 0:e4a10ed6eb92 66 spi.setQuadMode();
jbradshaw 0:e4a10ed6eb92 67 for (i = 0; i < tx_size; i++) {
jbradshaw 0:e4a10ed6eb92 68 rx_buf[index] = spi.write((int)tx_buf[i]);
jbradshaw 0:e4a10ed6eb92 69 index++;
jbradshaw 0:e4a10ed6eb92 70 }
jbradshaw 0:e4a10ed6eb92 71 // read in bytes from QUAD SPI
jbradshaw 0:e4a10ed6eb92 72 for (i = 0; i < rx_size; i++) {
jbradshaw 0:e4a10ed6eb92 73 rx_buf[index] = (uint8_t)spi.read();
jbradshaw 0:e4a10ed6eb92 74 index++;
jbradshaw 0:e4a10ed6eb92 75 }
jbradshaw 0:e4a10ed6eb92 76 // raise chip select if this is the last transaction
jbradshaw 0:e4a10ed6eb92 77 if (last) csPin = 1;
jbradshaw 0:e4a10ed6eb92 78 return result;
jbradshaw 0:e4a10ed6eb92 79 }
jbradshaw 0:e4a10ed6eb92 80
jbradshaw 0:e4a10ed6eb92 81 /**
jbradshaw 0:e4a10ed6eb92 82 * @brief Transmit and recieve QUAD SPI data
jbradshaw 0:e4a10ed6eb92 83 * @param tx_buf pointer to transmit byte buffer
jbradshaw 0:e4a10ed6eb92 84 * @param tx_size number of bytes to transmit
jbradshaw 0:e4a10ed6eb92 85 * @param rx_buf pointer to the recieve buffer
jbradshaw 0:e4a10ed6eb92 86 * @param rx_size number of bytes to recieve
jbradshaw 0:e4a10ed6eb92 87 * @param last flag to indicate if this is the last QUAD SPI transaction for the
jbradshaw 0:e4a10ed6eb92 88 * current chip select cycle
jbradshaw 0:e4a10ed6eb92 89 */
jbradshaw 0:e4a10ed6eb92 90 int QuadSpiInterface::SPI_Transmit4Wire(const uint8_t *tx_buf, uint32_t tx_size,
jbradshaw 0:e4a10ed6eb92 91 uint8_t *rx_buf, uint32_t rx_size,
jbradshaw 0:e4a10ed6eb92 92 int last) {
jbradshaw 0:e4a10ed6eb92 93 uint32_t i;
jbradshaw 0:e4a10ed6eb92 94 int result = 0;
jbradshaw 0:e4a10ed6eb92 95 int index = 0;
jbradshaw 0:e4a10ed6eb92 96 // lower chip select
jbradshaw 0:e4a10ed6eb92 97 csPin = 0;
jbradshaw 0:e4a10ed6eb92 98 // write bytes out Single SPI
jbradshaw 0:e4a10ed6eb92 99 spi.setSingleMode();
jbradshaw 0:e4a10ed6eb92 100 for (i = 0; i < tx_size; i++) {
jbradshaw 0:e4a10ed6eb92 101 rx_buf[index] = spi.write((int)tx_buf[i]);
jbradshaw 0:e4a10ed6eb92 102 index++;
jbradshaw 0:e4a10ed6eb92 103 }
jbradshaw 0:e4a10ed6eb92 104 // raise chip select if this is the last transaction
jbradshaw 0:e4a10ed6eb92 105 if (last) csPin = 1;
jbradshaw 0:e4a10ed6eb92 106 return result;
jbradshaw 0:e4a10ed6eb92 107 }