Forked version of the FXOS8700CQ library which maintains its own memory
Dependents: fxos8700cq_example
Fork of FXOS8700CQ by
FXOS8700CQ.cpp@5:2bd683278d23, 2017-03-02 (annotated)
- Committer:
- janjongboom
- Date:
- Thu Mar 02 17:12:06 2017 +0000
- Revision:
- 5:2bd683278d23
- Parent:
- 2:4c2f8a3549a9
The library should maintain its own memory
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
trm | 0:cf6299acfe98 | 1 | #include "FXOS8700CQ.h" |
trm | 0:cf6299acfe98 | 2 | |
trm | 0:cf6299acfe98 | 3 | uint8_t status_reg; // Status register contents |
trm | 0:cf6299acfe98 | 4 | uint8_t raw[FXOS8700CQ_READ_LEN]; // Buffer for reading out stored data |
trm | 0:cf6299acfe98 | 5 | |
trm | 0:cf6299acfe98 | 6 | // Construct class and its contents |
trm | 0:cf6299acfe98 | 7 | FXOS8700CQ::FXOS8700CQ(PinName sda, PinName scl, int addr) : dev_i2c(sda, scl), dev_addr(addr) |
trm | 0:cf6299acfe98 | 8 | { |
janjongboom | 5:2bd683278d23 | 9 | accel_data = new SRAWDATA(); |
janjongboom | 5:2bd683278d23 | 10 | magn_data = new SRAWDATA(); |
janjongboom | 5:2bd683278d23 | 11 | |
trm | 0:cf6299acfe98 | 12 | // Initialization of the FXOS8700CQ |
trm | 0:cf6299acfe98 | 13 | dev_i2c.frequency(I2C_400K); // Use maximum I2C frequency |
trm | 0:cf6299acfe98 | 14 | uint8_t data[6] = {0, 0, 0, 0, 0, 0}; // target device write address, single byte to write at address |
trm | 0:cf6299acfe98 | 15 | |
trm | 0:cf6299acfe98 | 16 | // TODO: verify WHOAMI? |
trm | 2:4c2f8a3549a9 | 17 | |
trm | 0:cf6299acfe98 | 18 | // TODO: un-magic-number register configuration |
trm | 0:cf6299acfe98 | 19 | |
trm | 0:cf6299acfe98 | 20 | // Place peripheral in standby for configuration, resetting CTRL_REG1 |
trm | 0:cf6299acfe98 | 21 | data[0] = FXOS8700CQ_CTRL_REG1; |
trm | 2:4c2f8a3549a9 | 22 | data[1] = 0x00; // this will unset CTRL_REG1:active |
trm | 0:cf6299acfe98 | 23 | write_regs(data, 2); |
trm | 0:cf6299acfe98 | 24 | |
trm | 0:cf6299acfe98 | 25 | // Now that the device is in standby, configure registers |
trm | 0:cf6299acfe98 | 26 | |
trm | 0:cf6299acfe98 | 27 | // Setup for write-though for CTRL_REG series |
trm | 0:cf6299acfe98 | 28 | // Keep data[0] as FXOS8700CQ_CTRL_REG1 |
trm | 2:4c2f8a3549a9 | 29 | data[1] = |
trm | 2:4c2f8a3549a9 | 30 | FXOS8700CQ_CTRL_REG1_ASLP_RATE2(1) | // 0b01 gives sleep rate of 12.5Hz |
trm | 2:4c2f8a3549a9 | 31 | FXOS8700CQ_CTRL_REG1_DR3(1); // 0x001 gives ODR of 400Hz/200Hz hybrid |
trm | 0:cf6299acfe98 | 32 | |
trm | 0:cf6299acfe98 | 33 | // FXOS8700CQ_CTRL_REG2; |
trm | 2:4c2f8a3549a9 | 34 | data[2] = |
trm | 2:4c2f8a3549a9 | 35 | FXOS8700CQ_CTRL_REG2_SMODS2(3) | // 0b11 gives low power sleep oversampling mode |
trm | 2:4c2f8a3549a9 | 36 | FXOS8700CQ_CTRL_REG2_MODS2(1); // 0b01 gives low noise, low power oversampling mode |
trm | 0:cf6299acfe98 | 37 | |
trm | 0:cf6299acfe98 | 38 | // No configuration changes from default 0x00 in CTRL_REG3 |
trm | 0:cf6299acfe98 | 39 | // Interrupts will be active low |
trm | 0:cf6299acfe98 | 40 | data[3] = 0x00; |
trm | 0:cf6299acfe98 | 41 | |
trm | 0:cf6299acfe98 | 42 | // FXOS8700CQ_CTRL_REG4; |
trm | 2:4c2f8a3549a9 | 43 | data[4] = |
trm | 2:4c2f8a3549a9 | 44 | FXOS8700CQ_CTRL_REG4_INT_EN_DRDY; |
trm | 0:cf6299acfe98 | 45 | |
trm | 0:cf6299acfe98 | 46 | // No configuration changes from default 0x00 in CTRL_REG5 |
trm | 0:cf6299acfe98 | 47 | // Data ready interrupt will appear on INT2 |
trm | 0:cf6299acfe98 | 48 | data[5] = 0x00; |
trm | 0:cf6299acfe98 | 49 | |
trm | 0:cf6299acfe98 | 50 | // Write to the 5 CTRL_REG registers |
trm | 0:cf6299acfe98 | 51 | write_regs(data, 6); |
trm | 0:cf6299acfe98 | 52 | |
trm | 2:4c2f8a3549a9 | 53 | // FXOS8700CQ_XYZ_DATA_CFG |
trm | 2:4c2f8a3549a9 | 54 | data[0] = FXOS8700CQ_XYZ_DATA_CFG; |
trm | 2:4c2f8a3549a9 | 55 | data[1] = |
trm | 2:4c2f8a3549a9 | 56 | FXOS8700CQ_XYZ_DATA_CFG_FS2(1); // 0x01 gives 4g full range, 0.488mg/LSB |
trm | 2:4c2f8a3549a9 | 57 | write_regs(data, 2); |
trm | 0:cf6299acfe98 | 58 | |
trm | 0:cf6299acfe98 | 59 | // Setup for write-through for M_CTRL_REG series |
trm | 0:cf6299acfe98 | 60 | data[0] = FXOS8700CQ_M_CTRL_REG1; |
trm | 2:4c2f8a3549a9 | 61 | data[1] = |
trm | 2:4c2f8a3549a9 | 62 | FXOS8700CQ_M_CTRL_REG1_M_ACAL | // set automatic calibration |
trm | 2:4c2f8a3549a9 | 63 | FXOS8700CQ_M_CTRL_REG1_MO_OS3(7) | // use maximum magnetic oversampling |
trm | 2:4c2f8a3549a9 | 64 | FXOS8700CQ_M_CTRL_REG1_M_HMS2(3); // enable hybrid sampling (both sensors) |
trm | 0:cf6299acfe98 | 65 | |
trm | 0:cf6299acfe98 | 66 | // FXOS8700CQ_M_CTRL_REG2 |
trm | 2:4c2f8a3549a9 | 67 | data[2] = |
trm | 2:4c2f8a3549a9 | 68 | FXOS8700CQ_M_CTRL_REG2_HYB_AUTOINC_MODE; |
trm | 0:cf6299acfe98 | 69 | |
trm | 0:cf6299acfe98 | 70 | // FXOS8700CQ_M_CTRL_REG3 |
trm | 2:4c2f8a3549a9 | 71 | data[3] = |
trm | 2:4c2f8a3549a9 | 72 | FXOS8700CQ_M_CTRL_REG3_M_ASLP_OS3(7); // maximum sleep magnetic oversampling |
trm | 0:cf6299acfe98 | 73 | |
trm | 0:cf6299acfe98 | 74 | // Write to the 3 M_CTRL_REG registers |
trm | 0:cf6299acfe98 | 75 | write_regs(data, 4); |
trm | 0:cf6299acfe98 | 76 | |
trm | 0:cf6299acfe98 | 77 | // Peripheral is configured, but disabled |
trm | 2:4c2f8a3549a9 | 78 | enabled = false; |
trm | 0:cf6299acfe98 | 79 | } |
trm | 0:cf6299acfe98 | 80 | |
trm | 0:cf6299acfe98 | 81 | // Destruct class |
janjongboom | 5:2bd683278d23 | 82 | FXOS8700CQ::~FXOS8700CQ(void) { |
janjongboom | 5:2bd683278d23 | 83 | if (accel_data) delete accel_data; |
janjongboom | 5:2bd683278d23 | 84 | if (magn_data) delete magn_data; |
janjongboom | 5:2bd683278d23 | 85 | } |
trm | 0:cf6299acfe98 | 86 | |
trm | 0:cf6299acfe98 | 87 | |
trm | 0:cf6299acfe98 | 88 | void FXOS8700CQ::enable(void) |
trm | 0:cf6299acfe98 | 89 | { |
trm | 0:cf6299acfe98 | 90 | uint8_t data[2]; |
trm | 0:cf6299acfe98 | 91 | read_regs( FXOS8700CQ_CTRL_REG1, &data[1], 1); |
trm | 2:4c2f8a3549a9 | 92 | data[1] |= FXOS8700CQ_CTRL_REG1_ACTIVE; |
trm | 0:cf6299acfe98 | 93 | data[0] = FXOS8700CQ_CTRL_REG1; |
trm | 0:cf6299acfe98 | 94 | write_regs(data, 2); // write back |
trm | 2:4c2f8a3549a9 | 95 | |
trm | 2:4c2f8a3549a9 | 96 | enabled = true; |
trm | 0:cf6299acfe98 | 97 | } |
trm | 0:cf6299acfe98 | 98 | |
trm | 0:cf6299acfe98 | 99 | void FXOS8700CQ::disable(void) |
trm | 0:cf6299acfe98 | 100 | { |
trm | 0:cf6299acfe98 | 101 | uint8_t data[2]; |
trm | 0:cf6299acfe98 | 102 | read_regs( FXOS8700CQ_CTRL_REG1, &data[1], 1); |
trm | 0:cf6299acfe98 | 103 | data[0] = FXOS8700CQ_CTRL_REG1; |
trm | 2:4c2f8a3549a9 | 104 | data[1] &= ~FXOS8700CQ_CTRL_REG1_ACTIVE; |
trm | 0:cf6299acfe98 | 105 | write_regs(data, 2); // write back |
trm | 2:4c2f8a3549a9 | 106 | |
trm | 2:4c2f8a3549a9 | 107 | enabled = false; |
trm | 0:cf6299acfe98 | 108 | } |
trm | 0:cf6299acfe98 | 109 | |
trm | 0:cf6299acfe98 | 110 | |
trm | 0:cf6299acfe98 | 111 | uint8_t FXOS8700CQ::status(void) |
trm | 0:cf6299acfe98 | 112 | { |
trm | 0:cf6299acfe98 | 113 | read_regs(FXOS8700CQ_STATUS, &status_reg, 1); |
trm | 0:cf6299acfe98 | 114 | return status_reg; |
trm | 0:cf6299acfe98 | 115 | } |
trm | 0:cf6299acfe98 | 116 | |
trm | 0:cf6299acfe98 | 117 | uint8_t FXOS8700CQ::get_whoami(void) |
trm | 0:cf6299acfe98 | 118 | { |
trm | 0:cf6299acfe98 | 119 | uint8_t databyte = 0x00; |
trm | 0:cf6299acfe98 | 120 | read_regs(FXOS8700CQ_WHOAMI, &databyte, 1); |
trm | 0:cf6299acfe98 | 121 | return databyte; |
trm | 0:cf6299acfe98 | 122 | } |
trm | 0:cf6299acfe98 | 123 | |
janjongboom | 5:2bd683278d23 | 124 | uint8_t FXOS8700CQ::get_data() |
trm | 0:cf6299acfe98 | 125 | { |
trm | 2:4c2f8a3549a9 | 126 | if(!enabled) { |
trm | 2:4c2f8a3549a9 | 127 | return 1; |
trm | 2:4c2f8a3549a9 | 128 | } |
trm | 2:4c2f8a3549a9 | 129 | |
trm | 2:4c2f8a3549a9 | 130 | read_regs(FXOS8700CQ_M_OUT_X_MSB, raw, FXOS8700CQ_READ_LEN); |
trm | 0:cf6299acfe98 | 131 | |
trm | 0:cf6299acfe98 | 132 | // Pull out 16-bit, 2's complement magnetometer data |
trm | 0:cf6299acfe98 | 133 | magn_data->x = (raw[0] << 8) | raw[1]; |
trm | 0:cf6299acfe98 | 134 | magn_data->y = (raw[2] << 8) | raw[3]; |
trm | 0:cf6299acfe98 | 135 | magn_data->z = (raw[4] << 8) | raw[5]; |
trm | 0:cf6299acfe98 | 136 | |
trm | 0:cf6299acfe98 | 137 | // Pull out 14-bit, 2's complement, right-justified accelerometer data |
trm | 0:cf6299acfe98 | 138 | accel_data->x = (raw[6] << 8) | raw[7]; |
trm | 0:cf6299acfe98 | 139 | accel_data->y = (raw[8] << 8) | raw[9]; |
trm | 0:cf6299acfe98 | 140 | accel_data->z = (raw[10] << 8) | raw[11]; |
trm | 2:4c2f8a3549a9 | 141 | |
trm | 2:4c2f8a3549a9 | 142 | // Have to apply corrections to make the int16_t correct |
trm | 2:4c2f8a3549a9 | 143 | if(accel_data->x > UINT14_MAX/2) { |
trm | 2:4c2f8a3549a9 | 144 | accel_data->x -= UINT14_MAX; |
trm | 2:4c2f8a3549a9 | 145 | } |
trm | 2:4c2f8a3549a9 | 146 | if(accel_data->y > UINT14_MAX/2) { |
trm | 2:4c2f8a3549a9 | 147 | accel_data->y -= UINT14_MAX; |
trm | 2:4c2f8a3549a9 | 148 | } |
trm | 2:4c2f8a3549a9 | 149 | if(accel_data->z > UINT14_MAX/2) { |
trm | 2:4c2f8a3549a9 | 150 | accel_data->z -= UINT14_MAX; |
trm | 2:4c2f8a3549a9 | 151 | } |
trm | 2:4c2f8a3549a9 | 152 | |
trm | 2:4c2f8a3549a9 | 153 | return 0; |
trm | 0:cf6299acfe98 | 154 | } |
trm | 0:cf6299acfe98 | 155 | |
janjongboom | 5:2bd683278d23 | 156 | int16_t FXOS8700CQ::getAccelX() { return accel_data->x; } |
janjongboom | 5:2bd683278d23 | 157 | int16_t FXOS8700CQ::getAccelY() { return accel_data->y; } |
janjongboom | 5:2bd683278d23 | 158 | int16_t FXOS8700CQ::getAccelZ() { return accel_data->z; } |
janjongboom | 5:2bd683278d23 | 159 | |
janjongboom | 5:2bd683278d23 | 160 | int16_t FXOS8700CQ::getMagnetX() { return magn_data->x; } |
janjongboom | 5:2bd683278d23 | 161 | int16_t FXOS8700CQ::getMagnetY() { return magn_data->y; } |
janjongboom | 5:2bd683278d23 | 162 | int16_t FXOS8700CQ::getMagnetZ() { return magn_data->z; } |
janjongboom | 5:2bd683278d23 | 163 | |
trm | 2:4c2f8a3549a9 | 164 | uint8_t FXOS8700CQ::get_accel_scale(void) |
trm | 2:4c2f8a3549a9 | 165 | { |
trm | 2:4c2f8a3549a9 | 166 | uint8_t data = 0x00; |
trm | 2:4c2f8a3549a9 | 167 | read_regs(FXOS8700CQ_XYZ_DATA_CFG, &data, 1); |
trm | 2:4c2f8a3549a9 | 168 | data &= FXOS8700CQ_XYZ_DATA_CFG_FS2(3); // mask with 0b11 |
trm | 2:4c2f8a3549a9 | 169 | |
trm | 2:4c2f8a3549a9 | 170 | switch(data) { |
trm | 2:4c2f8a3549a9 | 171 | case FXOS8700CQ_XYZ_DATA_CFG_FS2(0): |
trm | 2:4c2f8a3549a9 | 172 | return 2; |
trm | 2:4c2f8a3549a9 | 173 | case FXOS8700CQ_XYZ_DATA_CFG_FS2(1): |
trm | 2:4c2f8a3549a9 | 174 | return 4; |
trm | 2:4c2f8a3549a9 | 175 | case FXOS8700CQ_XYZ_DATA_CFG_FS2(2): |
trm | 2:4c2f8a3549a9 | 176 | return 8; |
trm | 2:4c2f8a3549a9 | 177 | default: |
trm | 2:4c2f8a3549a9 | 178 | return 0; |
trm | 2:4c2f8a3549a9 | 179 | } |
trm | 2:4c2f8a3549a9 | 180 | } |
trm | 0:cf6299acfe98 | 181 | |
trm | 0:cf6299acfe98 | 182 | // Private methods |
trm | 0:cf6299acfe98 | 183 | |
trm | 0:cf6299acfe98 | 184 | void FXOS8700CQ::read_regs(int reg_addr, uint8_t* data, int len) |
trm | 0:cf6299acfe98 | 185 | { |
trm | 0:cf6299acfe98 | 186 | char t[1] = {reg_addr}; |
trm | 0:cf6299acfe98 | 187 | dev_i2c.write(dev_addr, t, 1, true); |
trm | 0:cf6299acfe98 | 188 | dev_i2c.read(dev_addr, (char *)data, len); |
trm | 0:cf6299acfe98 | 189 | } |
trm | 0:cf6299acfe98 | 190 | |
trm | 0:cf6299acfe98 | 191 | void FXOS8700CQ::write_regs(uint8_t* data, int len) |
trm | 0:cf6299acfe98 | 192 | { |
trm | 0:cf6299acfe98 | 193 | dev_i2c.write(dev_addr, (char*)data, len); |
trm | 0:cf6299acfe98 | 194 | } |