A web server for monitoring and controlling a MakerBot Replicator over the USB host and ethernet.

Dependencies:   IAP NTPClient RTC mbed-rtos mbed Socket lwip-sys lwip BurstSPI

Fork of LPC1768_Mini-DK by Frank Vannieuwkerke

Makerbot Server for LPC1768 Copyright (c) 2013, jake (at) allaboutjake (dot) com All rights reserved.

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

  • Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
  • Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
  • The name of the author and/or copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER, AUTHOR, OR ANY CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

Warnings:

This is not a commercial product or a hardened and secure network appliance. It is intended as a thought experiment or proof of concept and should not be relied upon in any way. Always operate your 3D printer in a safe and controlled manner.

Do not connect this directly to the exposed internet. It is intended to be behind a secure firewall (and NAT) such that it will only accept commands from the local network. Imagine how much fun a hacker could have instructing your 3D printer to continually print Standford bunnies. Well it could be much worse then that- a malicious user could send commands that could crash your machine (both in the software sense, as well as in the "smash your moving parts against the side of the machine repeatedly sense), overheat your extruders, cause your build plate to catch fire, and do severe damage to the machine, any surrounding building and propery. You have been warned.

Never print unattended and be ready to step in and stop the machine if something goes wrong. Keep in mind, a 3D printer has heaters that are operating at high temperatures, and if something starts to burn, it could cause damage to the machine, other property, and/or hurt yourself, pets, or others.

You should understand what you are doing. The source code here is not intended as a finished product or set of step by step instructions. You should engineer your own solution, which may wind up being better than mine.

Proceed at your own risk. You've been warned. (Several times) If you break your Makerbot, burn your house down, or injure yourself or others, I take no responsibility.

Introduction

I've been working on a side project to solve the "last mile" problem for people wanting to print from the network on their bots. I feel like the first half of the problem is solved with the FlashAir- getting the files to the card. The next step is a lightweight way of sending the "play back capture" command to the bot.

I looked around for a microcontroller platform that supports both networking and can function as a USB host. I happened to have an mbed (mbed) on hand that fit the bill. The mbed also has a working online toolchain (you need to own an mbed to gain access to the compiler). Some people don't like the online development environment, but I'm a fan of "working" and "Mac compatible." It was a good start, but cost wise, you would need an mbed LPC1768 module and some sort of carrier board that has both USB host and ethernet, or rig up your own connector solution. I happened to also have a Seedstudio mbed shield carrier board. This provides ethernet and USB connectors, but is another $25, putting the solution at around $75.

I also had an LPC1768 development board here called the "Mini-DK2". It has a USB host and a wired ethernet connector on board (search ebay if you're interested). It's a single-board solution that costs only $32 (and for $40 you can get one with a touchscreen) Its the cheapest development board I've seen with both USB host and an ethernet connector. I considered RasPi, but I'm not on that bandwagon. Since I had the Mini-DK2 on hand from another project that never went anywhere, I moved from the mbed module and carrier board to the DK2.

The mbed environment can compile binaries that work on the DK2 (again, you need to own at least one 1768 mbed already to get a license to use the compiler), and the mbed libraries provide some nice features. A USB Host library and and Ethernet library were readily available. The USBHost library didn't quite work out of the box. It took some time and more learning about the USB protocols than I would have liked, but I have the board communicating over the USB Host and the Makerbot.

Changes to stock mbed libraries

Many libraries are imported, but then converted to folders as to unlink them.

mbed provides a USHost library that includes a USBHostSerial object for connecting to CDC serial devices. Unfortunately, it did not work for me out of the box. I spent some time learning about USB protocols. One good reference is [Jan Axelson's Lakeview Research](http://www.lvr.com/usb_virtual_com_port.htm) discussion about CDC.

I found that the stock library was sending the control transfers to Interface 1. From what I understand, the control transfers needed to go to interface 0. I modified the USBHostSerial library to correct this, and the serial port interface came to life.

Next, I found that I wasn't able to get reliable communication. I traced it to what I think is an odd C++ inheritance and override problem. The USBHostSerial class implements the Stream interface, allowing printf/scanf operations. This is done by overriding the virtual _getc and _putc methods. Unfortunately, and for a reason I can't understand, these methods were not being called consistently. Sometimes they would work, but other times they would not. My solution was to implement transmit/receive methods with different names, and since the names were different, they seemed to get called consistently. I'd like to learn exactly what's going on here, but I don't feel like debugging it for academic purposes when it works just fine with the added methods.

Usage

Connect up your chosen dev board to power, ethernet and the USB host to the Makerbot's USB cable. The Mini-DK uses a USB-OTG adapter for the USB host. If you're using a Mini-DK board with an LCD, it will inform you of it's IP address on the display. This means it is now listening for a connection on port 7654.

If you are using an mbed dev board, or a Mini-DK without a display, the message will be directed to the serial console. Connect your computer to the appropriate port at a baud rate of 115200 to see the messages.

Use a telnet client to connect to the given IP address at port 7654. Telnet clients typically revert to "line mode" on ports other than 21. This means you get a local echo and the command isn't sent until you press enter.

Once connected, you can send the following commands:

A <username>:<password> : Set a username & password for the web interface and the telnet interface. Use the format shown with a colon separating the username from the password.

V : Print the version and Makerbot name, as well as the local firmware version (the Makerbot_Server firmware as discussed here).

B <filename.x3g> : Build from SD the given filename. According tot he protocol spec, this command is limited to 12 characters, so 8.3 filenames only.

P : Pause an active build

R : Resume active build

C : Cancel build- note that this immediately halts the build and does not clear the build area. You might want to pause the build first, and then cancel shortly after to make sure the nozzle isn't left hot and in contact with a printed part.

S : Print build status, tool and platform temps

Q : Quit and logout

The Mini-DK has two onboard buttons (besides the ISP and reset buttons). Currently one button will trigger a pause (if the Makerbot is printing) and the other will resume (if the Makerbot it paused)

Compiling

Edit "Target.h" to set whether you're building for an MBED module or the Mini-DK2

Installation

If you are using a mbed, then you can simply load the BIN file to the mbed using the mass storage bootloader. The mbed mounts as if it were a USB thumbdrive, and you copy the BIN file to the drive. After a reset, you're running the installed firmware.

The MiniDK has a serial bootloader. You connect to this bootloader from the "top" USB connector (not the USB host one). Hold down the ISP button and then tap the reset button and then release the ISP button to put it into programming mode. I use [lpc21isp](http://sourceforge.net/projects/lpc21isp/) to load the binary. The other option is FlashMagic, which uses HEX files, so you'll need to use some sort of bin2hex utility to convert the firmware file if you use this utility. I can't really say if/how this works, as I don't use this method. See this (http://mbed.org/users/frankvnk/notebook/lpc1768-mini-dk/) for more info.

Credits

Some credits, where credit is due.

EthernetInterface - modified to include PHY code for both the MiniDK2 and MBED based on selected #definitions

Mini-DK - Thanks for Frank and Erik for doing all the heavy lifting getting the MBED compiler and libraries and peripherals working on the Mini-DK2

NTP Client - Thanks to Donatien for this library to set the clock over the network

RTC - Thanks to Erik for the RTC library. I've got it in my project, but I don't think I'm using it for anything (yet).

SimpleSocket - Thanks to Yamaguchi-san. Modified slightly to take out references to EthernetInterface::init() and ::getIPAddress(). For some reason these don't like to be called in a thread.

JPEGCamera - Thanks again to Yamaguchi-san. Modified to output the JPEG binary over a socket rather than to a file descriptor.

USBHost - modified as noted above

IAP - Thanks to Okano-san. Pulled out of the Mini-DK folder so that I could link it back to the base repository at the root level.

Committer:
jakeb
Date:
Fri Aug 23 21:45:08 2013 +0000
Revision:
15:688b3e3958fd
Initial commit of software v0.2;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
jakeb 15:688b3e3958fd 1 /**********************************************************************
jakeb 15:688b3e3958fd 2 * $Id$ lpc17xx_emac.h 2010-05-21
jakeb 15:688b3e3958fd 3 *//**
jakeb 15:688b3e3958fd 4 * @file lpc17xx_emac.h
jakeb 15:688b3e3958fd 5 * @brief Contains all macro definitions and function prototypes
jakeb 15:688b3e3958fd 6 * support for Ethernet MAC firmware library on LPC17xx
jakeb 15:688b3e3958fd 7 * @version 2.0
jakeb 15:688b3e3958fd 8 * @date 21. May. 2010
jakeb 15:688b3e3958fd 9 * @author NXP MCU SW Application Team
jakeb 15:688b3e3958fd 10 *
jakeb 15:688b3e3958fd 11 * Copyright(C) 2010, NXP Semiconductor
jakeb 15:688b3e3958fd 12 * All rights reserved.
jakeb 15:688b3e3958fd 13 *
jakeb 15:688b3e3958fd 14 ***********************************************************************
jakeb 15:688b3e3958fd 15 * Software that is described herein is for illustrative purposes only
jakeb 15:688b3e3958fd 16 * which provides customers with programming information regarding the
jakeb 15:688b3e3958fd 17 * products. This software is supplied "AS IS" without any warranties.
jakeb 15:688b3e3958fd 18 * NXP Semiconductors assumes no responsibility or liability for the
jakeb 15:688b3e3958fd 19 * use of the software, conveys no license or title under any patent,
jakeb 15:688b3e3958fd 20 * copyright, or mask work right to the product. NXP Semiconductors
jakeb 15:688b3e3958fd 21 * reserves the right to make changes in the software without
jakeb 15:688b3e3958fd 22 * notification. NXP Semiconductors also make no representation or
jakeb 15:688b3e3958fd 23 * warranty that such application will be suitable for the specified
jakeb 15:688b3e3958fd 24 * use without further testing or modification.
jakeb 15:688b3e3958fd 25 **********************************************************************/
jakeb 15:688b3e3958fd 26
jakeb 15:688b3e3958fd 27 /* Peripheral group ----------------------------------------------------------- */
jakeb 15:688b3e3958fd 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
jakeb 15:688b3e3958fd 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
jakeb 15:688b3e3958fd 30 * @{
jakeb 15:688b3e3958fd 31 */
jakeb 15:688b3e3958fd 32
jakeb 15:688b3e3958fd 33 #ifndef LPC17XX_EMAC_H_
jakeb 15:688b3e3958fd 34 #define LPC17XX_EMAC_H_
jakeb 15:688b3e3958fd 35
jakeb 15:688b3e3958fd 36 /* Includes ------------------------------------------------------------------- */
jakeb 15:688b3e3958fd 37 #include "LPC17xx.h"
jakeb 15:688b3e3958fd 38
jakeb 15:688b3e3958fd 39 #ifdef __cplusplus
jakeb 15:688b3e3958fd 40 extern "C"
jakeb 15:688b3e3958fd 41 {
jakeb 15:688b3e3958fd 42 #endif
jakeb 15:688b3e3958fd 43
jakeb 15:688b3e3958fd 44 #define MCB_LPC_1768
jakeb 15:688b3e3958fd 45 //#define IAR_LPC_1768
jakeb 15:688b3e3958fd 46
jakeb 15:688b3e3958fd 47 /* Public Macros -------------------------------------------------------------- */
jakeb 15:688b3e3958fd 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
jakeb 15:688b3e3958fd 49 * @{
jakeb 15:688b3e3958fd 50 */
jakeb 15:688b3e3958fd 51
jakeb 15:688b3e3958fd 52
jakeb 15:688b3e3958fd 53 /* EMAC PHY status type definitions */
jakeb 15:688b3e3958fd 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
jakeb 15:688b3e3958fd 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
jakeb 15:688b3e3958fd 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
jakeb 15:688b3e3958fd 57
jakeb 15:688b3e3958fd 58 /* EMAC PHY device Speed definitions */
jakeb 15:688b3e3958fd 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
jakeb 15:688b3e3958fd 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
jakeb 15:688b3e3958fd 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
jakeb 15:688b3e3958fd 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
jakeb 15:688b3e3958fd 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
jakeb 15:688b3e3958fd 64
jakeb 15:688b3e3958fd 65 /**
jakeb 15:688b3e3958fd 66 * @}
jakeb 15:688b3e3958fd 67 */
jakeb 15:688b3e3958fd 68 /* Private Macros ------------------------------------------------------------- */
jakeb 15:688b3e3958fd 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
jakeb 15:688b3e3958fd 70 * @{
jakeb 15:688b3e3958fd 71 */
jakeb 15:688b3e3958fd 72
jakeb 15:688b3e3958fd 73
jakeb 15:688b3e3958fd 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
jakeb 15:688b3e3958fd 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
jakeb 15:688b3e3958fd 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
jakeb 15:688b3e3958fd 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
jakeb 15:688b3e3958fd 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
jakeb 15:688b3e3958fd 79
jakeb 15:688b3e3958fd 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
jakeb 15:688b3e3958fd 81 /*********************************************************************//**
jakeb 15:688b3e3958fd 82 * Macro defines for MAC Configuration Register 1
jakeb 15:688b3e3958fd 83 **********************************************************************/
jakeb 15:688b3e3958fd 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
jakeb 15:688b3e3958fd 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
jakeb 15:688b3e3958fd 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
jakeb 15:688b3e3958fd 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
jakeb 15:688b3e3958fd 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
jakeb 15:688b3e3958fd 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
jakeb 15:688b3e3958fd 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
jakeb 15:688b3e3958fd 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
jakeb 15:688b3e3958fd 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
jakeb 15:688b3e3958fd 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
jakeb 15:688b3e3958fd 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
jakeb 15:688b3e3958fd 95
jakeb 15:688b3e3958fd 96 /*********************************************************************//**
jakeb 15:688b3e3958fd 97 * Macro defines for MAC Configuration Register 2
jakeb 15:688b3e3958fd 98 **********************************************************************/
jakeb 15:688b3e3958fd 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
jakeb 15:688b3e3958fd 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
jakeb 15:688b3e3958fd 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
jakeb 15:688b3e3958fd 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
jakeb 15:688b3e3958fd 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
jakeb 15:688b3e3958fd 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
jakeb 15:688b3e3958fd 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
jakeb 15:688b3e3958fd 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
jakeb 15:688b3e3958fd 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
jakeb 15:688b3e3958fd 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
jakeb 15:688b3e3958fd 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
jakeb 15:688b3e3958fd 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
jakeb 15:688b3e3958fd 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
jakeb 15:688b3e3958fd 112
jakeb 15:688b3e3958fd 113 /*********************************************************************//**
jakeb 15:688b3e3958fd 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
jakeb 15:688b3e3958fd 115 **********************************************************************/
jakeb 15:688b3e3958fd 116 /** Programmable field representing the nibble time offset of the minimum possible period
jakeb 15:688b3e3958fd 117 * between the end of any transmitted packet to the beginning of the next */
jakeb 15:688b3e3958fd 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
jakeb 15:688b3e3958fd 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
jakeb 15:688b3e3958fd 120 * offset of the minimum possible period between the end of any transmitted packet to the
jakeb 15:688b3e3958fd 121 * beginning of the next */
jakeb 15:688b3e3958fd 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
jakeb 15:688b3e3958fd 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
jakeb 15:688b3e3958fd 124 * offset of the minimum possible period between the end of any transmitted packet to the
jakeb 15:688b3e3958fd 125 * beginning of the next */
jakeb 15:688b3e3958fd 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
jakeb 15:688b3e3958fd 127
jakeb 15:688b3e3958fd 128 /*********************************************************************//**
jakeb 15:688b3e3958fd 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
jakeb 15:688b3e3958fd 130 **********************************************************************/
jakeb 15:688b3e3958fd 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
jakeb 15:688b3e3958fd 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
jakeb 15:688b3e3958fd 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
jakeb 15:688b3e3958fd 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
jakeb 15:688b3e3958fd 135 /** Programmable field representing the optional carrierSense window referenced in
jakeb 15:688b3e3958fd 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
jakeb 15:688b3e3958fd 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
jakeb 15:688b3e3958fd 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
jakeb 15:688b3e3958fd 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
jakeb 15:688b3e3958fd 140
jakeb 15:688b3e3958fd 141 /*********************************************************************//**
jakeb 15:688b3e3958fd 142 * Macro defines for Collision Window/Retry Register
jakeb 15:688b3e3958fd 143 **********************************************************************/
jakeb 15:688b3e3958fd 144 /** Programmable field specifying the number of retransmission attempts following a collision before
jakeb 15:688b3e3958fd 145 * aborting the packet due to excessive collisions */
jakeb 15:688b3e3958fd 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
jakeb 15:688b3e3958fd 147 /** Programmable field representing the slot time or collision window during which collisions occur
jakeb 15:688b3e3958fd 148 * in properly configured networks */
jakeb 15:688b3e3958fd 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
jakeb 15:688b3e3958fd 150 /** Default value for Collision Window / Retry register */
jakeb 15:688b3e3958fd 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
jakeb 15:688b3e3958fd 152
jakeb 15:688b3e3958fd 153 /*********************************************************************//**
jakeb 15:688b3e3958fd 154 * Macro defines for Maximum Frame Register
jakeb 15:688b3e3958fd 155 **********************************************************************/
jakeb 15:688b3e3958fd 156 /** Represents a maximum receive frame of 1536 octets */
jakeb 15:688b3e3958fd 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
jakeb 15:688b3e3958fd 158
jakeb 15:688b3e3958fd 159 /*********************************************************************//**
jakeb 15:688b3e3958fd 160 * Macro defines for PHY Support Register
jakeb 15:688b3e3958fd 161 **********************************************************************/
jakeb 15:688b3e3958fd 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
jakeb 15:688b3e3958fd 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
jakeb 15:688b3e3958fd 164
jakeb 15:688b3e3958fd 165 /*********************************************************************//**
jakeb 15:688b3e3958fd 166 * Macro defines for Test Register
jakeb 15:688b3e3958fd 167 **********************************************************************/
jakeb 15:688b3e3958fd 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
jakeb 15:688b3e3958fd 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
jakeb 15:688b3e3958fd 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
jakeb 15:688b3e3958fd 171
jakeb 15:688b3e3958fd 172 /*********************************************************************//**
jakeb 15:688b3e3958fd 173 * Macro defines for MII Management Configuration Register
jakeb 15:688b3e3958fd 174 **********************************************************************/
jakeb 15:688b3e3958fd 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
jakeb 15:688b3e3958fd 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
jakeb 15:688b3e3958fd 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
jakeb 15:688b3e3958fd 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
jakeb 15:688b3e3958fd 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
jakeb 15:688b3e3958fd 180
jakeb 15:688b3e3958fd 181 /*********************************************************************//**
jakeb 15:688b3e3958fd 182 * Macro defines for MII Management Command Register
jakeb 15:688b3e3958fd 183 **********************************************************************/
jakeb 15:688b3e3958fd 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
jakeb 15:688b3e3958fd 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
jakeb 15:688b3e3958fd 186
jakeb 15:688b3e3958fd 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
jakeb 15:688b3e3958fd 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
jakeb 15:688b3e3958fd 189
jakeb 15:688b3e3958fd 190 /*********************************************************************//**
jakeb 15:688b3e3958fd 191 * Macro defines for MII Management Address Register
jakeb 15:688b3e3958fd 192 **********************************************************************/
jakeb 15:688b3e3958fd 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
jakeb 15:688b3e3958fd 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
jakeb 15:688b3e3958fd 195
jakeb 15:688b3e3958fd 196 /*********************************************************************//**
jakeb 15:688b3e3958fd 197 * Macro defines for MII Management Write Data Register
jakeb 15:688b3e3958fd 198 **********************************************************************/
jakeb 15:688b3e3958fd 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
jakeb 15:688b3e3958fd 200
jakeb 15:688b3e3958fd 201 /*********************************************************************//**
jakeb 15:688b3e3958fd 202 * Macro defines for MII Management Read Data Register
jakeb 15:688b3e3958fd 203 **********************************************************************/
jakeb 15:688b3e3958fd 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
jakeb 15:688b3e3958fd 205
jakeb 15:688b3e3958fd 206 /*********************************************************************//**
jakeb 15:688b3e3958fd 207 * Macro defines for MII Management Indicators Register
jakeb 15:688b3e3958fd 208 **********************************************************************/
jakeb 15:688b3e3958fd 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
jakeb 15:688b3e3958fd 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
jakeb 15:688b3e3958fd 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
jakeb 15:688b3e3958fd 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
jakeb 15:688b3e3958fd 213
jakeb 15:688b3e3958fd 214 /* Station Address 0 Register */
jakeb 15:688b3e3958fd 215 /* Station Address 1 Register */
jakeb 15:688b3e3958fd 216 /* Station Address 2 Register */
jakeb 15:688b3e3958fd 217
jakeb 15:688b3e3958fd 218
jakeb 15:688b3e3958fd 219 /* Control register definitions --------------------------------------------------------------------------- */
jakeb 15:688b3e3958fd 220 /*********************************************************************//**
jakeb 15:688b3e3958fd 221 * Macro defines for Command Register
jakeb 15:688b3e3958fd 222 **********************************************************************/
jakeb 15:688b3e3958fd 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
jakeb 15:688b3e3958fd 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
jakeb 15:688b3e3958fd 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
jakeb 15:688b3e3958fd 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
jakeb 15:688b3e3958fd 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
jakeb 15:688b3e3958fd 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
jakeb 15:688b3e3958fd 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
jakeb 15:688b3e3958fd 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
jakeb 15:688b3e3958fd 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
jakeb 15:688b3e3958fd 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
jakeb 15:688b3e3958fd 233
jakeb 15:688b3e3958fd 234 /*********************************************************************//**
jakeb 15:688b3e3958fd 235 * Macro defines for Status Register
jakeb 15:688b3e3958fd 236 **********************************************************************/
jakeb 15:688b3e3958fd 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
jakeb 15:688b3e3958fd 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
jakeb 15:688b3e3958fd 239
jakeb 15:688b3e3958fd 240 /*********************************************************************//**
jakeb 15:688b3e3958fd 241 * Macro defines for Transmit Status Vector 0 Register
jakeb 15:688b3e3958fd 242 **********************************************************************/
jakeb 15:688b3e3958fd 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
jakeb 15:688b3e3958fd 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
jakeb 15:688b3e3958fd 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
jakeb 15:688b3e3958fd 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
jakeb 15:688b3e3958fd 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
jakeb 15:688b3e3958fd 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
jakeb 15:688b3e3958fd 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
jakeb 15:688b3e3958fd 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
jakeb 15:688b3e3958fd 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
jakeb 15:688b3e3958fd 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
jakeb 15:688b3e3958fd 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
jakeb 15:688b3e3958fd 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
jakeb 15:688b3e3958fd 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
jakeb 15:688b3e3958fd 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
jakeb 15:688b3e3958fd 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
jakeb 15:688b3e3958fd 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
jakeb 15:688b3e3958fd 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
jakeb 15:688b3e3958fd 260
jakeb 15:688b3e3958fd 261 /*********************************************************************//**
jakeb 15:688b3e3958fd 262 * Macro defines for Transmit Status Vector 1 Register
jakeb 15:688b3e3958fd 263 **********************************************************************/
jakeb 15:688b3e3958fd 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
jakeb 15:688b3e3958fd 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
jakeb 15:688b3e3958fd 266
jakeb 15:688b3e3958fd 267 /*********************************************************************//**
jakeb 15:688b3e3958fd 268 * Macro defines for Receive Status Vector Register
jakeb 15:688b3e3958fd 269 **********************************************************************/
jakeb 15:688b3e3958fd 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
jakeb 15:688b3e3958fd 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
jakeb 15:688b3e3958fd 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
jakeb 15:688b3e3958fd 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
jakeb 15:688b3e3958fd 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
jakeb 15:688b3e3958fd 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
jakeb 15:688b3e3958fd 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
jakeb 15:688b3e3958fd 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
jakeb 15:688b3e3958fd 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
jakeb 15:688b3e3958fd 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
jakeb 15:688b3e3958fd 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
jakeb 15:688b3e3958fd 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
jakeb 15:688b3e3958fd 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
jakeb 15:688b3e3958fd 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
jakeb 15:688b3e3958fd 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
jakeb 15:688b3e3958fd 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
jakeb 15:688b3e3958fd 286
jakeb 15:688b3e3958fd 287 /*********************************************************************//**
jakeb 15:688b3e3958fd 288 * Macro defines for Flow Control Counter Register
jakeb 15:688b3e3958fd 289 **********************************************************************/
jakeb 15:688b3e3958fd 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
jakeb 15:688b3e3958fd 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
jakeb 15:688b3e3958fd 292
jakeb 15:688b3e3958fd 293 /*********************************************************************//**
jakeb 15:688b3e3958fd 294 * Macro defines for Flow Control Status Register
jakeb 15:688b3e3958fd 295 **********************************************************************/
jakeb 15:688b3e3958fd 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
jakeb 15:688b3e3958fd 297
jakeb 15:688b3e3958fd 298
jakeb 15:688b3e3958fd 299 /* Receive filter register definitions -------------------------------------------------------- */
jakeb 15:688b3e3958fd 300 /*********************************************************************//**
jakeb 15:688b3e3958fd 301 * Macro defines for Receive Filter Control Register
jakeb 15:688b3e3958fd 302 **********************************************************************/
jakeb 15:688b3e3958fd 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
jakeb 15:688b3e3958fd 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
jakeb 15:688b3e3958fd 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
jakeb 15:688b3e3958fd 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
jakeb 15:688b3e3958fd 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
jakeb 15:688b3e3958fd 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
jakeb 15:688b3e3958fd 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
jakeb 15:688b3e3958fd 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
jakeb 15:688b3e3958fd 311
jakeb 15:688b3e3958fd 312 /*********************************************************************//**
jakeb 15:688b3e3958fd 313 * Macro defines for Receive Filter WoL Status/Clear Registers
jakeb 15:688b3e3958fd 314 **********************************************************************/
jakeb 15:688b3e3958fd 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
jakeb 15:688b3e3958fd 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
jakeb 15:688b3e3958fd 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
jakeb 15:688b3e3958fd 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
jakeb 15:688b3e3958fd 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
jakeb 15:688b3e3958fd 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
jakeb 15:688b3e3958fd 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
jakeb 15:688b3e3958fd 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
jakeb 15:688b3e3958fd 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
jakeb 15:688b3e3958fd 324
jakeb 15:688b3e3958fd 325
jakeb 15:688b3e3958fd 326 /* Module control register definitions ---------------------------------------------------- */
jakeb 15:688b3e3958fd 327 /*********************************************************************//**
jakeb 15:688b3e3958fd 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
jakeb 15:688b3e3958fd 329 **********************************************************************/
jakeb 15:688b3e3958fd 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
jakeb 15:688b3e3958fd 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
jakeb 15:688b3e3958fd 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
jakeb 15:688b3e3958fd 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
jakeb 15:688b3e3958fd 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
jakeb 15:688b3e3958fd 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
jakeb 15:688b3e3958fd 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
jakeb 15:688b3e3958fd 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
jakeb 15:688b3e3958fd 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
jakeb 15:688b3e3958fd 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
jakeb 15:688b3e3958fd 340
jakeb 15:688b3e3958fd 341 /*********************************************************************//**
jakeb 15:688b3e3958fd 342 * Macro defines for Power Down Register
jakeb 15:688b3e3958fd 343 **********************************************************************/
jakeb 15:688b3e3958fd 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
jakeb 15:688b3e3958fd 345
jakeb 15:688b3e3958fd 346 /* Descriptor and status formats ---------------------------------------------------- */
jakeb 15:688b3e3958fd 347 /*********************************************************************//**
jakeb 15:688b3e3958fd 348 * Macro defines for RX Descriptor Control Word
jakeb 15:688b3e3958fd 349 **********************************************************************/
jakeb 15:688b3e3958fd 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
jakeb 15:688b3e3958fd 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
jakeb 15:688b3e3958fd 352
jakeb 15:688b3e3958fd 353 /*********************************************************************//**
jakeb 15:688b3e3958fd 354 * Macro defines for RX Status Hash CRC Word
jakeb 15:688b3e3958fd 355 **********************************************************************/
jakeb 15:688b3e3958fd 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
jakeb 15:688b3e3958fd 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
jakeb 15:688b3e3958fd 358
jakeb 15:688b3e3958fd 359 /*********************************************************************//**
jakeb 15:688b3e3958fd 360 * Macro defines for RX Status Information Word
jakeb 15:688b3e3958fd 361 **********************************************************************/
jakeb 15:688b3e3958fd 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
jakeb 15:688b3e3958fd 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
jakeb 15:688b3e3958fd 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
jakeb 15:688b3e3958fd 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
jakeb 15:688b3e3958fd 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
jakeb 15:688b3e3958fd 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
jakeb 15:688b3e3958fd 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
jakeb 15:688b3e3958fd 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
jakeb 15:688b3e3958fd 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
jakeb 15:688b3e3958fd 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
jakeb 15:688b3e3958fd 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
jakeb 15:688b3e3958fd 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
jakeb 15:688b3e3958fd 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
jakeb 15:688b3e3958fd 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
jakeb 15:688b3e3958fd 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
jakeb 15:688b3e3958fd 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
jakeb 15:688b3e3958fd 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
jakeb 15:688b3e3958fd 379
jakeb 15:688b3e3958fd 380 /*********************************************************************//**
jakeb 15:688b3e3958fd 381 * Macro defines for TX Descriptor Control Word
jakeb 15:688b3e3958fd 382 **********************************************************************/
jakeb 15:688b3e3958fd 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
jakeb 15:688b3e3958fd 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
jakeb 15:688b3e3958fd 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
jakeb 15:688b3e3958fd 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
jakeb 15:688b3e3958fd 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
jakeb 15:688b3e3958fd 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
jakeb 15:688b3e3958fd 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
jakeb 15:688b3e3958fd 390
jakeb 15:688b3e3958fd 391 /*********************************************************************//**
jakeb 15:688b3e3958fd 392 * Macro defines for TX Status Information Word
jakeb 15:688b3e3958fd 393 **********************************************************************/
jakeb 15:688b3e3958fd 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
jakeb 15:688b3e3958fd 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
jakeb 15:688b3e3958fd 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
jakeb 15:688b3e3958fd 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
jakeb 15:688b3e3958fd 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
jakeb 15:688b3e3958fd 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
jakeb 15:688b3e3958fd 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
jakeb 15:688b3e3958fd 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
jakeb 15:688b3e3958fd 402
jakeb 15:688b3e3958fd 403 #ifdef MCB_LPC_1768
jakeb 15:688b3e3958fd 404 /* DP83848C PHY definition ------------------------------------------------------------ */
jakeb 15:688b3e3958fd 405
jakeb 15:688b3e3958fd 406 /** PHY device reset time out definition */
jakeb 15:688b3e3958fd 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
jakeb 15:688b3e3958fd 408
jakeb 15:688b3e3958fd 409 /* ENET Device Revision ID */
jakeb 15:688b3e3958fd 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
jakeb 15:688b3e3958fd 411
jakeb 15:688b3e3958fd 412 /*********************************************************************//**
jakeb 15:688b3e3958fd 413 * Macro defines for DP83848C PHY Registers
jakeb 15:688b3e3958fd 414 **********************************************************************/
jakeb 15:688b3e3958fd 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
jakeb 15:688b3e3958fd 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
jakeb 15:688b3e3958fd 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
jakeb 15:688b3e3958fd 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
jakeb 15:688b3e3958fd 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
jakeb 15:688b3e3958fd 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
jakeb 15:688b3e3958fd 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
jakeb 15:688b3e3958fd 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
jakeb 15:688b3e3958fd 423 #define EMAC_PHY_REG_LPNPA 0x08
jakeb 15:688b3e3958fd 424
jakeb 15:688b3e3958fd 425 /*********************************************************************//**
jakeb 15:688b3e3958fd 426 * Macro defines for PHY Extended Registers
jakeb 15:688b3e3958fd 427 **********************************************************************/
jakeb 15:688b3e3958fd 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
jakeb 15:688b3e3958fd 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
jakeb 15:688b3e3958fd 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
jakeb 15:688b3e3958fd 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
jakeb 15:688b3e3958fd 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
jakeb 15:688b3e3958fd 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
jakeb 15:688b3e3958fd 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
jakeb 15:688b3e3958fd 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
jakeb 15:688b3e3958fd 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
jakeb 15:688b3e3958fd 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
jakeb 15:688b3e3958fd 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
jakeb 15:688b3e3958fd 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
jakeb 15:688b3e3958fd 440
jakeb 15:688b3e3958fd 441 /*********************************************************************//**
jakeb 15:688b3e3958fd 442 * Macro defines for PHY Basic Mode Control Register
jakeb 15:688b3e3958fd 443 **********************************************************************/
jakeb 15:688b3e3958fd 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
jakeb 15:688b3e3958fd 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
jakeb 15:688b3e3958fd 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
jakeb 15:688b3e3958fd 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
jakeb 15:688b3e3958fd 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
jakeb 15:688b3e3958fd 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
jakeb 15:688b3e3958fd 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
jakeb 15:688b3e3958fd 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
jakeb 15:688b3e3958fd 452
jakeb 15:688b3e3958fd 453 /*********************************************************************//**
jakeb 15:688b3e3958fd 454 * Macro defines for PHY Basic Mode Status Status Register
jakeb 15:688b3e3958fd 455 **********************************************************************/
jakeb 15:688b3e3958fd 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
jakeb 15:688b3e3958fd 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
jakeb 15:688b3e3958fd 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
jakeb 15:688b3e3958fd 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
jakeb 15:688b3e3958fd 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
jakeb 15:688b3e3958fd 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
jakeb 15:688b3e3958fd 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
jakeb 15:688b3e3958fd 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
jakeb 15:688b3e3958fd 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
jakeb 15:688b3e3958fd 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
jakeb 15:688b3e3958fd 466
jakeb 15:688b3e3958fd 467 /*********************************************************************//**
jakeb 15:688b3e3958fd 468 * Macro defines for PHY Status Register
jakeb 15:688b3e3958fd 469 **********************************************************************/
jakeb 15:688b3e3958fd 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
jakeb 15:688b3e3958fd 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
jakeb 15:688b3e3958fd 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
jakeb 15:688b3e3958fd 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
jakeb 15:688b3e3958fd 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
jakeb 15:688b3e3958fd 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
jakeb 15:688b3e3958fd 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
jakeb 15:688b3e3958fd 477
jakeb 15:688b3e3958fd 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
jakeb 15:688b3e3958fd 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
jakeb 15:688b3e3958fd 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
jakeb 15:688b3e3958fd 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
jakeb 15:688b3e3958fd 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
jakeb 15:688b3e3958fd 483
jakeb 15:688b3e3958fd 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
jakeb 15:688b3e3958fd 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
jakeb 15:688b3e3958fd 486
jakeb 15:688b3e3958fd 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
jakeb 15:688b3e3958fd 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
jakeb 15:688b3e3958fd 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
jakeb 15:688b3e3958fd 490
jakeb 15:688b3e3958fd 491 #elif defined(IAR_LPC_1768)
jakeb 15:688b3e3958fd 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
jakeb 15:688b3e3958fd 493 /** PHY device reset time out definition */
jakeb 15:688b3e3958fd 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
jakeb 15:688b3e3958fd 495
jakeb 15:688b3e3958fd 496 /* ENET Device Revision ID */
jakeb 15:688b3e3958fd 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
jakeb 15:688b3e3958fd 498
jakeb 15:688b3e3958fd 499 /*********************************************************************//**
jakeb 15:688b3e3958fd 500 * Macro defines for KSZ8721BL PHY Registers
jakeb 15:688b3e3958fd 501 **********************************************************************/
jakeb 15:688b3e3958fd 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
jakeb 15:688b3e3958fd 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
jakeb 15:688b3e3958fd 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
jakeb 15:688b3e3958fd 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
jakeb 15:688b3e3958fd 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
jakeb 15:688b3e3958fd 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
jakeb 15:688b3e3958fd 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
jakeb 15:688b3e3958fd 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
jakeb 15:688b3e3958fd 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
jakeb 15:688b3e3958fd 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
jakeb 15:688b3e3958fd 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
jakeb 15:688b3e3958fd 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
jakeb 15:688b3e3958fd 514
jakeb 15:688b3e3958fd 515 /*********************************************************************//**
jakeb 15:688b3e3958fd 516 * Macro defines for PHY Basic Mode Control Register
jakeb 15:688b3e3958fd 517 **********************************************************************/
jakeb 15:688b3e3958fd 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
jakeb 15:688b3e3958fd 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
jakeb 15:688b3e3958fd 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
jakeb 15:688b3e3958fd 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
jakeb 15:688b3e3958fd 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
jakeb 15:688b3e3958fd 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
jakeb 15:688b3e3958fd 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
jakeb 15:688b3e3958fd 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
jakeb 15:688b3e3958fd 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
jakeb 15:688b3e3958fd 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
jakeb 15:688b3e3958fd 528
jakeb 15:688b3e3958fd 529 /*********************************************************************//**
jakeb 15:688b3e3958fd 530 * Macro defines for PHY Basic Mode Status Register
jakeb 15:688b3e3958fd 531 **********************************************************************/
jakeb 15:688b3e3958fd 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
jakeb 15:688b3e3958fd 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
jakeb 15:688b3e3958fd 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
jakeb 15:688b3e3958fd 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
jakeb 15:688b3e3958fd 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
jakeb 15:688b3e3958fd 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
jakeb 15:688b3e3958fd 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
jakeb 15:688b3e3958fd 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
jakeb 15:688b3e3958fd 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
jakeb 15:688b3e3958fd 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
jakeb 15:688b3e3958fd 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
jakeb 15:688b3e3958fd 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
jakeb 15:688b3e3958fd 544
jakeb 15:688b3e3958fd 545 /*********************************************************************//**
jakeb 15:688b3e3958fd 546 * Macro defines for PHY Identifier
jakeb 15:688b3e3958fd 547 **********************************************************************/
jakeb 15:688b3e3958fd 548 /* PHY Identifier 1 bitmap definitions */
jakeb 15:688b3e3958fd 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
jakeb 15:688b3e3958fd 550
jakeb 15:688b3e3958fd 551 /* PHY Identifier 2 bitmap definitions */
jakeb 15:688b3e3958fd 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
jakeb 15:688b3e3958fd 553
jakeb 15:688b3e3958fd 554 /*********************************************************************//**
jakeb 15:688b3e3958fd 555 * Macro defines for Auto-Negotiation Advertisement
jakeb 15:688b3e3958fd 556 **********************************************************************/
jakeb 15:688b3e3958fd 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
jakeb 15:688b3e3958fd 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
jakeb 15:688b3e3958fd 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
jakeb 15:688b3e3958fd 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
jakeb 15:688b3e3958fd 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
jakeb 15:688b3e3958fd 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
jakeb 15:688b3e3958fd 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
jakeb 15:688b3e3958fd 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
jakeb 15:688b3e3958fd 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
jakeb 15:688b3e3958fd 566
jakeb 15:688b3e3958fd 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
jakeb 15:688b3e3958fd 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
jakeb 15:688b3e3958fd 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
jakeb 15:688b3e3958fd 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
jakeb 15:688b3e3958fd 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
jakeb 15:688b3e3958fd 572
jakeb 15:688b3e3958fd 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
jakeb 15:688b3e3958fd 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
jakeb 15:688b3e3958fd 575
jakeb 15:688b3e3958fd 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
jakeb 15:688b3e3958fd 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
jakeb 15:688b3e3958fd 578 #endif
jakeb 15:688b3e3958fd 579
jakeb 15:688b3e3958fd 580 /**
jakeb 15:688b3e3958fd 581 * @}
jakeb 15:688b3e3958fd 582 */
jakeb 15:688b3e3958fd 583
jakeb 15:688b3e3958fd 584
jakeb 15:688b3e3958fd 585 /* Public Types --------------------------------------------------------------- */
jakeb 15:688b3e3958fd 586 /** @defgroup EMAC_Public_Types EMAC Public Types
jakeb 15:688b3e3958fd 587 * @{
jakeb 15:688b3e3958fd 588 */
jakeb 15:688b3e3958fd 589
jakeb 15:688b3e3958fd 590 /* Descriptor and status formats ---------------------------------------------- */
jakeb 15:688b3e3958fd 591
jakeb 15:688b3e3958fd 592 /**
jakeb 15:688b3e3958fd 593 * @brief RX Descriptor structure type definition
jakeb 15:688b3e3958fd 594 */
jakeb 15:688b3e3958fd 595 typedef struct {
jakeb 15:688b3e3958fd 596 uint32_t Packet; /**< Receive Packet Descriptor */
jakeb 15:688b3e3958fd 597 uint32_t Ctrl; /**< Receive Control Descriptor */
jakeb 15:688b3e3958fd 598 } RX_Desc;
jakeb 15:688b3e3958fd 599
jakeb 15:688b3e3958fd 600 /**
jakeb 15:688b3e3958fd 601 * @brief RX Status structure type definition
jakeb 15:688b3e3958fd 602 */
jakeb 15:688b3e3958fd 603 typedef struct {
jakeb 15:688b3e3958fd 604 uint32_t Info; /**< Receive Information Status */
jakeb 15:688b3e3958fd 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
jakeb 15:688b3e3958fd 606 } RX_Stat;
jakeb 15:688b3e3958fd 607
jakeb 15:688b3e3958fd 608 /**
jakeb 15:688b3e3958fd 609 * @brief TX Descriptor structure type definition
jakeb 15:688b3e3958fd 610 */
jakeb 15:688b3e3958fd 611 typedef struct {
jakeb 15:688b3e3958fd 612 uint32_t Packet; /**< Transmit Packet Descriptor */
jakeb 15:688b3e3958fd 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
jakeb 15:688b3e3958fd 614 } TX_Desc;
jakeb 15:688b3e3958fd 615
jakeb 15:688b3e3958fd 616 /**
jakeb 15:688b3e3958fd 617 * @brief TX Status structure type definition
jakeb 15:688b3e3958fd 618 */
jakeb 15:688b3e3958fd 619 typedef struct {
jakeb 15:688b3e3958fd 620 uint32_t Info; /**< Transmit Information Status */
jakeb 15:688b3e3958fd 621 } TX_Stat;
jakeb 15:688b3e3958fd 622
jakeb 15:688b3e3958fd 623
jakeb 15:688b3e3958fd 624 /**
jakeb 15:688b3e3958fd 625 * @brief TX Data Buffer structure definition
jakeb 15:688b3e3958fd 626 */
jakeb 15:688b3e3958fd 627 typedef struct {
jakeb 15:688b3e3958fd 628 uint32_t ulDataLen; /**< Data length */
jakeb 15:688b3e3958fd 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
jakeb 15:688b3e3958fd 630 } EMAC_PACKETBUF_Type;
jakeb 15:688b3e3958fd 631
jakeb 15:688b3e3958fd 632 /**
jakeb 15:688b3e3958fd 633 * @brief EMAC configuration structure definition
jakeb 15:688b3e3958fd 634 */
jakeb 15:688b3e3958fd 635 typedef struct {
jakeb 15:688b3e3958fd 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
jakeb 15:688b3e3958fd 637 - EMAC_MODE_AUTO
jakeb 15:688b3e3958fd 638 - EMAC_MODE_10M_FULL
jakeb 15:688b3e3958fd 639 - EMAC_MODE_10M_HALF
jakeb 15:688b3e3958fd 640 - EMAC_MODE_100M_FULL
jakeb 15:688b3e3958fd 641 - EMAC_MODE_100M_HALF
jakeb 15:688b3e3958fd 642 */
jakeb 15:688b3e3958fd 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
jakeb 15:688b3e3958fd 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
jakeb 15:688b3e3958fd 645 */
jakeb 15:688b3e3958fd 646 } EMAC_CFG_Type;
jakeb 15:688b3e3958fd 647
jakeb 15:688b3e3958fd 648 /** Ethernet block power/clock control bit*/
jakeb 15:688b3e3958fd 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
jakeb 15:688b3e3958fd 650
jakeb 15:688b3e3958fd 651 #ifdef __cplusplus
jakeb 15:688b3e3958fd 652 }
jakeb 15:688b3e3958fd 653 #endif
jakeb 15:688b3e3958fd 654
jakeb 15:688b3e3958fd 655 #endif /* LPC17XX_EMAC_H_ */
jakeb 15:688b3e3958fd 656
jakeb 15:688b3e3958fd 657 /**
jakeb 15:688b3e3958fd 658 * @}
jakeb 15:688b3e3958fd 659 */
jakeb 15:688b3e3958fd 660
jakeb 15:688b3e3958fd 661 /* --------------------------------- End Of File ------------------------------ */