DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_timer.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/**
igorsk	0:1063a091a062	2	* @file : lpc17xx_timer.h
igorsk	0:1063a091a062	3	* @brief : Contains all functions support for Timer firmware library on LPC17xx
igorsk	0:1063a091a062	4	* @version : 1.0
igorsk	0:1063a091a062	5	* @date : 14. April. 2009
igorsk	0:1063a091a062	6	* @author : HieuNguyen
igorsk	0:1063a091a062	7	**************************************************************************
igorsk	0:1063a091a062	8	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	9	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	10	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	11	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	12	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	13	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	14	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	15	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	16	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	17	* use without further testing or modification.
igorsk	0:1063a091a062	18	**********************************************************************/
igorsk	0:1063a091a062	19
igorsk	0:1063a091a062	20	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	21	/** @defgroup TIM
igorsk	0:1063a091a062	22	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	23	* @{
igorsk	0:1063a091a062	24	*/
igorsk	0:1063a091a062	25
igorsk	0:1063a091a062	26	#ifndef __LPC17XX_TIMER_H_
igorsk	0:1063a091a062	27	#define __LPC17XX_TIMER_H_
igorsk	0:1063a091a062	28
igorsk	0:1063a091a062	29	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	30	#include "cmsis.h"
igorsk	0:1063a091a062	31	#include "lpc_types.h"
igorsk	0:1063a091a062	32
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	35	/** @defgroup TIM_Private_Macros
igorsk	0:1063a091a062	36	* @{
igorsk	0:1063a091a062	37	*/
igorsk	0:1063a091a062	38
igorsk	0:1063a091a062	39	/************************ TIMER/COUNTER Control ************************/
igorsk	0:1063a091a062	40	/** @defgroup TIM_REGISTER_BIT_DEFINITION
igorsk	0:1063a091a062	41	* @{
igorsk	0:1063a091a062	42	*/
igorsk	0:1063a091a062	43
igorsk	0:1063a091a062	44	/**********************************************************************
igorsk	0:1063a091a062	45	** Interrupt information
igorsk	0:1063a091a062	46	**********************************************************************/
igorsk	0:1063a091a062	47	/** Macro to clean interrupt pending */
igorsk	0:1063a091a062	48	#define TIM_IR_CLR(n) _BIT(n)
igorsk	0:1063a091a062	49
igorsk	0:1063a091a062	50	/**********************************************************************
igorsk	0:1063a091a062	51	** Timer interrupt register definitions
igorsk	0:1063a091a062	52	**********************************************************************/
igorsk	0:1063a091a062	53	/** Macro for getting a timer match interrupt bit */
igorsk	0:1063a091a062	54	#define TIM_MATCH_INT(n) (_BIT(n & 0x0F))
igorsk	0:1063a091a062	55	/** Macro for getting a capture event interrupt bit */
igorsk	0:1063a091a062	56	#define TIM_CAP_INT(n) (_BIT(((n & 0x0F) + 4)))
igorsk	0:1063a091a062	57
igorsk	0:1063a091a062	58	/**********************************************************************
igorsk	0:1063a091a062	59	* Timer control register definitions
igorsk	0:1063a091a062	60	**********************************************************************/
igorsk	0:1063a091a062	61	/** Timer/counter enable bit */
igorsk	0:1063a091a062	62	#define TIM_ENABLE ((uint32_t)(1<<0))
igorsk	0:1063a091a062	63	/** Timer/counter reset bit */
igorsk	0:1063a091a062	64	#define TIM_RESET ((uint32_t)(1<<1))
igorsk	0:1063a091a062	65	/** Timer control bit mask */
igorsk	0:1063a091a062	66	#define TIM_TCR_MASKBIT ((uint32_t)(3))
igorsk	0:1063a091a062	67
igorsk	0:1063a091a062	68	/**********************************************************************
igorsk	0:1063a091a062	69	* Timer match control register definitions
igorsk	0:1063a091a062	70	**********************************************************************/
igorsk	0:1063a091a062	71	/** Bit location for interrupt on MRx match, n = 0 to 3 */
igorsk	0:1063a091a062	72	#define TIM_INT_ON_MATCH(n) (_BIT((n * 3)))
igorsk	0:1063a091a062	73	/** Bit location for reset on MRx match, n = 0 to 3 */
igorsk	0:1063a091a062	74	#define TIM_RESET_ON_MATCH(n) (_BIT(((n * 3) + 1)))
igorsk	0:1063a091a062	75	/** Bit location for stop on MRx match, n = 0 to 3 */
igorsk	0:1063a091a062	76	#define TIM_STOP_ON_MATCH(n) (_BIT(((n * 3) + 2)))
igorsk	0:1063a091a062	77	/** Timer Match control bit mask */
igorsk	0:1063a091a062	78	#define TIM_MCR_MASKBIT ((uint32_t)(0x0FFF))
igorsk	0:1063a091a062	79	/** Timer Match control bit mask for specific channel*/
igorsk	0:1063a091a062	80	#define TIM_MCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<n))
igorsk	0:1063a091a062	81	/**********************************************************************
igorsk	0:1063a091a062	82	* Timer capture control register definitions
igorsk	0:1063a091a062	83	**********************************************************************/
igorsk	0:1063a091a062	84	/** Bit location for CAP.n on CRx rising edge, n = 0 to 3 */
igorsk	0:1063a091a062	85	#define TIM_CAP_RISING(n) (_BIT((n * 3)))
igorsk	0:1063a091a062	86	/** Bit location for CAP.n on CRx falling edge, n = 0 to 3 */
igorsk	0:1063a091a062	87	#define TIM_CAP_FALLING(n) (_BIT(((n * 3) + 1)))
igorsk	0:1063a091a062	88	/** Bit location for CAP.n on CRx interrupt enable, n = 0 to 3 */
igorsk	0:1063a091a062	89	#define TIM_INT_ON_CAP(n) (_BIT(((n * 3) + 2)))
igorsk	0:1063a091a062	90	/** Mask bit for rising and falling edge bit */
igorsk	0:1063a091a062	91	#define TIM_EDGE_MASK(n) (_SBF((n * 3), 0x03))
igorsk	0:1063a091a062	92	/** Timer capture control bit mask */
igorsk	0:1063a091a062	93	#define TIM_CCR_MASKBIT ((uint32_t)(0x3F))
igorsk	0:1063a091a062	94	/** Timer Capture control bit mask for specific channel*/
igorsk	0:1063a091a062	95	#define TIM_CCR_CHANNEL_MASKBIT(n) ((uint32_t)(7<<n))
igorsk	0:1063a091a062	96
igorsk	0:1063a091a062	97	/**********************************************************************
igorsk	0:1063a091a062	98	* Timer external match register definitions
igorsk	0:1063a091a062	99	**********************************************************************/
igorsk	0:1063a091a062	100	/** Bit location for output state change of MAT.n when external match
igorsk	0:1063a091a062	101	happens, n = 0 to 3 */
igorsk	0:1063a091a062	102	#define TIM_EM(n) _BIT(n)
igorsk	0:1063a091a062	103	/** Output state change of MAT.n when external match happens: no change */
igorsk	0:1063a091a062	104	#define TIM_EM_NOTHING ((uint8_t)(0x0))
igorsk	0:1063a091a062	105	/** Output state change of MAT.n when external match happens: low */
igorsk	0:1063a091a062	106	#define TIM_EM_LOW ((uint8_t)(0x1))
igorsk	0:1063a091a062	107	/** Output state change of MAT.n when external match happens: high */
igorsk	0:1063a091a062	108	#define TIM_EM_HIGH ((uint8_t)(0x2))
igorsk	0:1063a091a062	109	/** Output state change of MAT.n when external match happens: toggle */
igorsk	0:1063a091a062	110	#define TIM_EM_TOGGLE ((uint8_t)(0x3))
igorsk	0:1063a091a062	111	/** Macro for setting for the MAT.n change state bits */
igorsk	0:1063a091a062	112	#define TIM_EM_SET(n,s) (_SBF(((n << 1) + 4), (s & 0x03)))
igorsk	0:1063a091a062	113	/** Mask for the MAT.n change state bits */
igorsk	0:1063a091a062	114	#define TIM_EM_MASK(n) (_SBF(((n << 1) + 4), 0x03))
igorsk	0:1063a091a062	115	/** Timer external match bit mask */
igorsk	0:1063a091a062	116	#define TIM_EMR_MASKBIT 0x0FFF
igorsk	0:1063a091a062	117	/**********************************************************************
igorsk	0:1063a091a062	118	* Timer Count Control Register definitions
igorsk	0:1063a091a062	119	**********************************************************************/
igorsk	0:1063a091a062	120	/** Mask to get the Counter/timer mode bits */
igorsk	0:1063a091a062	121	#define TIM_CTCR_MODE_MASK 0x3
igorsk	0:1063a091a062	122	/** Mask to get the count input select bits */
igorsk	0:1063a091a062	123	#define TIM_CTCR_INPUT_MASK 0xC
igorsk	0:1063a091a062	124	/** Timer Count control bit mask */
igorsk	0:1063a091a062	125	#define TIM_CTCR_MASKBIT 0xF
igorsk	0:1063a091a062	126	#define TIM_COUNTER_MODE ((uint8_t)(1))
igorsk	0:1063a091a062	127
igorsk	0:1063a091a062	128	/**
igorsk	0:1063a091a062	129	* @}
igorsk	0:1063a091a062	130	*/
igorsk	0:1063a091a062	131
igorsk	0:1063a091a062	132	/**
igorsk	0:1063a091a062	133	* @}
igorsk	0:1063a091a062	134	*/
igorsk	0:1063a091a062	135
igorsk	0:1063a091a062	136
igorsk	0:1063a091a062	137	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	138	/** @defgroup TIM_Public_Types
igorsk	0:1063a091a062	139	* @{
igorsk	0:1063a091a062	140	*/
igorsk	0:1063a091a062	141
igorsk	0:1063a091a062	142	/***********************************************************************
igorsk	0:1063a091a062	143	* Timer device enumeration
igorsk	0:1063a091a062	144	**********************************************************************/
igorsk	0:1063a091a062	145	/** @brief interrupt type */
igorsk	0:1063a091a062	146	typedef enum
igorsk	0:1063a091a062	147	{
igorsk	0:1063a091a062	148	TIM_MR0_INT =0, /!< interrupt for Match channel 0/
igorsk	0:1063a091a062	149	TIM_MR1_INT =1, /!< interrupt for Match channel 1/
igorsk	0:1063a091a062	150	TIM_MR2_INT =2, /!< interrupt for Match channel 2/
igorsk	0:1063a091a062	151	TIM_MR3_INT =3, /!< interrupt for Match channel 3/
igorsk	0:1063a091a062	152	TIM_CR0_INT =4, /!< interrupt for Capture channel 0/
igorsk	0:1063a091a062	153	TIM_CR1_INT =5, /!< interrupt for Capture channel 1/
igorsk	0:1063a091a062	154	}TIM_INT_TYPE;
igorsk	0:1063a091a062	155	#define PARAM_TIM_INT_TYPE(TYPE) ((TYPE ==TIM_MR0_INT)\|\|(TYPE ==TIM_MR1_INT)\
igorsk	0:1063a091a062	156	\|\|(TYPE ==TIM_MR2_INT)\|\|(TYPE ==TIM_MR3_INT)\
igorsk	0:1063a091a062	157	\|\|(TYPE ==TIM_CR0_INT)\|\|(TYPE ==TIM_CR1_INT))
igorsk	0:1063a091a062	158
igorsk	0:1063a091a062	159	/** @brief Timer/counter operating mode */
igorsk	0:1063a091a062	160	typedef enum
igorsk	0:1063a091a062	161	{
igorsk	0:1063a091a062	162	TIM_TIMER_MODE = 0, /!< Timer mode /
igorsk	0:1063a091a062	163	TIM_COUNTER_RISING_MODE, /!< Counter rising mode /
igorsk	0:1063a091a062	164	TIM_COUNTER_FALLING_MODE, /!< Counter falling mode /
igorsk	0:1063a091a062	165	TIM_COUNTER_ANY_MODE /!< Counter on both edges /
igorsk	0:1063a091a062	166	} TIM_MODE_OPT;
igorsk	0:1063a091a062	167	#define PARAM_TIM_MODE_OPT(MODE) ((MODE == TIM_TIMER_MODE)\|\|(MODE == TIM_COUNTER_RISING_MODE)\
igorsk	0:1063a091a062	168	\|\| (MODE == TIM_COUNTER_RISING_MODE)\|\|(MODE == TIM_COUNTER_RISING_MODE))
igorsk	0:1063a091a062	169	/** @brief Timer/Counter prescale option */
igorsk	0:1063a091a062	170	typedef enum
igorsk	0:1063a091a062	171	{
igorsk	0:1063a091a062	172	TIM_PRESCALE_TICKVAL = 0, /!< Prescale in absolute value /
igorsk	0:1063a091a062	173	TIM_PRESCALE_USVAL /!< Prescale in microsecond value /
igorsk	0:1063a091a062	174	} TIM_PRESCALE_OPT;
igorsk	0:1063a091a062	175	#define PARAM_TIM_PRESCALE_OPT(OPT) ((OPT == TIM_PRESCALE_TICKVAL)\|\|(OPT == TIM_PRESCALE_USVAL))
igorsk	0:1063a091a062	176	/** @brief Counter input option */
igorsk	0:1063a091a062	177	typedef enum
igorsk	0:1063a091a062	178	{
igorsk	0:1063a091a062	179	TIM_COUNTER_INCAP0 = 0, /!< CAPn.0 input pin for TIMERn /
igorsk	0:1063a091a062	180	TIM_COUNTER_INCAP1, /!< CAPn.1 input pin for TIMERn /
igorsk	0:1063a091a062	181	} TIM_COUNTER_INPUT_OPT;
igorsk	0:1063a091a062	182	#define PARAM_TIM_COUNTER_INPUT_OPT(OPT) ((OPT == TIM_COUNTER_INCAP0)\|\|(OPT == TIM_COUNTER_INCAP1))
igorsk	0:1063a091a062	183
igorsk	0:1063a091a062	184	/** @brief Timer/Counter external match option */
igorsk	0:1063a091a062	185	typedef enum
igorsk	0:1063a091a062	186	{
igorsk	0:1063a091a062	187	TIM_EXTMATCH_NOTHING = 0, /!< Do nothing for external output pin if match /
igorsk	0:1063a091a062	188	TIM_EXTMATCH_LOW, /!< Force external output pin to low if match /
igorsk	0:1063a091a062	189	TIM_EXTMATCH_HIGH, /!< Force external output pin to high if match /
igorsk	0:1063a091a062	190	TIM_EXTMATCH_TOGGLE /!< Toggle external output pin if match /
igorsk	0:1063a091a062	191	}TIM_EXTMATCH_OPT;
igorsk	0:1063a091a062	192	#define PARAM_TIM_EXTMATCH_OPT(OPT) ((OPT == TIM_EXTMATCH_NOTHING)\|\|(OPT == TIM_EXTMATCH_LOW)\
igorsk	0:1063a091a062	193	\|\|(OPT == TIM_EXTMATCH_HIGH)\|\|(OPT == TIM_EXTMATCH_TOGGLE))
igorsk	0:1063a091a062	194
igorsk	0:1063a091a062	195	/** @brief Timer/counter capture mode options */
igorsk	0:1063a091a062	196	typedef enum {
igorsk	0:1063a091a062	197	TIM_CAPTURE_NONE = 0, /!< No Capture /
igorsk	0:1063a091a062	198	TIM_CAPTURE_RISING, /!< Rising capture mode /
igorsk	0:1063a091a062	199	TIM_CAPTURE_FALLING, /!< Falling capture mode /
igorsk	0:1063a091a062	200	TIM_CAPTURE_ANY /!< On both edges /
igorsk	0:1063a091a062	201	} TIM_CAP_MODE_OPT;
igorsk	0:1063a091a062	202
igorsk	0:1063a091a062	203	#define PARAM_TIM_CAP_MODE_OPT(OPT) ((OPT == TIM_CAPTURE_NONE)\|\|(OPT == TIM_CAPTURE_RISING) \
igorsk	0:1063a091a062	204	\|\|(OPT == TIM_CAPTURE_FALLING)\|\|(OPT == TIM_CAPTURE_ANY))
igorsk	0:1063a091a062	205
igorsk	0:1063a091a062	206	/** @brief Configuration structure in TIMER mode */
igorsk	0:1063a091a062	207	typedef struct
igorsk	0:1063a091a062	208	{
igorsk	0:1063a091a062	209
igorsk	0:1063a091a062	210	uint8_t PrescaleOption; /**< Timer Prescale option, should be:
igorsk	0:1063a091a062	211	- TIM_PRESCALE_TICKVAL: Prescale in absolute value
igorsk	0:1063a091a062	212	- TIM_PRESCALE_USVAL: Prescale in microsecond value
igorsk	0:1063a091a062	213	*/
igorsk	0:1063a091a062	214	uint8_t Reserved[3]; /*< Reserved /
igorsk	0:1063a091a062	215	uint32_t PrescaleValue; /*< Prescale value /
igorsk	0:1063a091a062	216	} TIM_TIMERCFG_Type;
igorsk	0:1063a091a062	217
igorsk	0:1063a091a062	218	/** @brief Configuration structure in COUNTER mode */
igorsk	0:1063a091a062	219	typedef struct {
igorsk	0:1063a091a062	220
igorsk	0:1063a091a062	221	uint8_t CounterOption; /**< Counter Option, should be:
igorsk	0:1063a091a062	222	- TIM_COUNTER_INCAP0: CAPn.0 input pin for TIMERn
igorsk	0:1063a091a062	223	- TIM_COUNTER_INCAP1: CAPn.1 input pin for TIMERn
igorsk	0:1063a091a062	224	*/
igorsk	0:1063a091a062	225	uint8_t CountInputSelect;
igorsk	0:1063a091a062	226	uint8_t Reserved[2];
igorsk	0:1063a091a062	227	} TIM_COUNTERCFG_Type;
igorsk	0:1063a091a062	228
igorsk	0:1063a091a062	229	/** @brief Match channel configuration structure */
igorsk	0:1063a091a062	230	typedef struct {
igorsk	0:1063a091a062	231	uint8_t MatchChannel; /**< Match channel, should be in range
igorsk	0:1063a091a062	232	from 0..3 */
igorsk	0:1063a091a062	233	uint8_t IntOnMatch; /**< Interrupt On match, should be:
igorsk	0:1063a091a062	234	- ENABLE: Enable this function.
igorsk	0:1063a091a062	235	- DISABLE: Disable this function.
igorsk	0:1063a091a062	236	*/
igorsk	0:1063a091a062	237	uint8_t StopOnMatch; /**< Stop On match, should be:
igorsk	0:1063a091a062	238	- ENABLE: Enable this function.
igorsk	0:1063a091a062	239	- DISABLE: Disable this function.
igorsk	0:1063a091a062	240	*/
igorsk	0:1063a091a062	241	uint8_t ResetOnMatch; /**< Reset On match, should be:
igorsk	0:1063a091a062	242	- ENABLE: Enable this function.
igorsk	0:1063a091a062	243	- DISABLE: Disable this function.
igorsk	0:1063a091a062	244	*/
igorsk	0:1063a091a062	245
igorsk	0:1063a091a062	246	uint8_t ExtMatchOutputType; /**< External Match Output type, should be:
igorsk	0:1063a091a062	247	- 0: Do nothing for external output pin if match
igorsk	0:1063a091a062	248	- 1: Force external output pin to low if match
igorsk	0:1063a091a062	249	- 2: Force external output pin to high if match
igorsk	0:1063a091a062	250	- 3: Toggle external output pin if match.
igorsk	0:1063a091a062	251	*/
igorsk	0:1063a091a062	252	uint8_t Reserved[3]; /** Reserved */
igorsk	0:1063a091a062	253	uint32_t MatchValue; /** Match value */
igorsk	0:1063a091a062	254	} TIM_MATCHCFG_Type;
igorsk	0:1063a091a062	255
igorsk	0:1063a091a062	256
igorsk	0:1063a091a062	257	/** @brief Capture Input configuration structure */
igorsk	0:1063a091a062	258	typedef struct {
igorsk	0:1063a091a062	259	uint8_t CaptureChannel; /**< Capture channel, should be in range
igorsk	0:1063a091a062	260	from 0..1 */
igorsk	0:1063a091a062	261	uint8_t RisingEdge; /**< caption rising edge, should be:
igorsk	0:1063a091a062	262	- ENABLE: Enable rising edge.
igorsk	0:1063a091a062	263	- DISABLE: Disable this function.
igorsk	0:1063a091a062	264	*/
igorsk	0:1063a091a062	265	uint8_t FallingEdge; /**< caption falling edge, should be:
igorsk	0:1063a091a062	266	- ENABLE: Enable falling edge.
igorsk	0:1063a091a062	267	- DISABLE: Disable this function.
igorsk	0:1063a091a062	268	*/
igorsk	0:1063a091a062	269	uint8_t IntOnCaption; /**< Interrupt On caption, should be:
igorsk	0:1063a091a062	270	- ENABLE: Enable interrupt function.
igorsk	0:1063a091a062	271	- DISABLE: Disable this function.
igorsk	0:1063a091a062	272	*/
igorsk	0:1063a091a062	273
igorsk	0:1063a091a062	274	} TIM_CAPTURECFG_Type;
igorsk	0:1063a091a062	275
igorsk	0:1063a091a062	276	/**
igorsk	0:1063a091a062	277	* @}
igorsk	0:1063a091a062	278	*/
igorsk	0:1063a091a062	279
igorsk	0:1063a091a062	280
igorsk	0:1063a091a062	281	/* Public Macros -------------------------------------------------------------- */
igorsk	0:1063a091a062	282	/** @defgroup TIM_Public_Macros
igorsk	0:1063a091a062	283	* @{
igorsk	0:1063a091a062	284	*/
igorsk	0:1063a091a062	285
igorsk	0:1063a091a062	286	/** Macro to determine if it is valid TIMER peripheral */
igorsk	0:1063a091a062	287	#define PARAM_TIMx(n) ((((uint32_t )n)==((uint32_t )LPC_TIM0)) \|\| (((uint32_t )n)==((uint32_t )LPC_TIM1)) \
igorsk	0:1063a091a062	288	\|\| (((uint32_t )n)==((uint32_t )LPC_TIM2)) \|\| (((uint32_t )n)==((uint32_t )LPC_TIM3)))
igorsk	0:1063a091a062	289
igorsk	0:1063a091a062	290	/**
igorsk	0:1063a091a062	291	* @}
igorsk	0:1063a091a062	292	*/
igorsk	0:1063a091a062	293
igorsk	0:1063a091a062	294
igorsk	0:1063a091a062	295	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	296	/** @defgroup TIM_Public_Functions
igorsk	0:1063a091a062	297	* @{
igorsk	0:1063a091a062	298	*/
igorsk	0:1063a091a062	299
igorsk	0:1063a091a062	300	FlagStatus TIM_GetIntStatus(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag);
igorsk	0:1063a091a062	301	FlagStatus TIM_GetIntCaptureStatus(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag);
igorsk	0:1063a091a062	302	void TIM_ClearIntPending(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag);
igorsk	0:1063a091a062	303	void TIM_ClearIntCapturePending(LPC_TIM_TypeDef *TIMx, uint8_t IntFlag);
igorsk	0:1063a091a062	304	void TIM_Cmd(LPC_TIM_TypeDef *TIMx, FunctionalState NewState);
igorsk	0:1063a091a062	305	void TIM_ResetCounter(LPC_TIM_TypeDef *TIMx);
igorsk	0:1063a091a062	306	void TIM_Init(LPC_TIM_TypeDef TIMx, uint8_t TimerCounterMode, void TIM_ConfigStruct);
igorsk	0:1063a091a062	307	void TIM_DeInit(LPC_TIM_TypeDef *TIMx);
igorsk	0:1063a091a062	308	void TIM_ConfigStructInit(uint8_t TimerCounterMode, void *TIM_ConfigStruct);
igorsk	0:1063a091a062	309	void TIM_ConfigMatch(LPC_TIM_TypeDef TIMx, TIM_MATCHCFG_Type TIM_MatchConfigStruct);
igorsk	0:1063a091a062	310	void TIM_SetMatchExt(LPC_TIM_TypeDef *TIMx,TIM_EXTMATCH_OPT ext_match );
igorsk	0:1063a091a062	311	void TIM_ConfigCapture(LPC_TIM_TypeDef TIMx, TIM_CAPTURECFG_Type TIM_CaptureConfigStruct);
igorsk	0:1063a091a062	312	uint32_t TIM_GetCaptureValue(LPC_TIM_TypeDef *TIMx, uint8_t CaptureChannel);
igorsk	0:1063a091a062	313
igorsk	0:1063a091a062	314	/**
igorsk	0:1063a091a062	315	* @}
igorsk	0:1063a091a062	316	*/
igorsk	0:1063a091a062	317
igorsk	0:1063a091a062	318	#endif /* __LPC17XX_TIMER_H_ */
igorsk	0:1063a091a062	319
igorsk	0:1063a091a062	320	/**
igorsk	0:1063a091a062	321	* @}
igorsk	0:1063a091a062	322	*/
igorsk	0:1063a091a062	323
igorsk	0:1063a091a062	324	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_timer.h@0:1063a091a062, 2010-02-17 (annotated)

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