DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_i2s.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_i2s.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for I2S firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 13. May. 2009
igorsk	0:1063a091a062	7	* @author : NguyenCao
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup I2S
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_I2S_H_
igorsk	0:1063a091a062	28	#define LPC17XX_I2S_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34
igorsk	0:1063a091a062	35	#ifdef __cplusplus
igorsk	0:1063a091a062	36	extern "C"
igorsk	0:1063a091a062	37	{
igorsk	0:1063a091a062	38	#endif
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	42	/** @defgroup I2S_Private_Macros
igorsk	0:1063a091a062	43	* @{
igorsk	0:1063a091a062	44	*/
igorsk	0:1063a091a062	45
igorsk	0:1063a091a062	46	/*******************************************************************//
igorsk	0:1063a091a062	47	* Macro defines for DAO-Digital Audio Output register
igorsk	0:1063a091a062	48	**********************************************************************/
igorsk	0:1063a091a062	49	/** @defgroup I2S_REGISTER_BIT_DEFINITION
igorsk	0:1063a091a062	50	* @{
igorsk	0:1063a091a062	51	*/
igorsk	0:1063a091a062	52
igorsk	0:1063a091a062	53	/** I2S wordwide - the number of bytes in data*/
igorsk	0:1063a091a062	54	#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
igorsk	0:1063a091a062	55	#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
igorsk	0:1063a091a062	56	#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
igorsk	0:1063a091a062	57	/** I2S control mono or stereo format */
igorsk	0:1063a091a062	58	#define I2S_DAO_MONO ((uint32_t)(1<<2))
igorsk	0:1063a091a062	59	/** I2S control stop mode */
igorsk	0:1063a091a062	60	#define I2S_DAO_STOP ((uint32_t)(1<<3))
igorsk	0:1063a091a062	61	/** I2S control reset mode */
igorsk	0:1063a091a062	62	#define I2S_DAO_RESET ((uint32_t)(1<<4))
igorsk	0:1063a091a062	63	/** I2S control master/slave mode */
igorsk	0:1063a091a062	64	#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
igorsk	0:1063a091a062	65	/** I2S word select half period minus one */
igorsk	0:1063a091a062	66	#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
igorsk	0:1063a091a062	67	/** I2S control mute mode */
igorsk	0:1063a091a062	68	#define I2S_DAO_MUTE ((uint32_t)(1<<15))
igorsk	0:1063a091a062	69
igorsk	0:1063a091a062	70	/*******************************************************************//
igorsk	0:1063a091a062	71	* Macro defines for DAI-Digital Audio Input register
igorsk	0:1063a091a062	72	**********************************************************************/
igorsk	0:1063a091a062	73	/** I2S wordwide - the number of bytes in data*/
igorsk	0:1063a091a062	74	#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
igorsk	0:1063a091a062	75	#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
igorsk	0:1063a091a062	76	#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
igorsk	0:1063a091a062	77	/** I2S control mono or stereo format */
igorsk	0:1063a091a062	78	#define I2S_DAI_MONO ((uint32_t)(1<<2))
igorsk	0:1063a091a062	79	/** I2S control stop mode */
igorsk	0:1063a091a062	80	#define I2S_DAI_STOP ((uint32_t)(1<<3))
igorsk	0:1063a091a062	81	/** I2S control reset mode */
igorsk	0:1063a091a062	82	#define I2S_DAI_RESET ((uint32_t)(1<<4))
igorsk	0:1063a091a062	83	/** I2S control master/slave mode */
igorsk	0:1063a091a062	84	#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
igorsk	0:1063a091a062	85	/** I2S word select half period minus one (9 bits)*/
igorsk	0:1063a091a062	86	#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
igorsk	0:1063a091a062	87	/** I2S control mute mode */
igorsk	0:1063a091a062	88	#define I2S_DAI_MUTE ((uint32_t)(1<<15))
igorsk	0:1063a091a062	89
igorsk	0:1063a091a062	90	/*******************************************************************//
igorsk	0:1063a091a062	91	* Macro defines for STAT register (Status Feedback register)
igorsk	0:1063a091a062	92	**********************************************************************/
igorsk	0:1063a091a062	93	/** I2S Status Receive or Transmit Interrupt */
igorsk	0:1063a091a062	94	#define I2S_STATE_IRQ ((uint32_t)(1))
igorsk	0:1063a091a062	95	/** I2S Status Receive or Transmit DMA1 */
igorsk	0:1063a091a062	96	#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
igorsk	0:1063a091a062	97	/** I2S Status Receive or Transmit DMA2 */
igorsk	0:1063a091a062	98	#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
igorsk	0:1063a091a062	99	/** I2S Status Current level of the Receive FIFO (5 bits)*/
igorsk	0:1063a091a062	100	#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
igorsk	0:1063a091a062	101	/** I2S Status Current level of the Transmit FIFO (5 bits)*/
igorsk	0:1063a091a062	102	#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
igorsk	0:1063a091a062	103
igorsk	0:1063a091a062	104	/*******************************************************************//
igorsk	0:1063a091a062	105	* Macro defines for DMA1 register (DMA1 Configuration register)
igorsk	0:1063a091a062	106	**********************************************************************/
igorsk	0:1063a091a062	107	/** I2S control DMA1 for I2S receive */
igorsk	0:1063a091a062	108	#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
igorsk	0:1063a091a062	109	/** I2S control DMA1 for I2S transmit */
igorsk	0:1063a091a062	110	#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
igorsk	0:1063a091a062	111	/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
igorsk	0:1063a091a062	112	#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
igorsk	0:1063a091a062	113	/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
igorsk	0:1063a091a062	114	#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
igorsk	0:1063a091a062	115
igorsk	0:1063a091a062	116	/*******************************************************************//
igorsk	0:1063a091a062	117	* Macro defines for DMA2 register (DMA2 Configuration register)
igorsk	0:1063a091a062	118	**********************************************************************/
igorsk	0:1063a091a062	119	/** I2S control DMA2 for I2S receive */
igorsk	0:1063a091a062	120	#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
igorsk	0:1063a091a062	121	/** I2S control DMA1 for I2S transmit */
igorsk	0:1063a091a062	122	#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
igorsk	0:1063a091a062	123	/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
igorsk	0:1063a091a062	124	#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
igorsk	0:1063a091a062	125	/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
igorsk	0:1063a091a062	126	#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
igorsk	0:1063a091a062	127
igorsk	0:1063a091a062	128	/*******************************************************************//
igorsk	0:1063a091a062	129	* Macro defines for IRQ register (Interrupt Request Control register)
igorsk	0:1063a091a062	130	**********************************************************************/
igorsk	0:1063a091a062	131	/** I2S control I2S receive interrupt */
igorsk	0:1063a091a062	132	#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
igorsk	0:1063a091a062	133	/** I2S control I2S transmit interrupt */
igorsk	0:1063a091a062	134	#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
igorsk	0:1063a091a062	135	/** I2S set the FIFO level on which to create an irq request */
igorsk	0:1063a091a062	136	#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
igorsk	0:1063a091a062	137	/** I2S set the FIFO level on which to create an irq request */
igorsk	0:1063a091a062	138	#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
igorsk	0:1063a091a062	139
igorsk	0:1063a091a062	140	/******************************************************************************//
igorsk	0:1063a091a062	141	* Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
igorsk	0:1063a091a062	142	*********************************************************************************/
igorsk	0:1063a091a062	143	/** I2S Transmit MCLK rate denominator */
igorsk	0:1063a091a062	144	#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
igorsk	0:1063a091a062	145	/** I2S Transmit MCLK rate denominator */
igorsk	0:1063a091a062	146	#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
igorsk	0:1063a091a062	147	/** I2S Receive MCLK rate denominator */
igorsk	0:1063a091a062	148	#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
igorsk	0:1063a091a062	149	/** I2S Receive MCLK rate denominator */
igorsk	0:1063a091a062	150	#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
igorsk	0:1063a091a062	151
igorsk	0:1063a091a062	152	/***********************************************************************************//
igorsk	0:1063a091a062	153	* Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
igorsk	0:1063a091a062	154	**************************************************************************************/
igorsk	0:1063a091a062	155	#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
igorsk	0:1063a091a062	156	#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
igorsk	0:1063a091a062	157
igorsk	0:1063a091a062	158	/********************************************************************************//
igorsk	0:1063a091a062	159	* Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
igorsk	0:1063a091a062	160	************************************************************************************/
igorsk	0:1063a091a062	161	/** I2S Transmit select clock source (2 bits)*/
igorsk	0:1063a091a062	162	#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
igorsk	0:1063a091a062	163	/** I2S Transmit control 4-pin mode */
igorsk	0:1063a091a062	164	#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
igorsk	0:1063a091a062	165	/** I2S Transmit control the TX_MCLK output */
igorsk	0:1063a091a062	166	#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
igorsk	0:1063a091a062	167	/** I2S Receive select clock source */
igorsk	0:1063a091a062	168	#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
igorsk	0:1063a091a062	169	/** I2S Receive control 4-pin mode */
igorsk	0:1063a091a062	170	#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
igorsk	0:1063a091a062	171	/** I2S Receive control the TX_MCLK output */
igorsk	0:1063a091a062	172	#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
igorsk	0:1063a091a062	173
igorsk	0:1063a091a062	174	/**
igorsk	0:1063a091a062	175	* @}
igorsk	0:1063a091a062	176	*/
igorsk	0:1063a091a062	177
igorsk	0:1063a091a062	178	/**
igorsk	0:1063a091a062	179	* @}
igorsk	0:1063a091a062	180	*/
igorsk	0:1063a091a062	181
igorsk	0:1063a091a062	182
igorsk	0:1063a091a062	183	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	184	/** @defgroup I2S_Public_Types
igorsk	0:1063a091a062	185	* @{
igorsk	0:1063a091a062	186	*/
igorsk	0:1063a091a062	187
igorsk	0:1063a091a062	188
igorsk	0:1063a091a062	189	/**
igorsk	0:1063a091a062	190	* @brief I2S configuration structure
igorsk	0:1063a091a062	191	*/
igorsk	0:1063a091a062	192	typedef struct {
igorsk	0:1063a091a062	193	uint8_t CLK_Pin; /**< Clock Pin, should be:
igorsk	0:1063a091a062	194	- I2S_SRX_CLK_P0_4: RX_CLK pin is on P0.4
igorsk	0:1063a091a062	195	- I2S_SRX_CLK_P0_23: RX_CLK pin is on P0.23
igorsk	0:1063a091a062	196	- I2S_STX_CLK_P0_7: TX_CLK pin is on P0.7
igorsk	0:1063a091a062	197	- I2S_STX_CLK_P2_11: TX_CLK pin is on P2.11 */
igorsk	0:1063a091a062	198	uint8_t WS_Pin; /**< Word Select, should be:
igorsk	0:1063a091a062	199	- I2S_SRX_WS_P0_5: RX_WS pin is on P0.5
igorsk	0:1063a091a062	200	- I2S_SRX_WS_P0_24: RX_WS pin is on P0.24
igorsk	0:1063a091a062	201	- I2S_STX_WS_P0_8: TX_WS pin is on P0.8
igorsk	0:1063a091a062	202	- I2S_STX_WS_P2_12: TX_WS pin is on P2.12 */
igorsk	0:1063a091a062	203	uint8_t SDA_Pin; /**< Data, should be:
igorsk	0:1063a091a062	204	- I2S_SRX_SDA_P0_6: RX_SDA pin is on P0.6
igorsk	0:1063a091a062	205	- I2S_SRX_SDA_P0_25: RX_SDA pin is on P0.25
igorsk	0:1063a091a062	206	- I2S_STX_SDA_P0_9: TX_SDA pin is on P0.8
igorsk	0:1063a091a062	207	- I2S_STX_SDA_P2_13: TX_SDA pin is on P2.13 */
igorsk	0:1063a091a062	208	uint8_t MCLK_Pin; /**< Master Clock output, should be:
igorsk	0:1063a091a062	209	- I2S_RX_MCLK_P4_28: RX_MCLK pin is on P4.28
igorsk	0:1063a091a062	210	- I2S_TX_MCLK_P4_29: TX_MCLK pin is on P4.29*/
igorsk	0:1063a091a062	211	}I2S_PinCFG_Type;
igorsk	0:1063a091a062	212
igorsk	0:1063a091a062	213	/**
igorsk	0:1063a091a062	214	* @brief I2S configuration structure definition
igorsk	0:1063a091a062	215	*/
igorsk	0:1063a091a062	216	typedef struct {
igorsk	0:1063a091a062	217	uint8_t wordwidth; /** the number of bytes in data as follow:
igorsk	0:1063a091a062	218	-I2S_WORDWIDTH_8: 8 bit data
igorsk	0:1063a091a062	219	-I2S_WORDWIDTH_16: 16 bit data
igorsk	0:1063a091a062	220	-I2S_WORDWIDTH_32: 32 bit data */
igorsk	0:1063a091a062	221	uint8_t mono; /** Set mono/stereo mode, should be:
igorsk	0:1063a091a062	222	- I2S_STEREO: stereo mode
igorsk	0:1063a091a062	223	- I2S_MONO: mono mode */
igorsk	0:1063a091a062	224	uint8_t stop; /** Disables accesses on FIFOs, should be:
igorsk	0:1063a091a062	225	- I2S_STOP_ENABLE: enable stop mode
igorsk	0:1063a091a062	226	- I2S_STOP_DISABLE: disable stop mode */
igorsk	0:1063a091a062	227	uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
igorsk	0:1063a091a062	228	- I2S_RESET_ENABLE: enable reset mode
igorsk	0:1063a091a062	229	- I2S_RESET_DISABLE: disable reset mode */
igorsk	0:1063a091a062	230	uint8_t ws_sel; /** Set Master/Slave mode, should be:
igorsk	0:1063a091a062	231	- I2S_MASTER_MODE: I2S master mode
igorsk	0:1063a091a062	232	- I2S_SLAVE_MODE: I2S slave mode */
igorsk	0:1063a091a062	233	uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
igorsk	0:1063a091a062	234	- I2S_MUTE_ENABLE: enable mute mode
igorsk	0:1063a091a062	235	- I2S_MUTE_DISABLE: disable mute mode */
igorsk	0:1063a091a062	236	uint8_t Reserved0[2];
igorsk	0:1063a091a062	237	} I2S_CFG_Type;
igorsk	0:1063a091a062	238
igorsk	0:1063a091a062	239	/**
igorsk	0:1063a091a062	240	* @brief I2S DMA configuration structure definition
igorsk	0:1063a091a062	241	*/
igorsk	0:1063a091a062	242	typedef struct {
igorsk	0:1063a091a062	243	uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
igorsk	0:1063a091a062	244	- I2S_DMA_1: DMA1
igorsk	0:1063a091a062	245	- I2S_DMA_2: DMA2 */
igorsk	0:1063a091a062	246	uint8_t depth; /** FIFO level that triggers a DMA request */
igorsk	0:1063a091a062	247	uint8_t Reserved0[2];
igorsk	0:1063a091a062	248	}I2S_DMAConf_Type;
igorsk	0:1063a091a062	249
igorsk	0:1063a091a062	250	/**
igorsk	0:1063a091a062	251	* @brief I2S mode configuration structure definition
igorsk	0:1063a091a062	252	*/
igorsk	0:1063a091a062	253	typedef struct{
igorsk	0:1063a091a062	254	uint8_t clksel; /** Clock source selection, should be:
igorsk	0:1063a091a062	255	- I2S_CLKSEL_0: Select the fractional rate divider clock output
igorsk	0:1063a091a062	256	- I2S_CLKSEL_2: Select the MCLK signal as the clock source */
igorsk	0:1063a091a062	257	uint8_t fpin; /** Select four pin mode, should be:
igorsk	0:1063a091a062	258	- I2S_4PIN_ENABLE: 4-pin enable
igorsk	0:1063a091a062	259	- I2S_4PIN_DISABLE: 4-pin disable */
igorsk	0:1063a091a062	260	uint8_t mcena; /** Select MCLK mode, should be:
igorsk	0:1063a091a062	261	- I2S_MCLK_ENABLE: MCLK enable for output
igorsk	0:1063a091a062	262	- I2S_MCLK_DISABLE: MCLK disable for output */
igorsk	0:1063a091a062	263	uint8_t Reserved;
igorsk	0:1063a091a062	264	}I2S_MODEConf_Type;
igorsk	0:1063a091a062	265
igorsk	0:1063a091a062	266	/** I2S call-back function type definitions */
igorsk	0:1063a091a062	267	typedef void (fnI2SCbs_Type)();
igorsk	0:1063a091a062	268
igorsk	0:1063a091a062	269	/**
igorsk	0:1063a091a062	270	* @}
igorsk	0:1063a091a062	271	*/
igorsk	0:1063a091a062	272
igorsk	0:1063a091a062	273
igorsk	0:1063a091a062	274	/* Public Macros -------------------------------------------------------------- */
igorsk	0:1063a091a062	275	/** @defgroup I2S_Public_Macros
igorsk	0:1063a091a062	276	* @{
igorsk	0:1063a091a062	277	*/
igorsk	0:1063a091a062	278
igorsk	0:1063a091a062	279	/** Macro to determine if it is valid I2S peripheral */
igorsk	0:1063a091a062	280	#define PARAM_I2Sx(n) (((uint32_t )n)==((uint32_t )LPC_I2S))
igorsk	0:1063a091a062	281
igorsk	0:1063a091a062	282	/** Macro to check Data to send valid */
igorsk	0:1063a091a062	283	#define PARAM_I2S_DATA(data) ((data <= 0xFFFFFFFF))
igorsk	0:1063a091a062	284	#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
igorsk	0:1063a091a062	285
igorsk	0:1063a091a062	286	/** SSP0 function pin selection defines */
igorsk	0:1063a091a062	287	#define I2S_SRX_CLK_P0_4 ((uint8_t)(0))
igorsk	0:1063a091a062	288	#define I2S_SRX_WS_P0_5 ((uint8_t)(0))
igorsk	0:1063a091a062	289	#define I2S_SRX_SDA_P0_6 ((uint8_t)(0))
igorsk	0:1063a091a062	290	#define I2S_STX_CLK_P0_7 ((uint8_t)(0))
igorsk	0:1063a091a062	291	#define I2S_STX_WS_P0_8 ((uint8_t)(0))
igorsk	0:1063a091a062	292	#define I2S_STX_SDA_P0_9 ((uint8_t)(0))
igorsk	0:1063a091a062	293
igorsk	0:1063a091a062	294
igorsk	0:1063a091a062	295	#define I2S_SRX_CLK_P0_23 ((uint8_t)(0))
igorsk	0:1063a091a062	296	#define I2S_SRX_WS_P0_24 ((uint8_t)(0))
igorsk	0:1063a091a062	297	#define I2S_SRX_SDA_P0_25 ((uint8_t)(0))
igorsk	0:1063a091a062	298
igorsk	0:1063a091a062	299	#define I2S_STX_CLK_P2_11 ((uint8_t)(2))
igorsk	0:1063a091a062	300	#define I2S_STX_WS_P2_12 ((uint8_t)(2))
igorsk	0:1063a091a062	301	#define I2S_STX_SDA_P2_13 ((uint8_t)(2))
igorsk	0:1063a091a062	302
igorsk	0:1063a091a062	303	#define I2S_TX_MCLK_P4_29 ((uint8_t)(4))
igorsk	0:1063a091a062	304	#define I2S_RX_MCLK_P4_28 ((uint8_t)(4))
igorsk	0:1063a091a062	305
igorsk	0:1063a091a062	306	/** Macro to check PIN parameter */
igorsk	0:1063a091a062	307	#define PARAM_RX_CLK_PIN(n) ((n==I2S_SRX_CLK_P0_4)\|\|(n==I2S_SRX_CLK_P0_23))
igorsk	0:1063a091a062	308	#define PARAM_TX_CLK_PIN(n) ((n==I2S_STX_CLK_P0_7)\|\|(n==I2S_STX_CLK_P2_11))
igorsk	0:1063a091a062	309
igorsk	0:1063a091a062	310	#define PARAM_RX_WS_PIN(n) ((n==I2S_SRX_WS_P0_5)\|\|(n==I2S_SRX_WS_P0_24))
igorsk	0:1063a091a062	311	#define PARAM_TX_WS_PIN(n) ((n==I2S_STX_WS_P0_8)\|\|(n==I2S_STX_WS_P2_12))
igorsk	0:1063a091a062	312
igorsk	0:1063a091a062	313	#define PARAM_RX_SDA_PIN(n) ((n==I2S_SRX_SDA_P0_6)\|\|(n==I2S_SRX_SDA_P0_25))
igorsk	0:1063a091a062	314	#define PARAM_TX_SDA_PIN(n) ((n==I2S_STX_SDA_P0_9)\|\|(n==I2S_STX_SDA_P2_13))
igorsk	0:1063a091a062	315
igorsk	0:1063a091a062	316	#define PARAM_RX_MCLK_PIN(n) (n==I2S_RX_MCLK_P4_28)
igorsk	0:1063a091a062	317	#define PARAM_TX_MCLK_PIN(n) (n==I2S_TX_MCLK_P4_29)
igorsk	0:1063a091a062	318
igorsk	0:1063a091a062	319	/*******************************************************************//
igorsk	0:1063a091a062	320	* I2S configuration parameter defines
igorsk	0:1063a091a062	321	**********************************************************************/
igorsk	0:1063a091a062	322	/** I2S Wordwidth bit */
igorsk	0:1063a091a062	323	#define I2S_WORDWIDTH_8 I2S_DAO_WORDWIDTH_8
igorsk	0:1063a091a062	324	#define I2S_WORDWIDTH_16 I2S_DAO_WORDWIDTH_16
igorsk	0:1063a091a062	325	#define I2S_WORDWIDTH_32 I2S_DAO_WORDWIDTH_32
igorsk	0:1063a091a062	326	#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)\|\|(n==I2S_WORDWIDTH_16)\
igorsk	0:1063a091a062	327	\|\|(n==I2S_WORDWIDTH_32))
igorsk	0:1063a091a062	328
igorsk	0:1063a091a062	329	/** I2S Channel bit */
igorsk	0:1063a091a062	330	#define I2S_STEREO ((uint32_t)(0))
igorsk	0:1063a091a062	331	#define I2S_MONO ((uint32_t)(1))
igorsk	0:1063a091a062	332	#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)\|\|(n==I2S_MONO))
igorsk	0:1063a091a062	333
igorsk	0:1063a091a062	334	/** I2S Master/Slave mode bit */
igorsk	0:1063a091a062	335	#define I2S_MASTER_MODE ((uint8_t)(0))
igorsk	0:1063a091a062	336	#define I2S_SLAVE_MODE ((uint8_t)(1))
igorsk	0:1063a091a062	337	#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)\|\|(n==I2S_SLAVE_MODE))
igorsk	0:1063a091a062	338
igorsk	0:1063a091a062	339	/** I2S Stop bit */
igorsk	0:1063a091a062	340	#define I2S_STOP_ENABLE ((uint8_t)(1))
igorsk	0:1063a091a062	341	#define I2S_STOP_DISABLE ((uint8_t)(0))
igorsk	0:1063a091a062	342	#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)\|\|(n==I2S_STOP_DISABLE))
igorsk	0:1063a091a062	343
igorsk	0:1063a091a062	344	/** I2S Reset bit */
igorsk	0:1063a091a062	345	#define I2S_RESET_ENABLE ((uint8_t)(1))
igorsk	0:1063a091a062	346	#define I2S_RESET_DISABLE ((uint8_t)(0))
igorsk	0:1063a091a062	347	#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)\|\|(n==I2S_RESET_DISABLE))
igorsk	0:1063a091a062	348
igorsk	0:1063a091a062	349	/** I2S Mute bit */
igorsk	0:1063a091a062	350	#define I2S_MUTE_ENABLE ((uint8_t)(1))
igorsk	0:1063a091a062	351	#define I2S_MUTE_DISABLE ((uint8_t)(0))
igorsk	0:1063a091a062	352	#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)\|\|(n==I2S_MUTE_DISABLE))
igorsk	0:1063a091a062	353
igorsk	0:1063a091a062	354	/** I2S Transmit/Receive bit */
igorsk	0:1063a091a062	355	#define I2S_TX_MODE ((uint8_t)(0))
igorsk	0:1063a091a062	356	#define I2S_RX_MODE ((uint8_t)(1))
igorsk	0:1063a091a062	357	#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)\|\|(n==I2S_RX_MODE))
igorsk	0:1063a091a062	358
igorsk	0:1063a091a062	359	/** I2S Clock Select bit */
igorsk	0:1063a091a062	360	#define I2S_CLKSEL_0 ((uint8_t)(0))
igorsk	0:1063a091a062	361	#define I2S_CLKSEL_1 ((uint8_t)(2))
igorsk	0:1063a091a062	362	#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_0)\|\|(n==I2S_CLKSEL_1))
igorsk	0:1063a091a062	363
igorsk	0:1063a091a062	364	/** I2S 4-pin Mode bit */
igorsk	0:1063a091a062	365	#define I2S_4PIN_ENABLE ((uint8_t)(1))
igorsk	0:1063a091a062	366	#define I2S_4PIN_DISABLE ((uint8_t)(0))
igorsk	0:1063a091a062	367	#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)\|\|(n==I2S_4PIN_DISABLE))
igorsk	0:1063a091a062	368
igorsk	0:1063a091a062	369	/** I2S MCLK Enable bit */
igorsk	0:1063a091a062	370	#define I2S_MCLK_ENABLE ((uint8_t)(1))
igorsk	0:1063a091a062	371	#define I2S_MCLK_DISABLE ((uint8_t)(0))
igorsk	0:1063a091a062	372	#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)\|\|(n==I2S_MCLK_DISABLE))
igorsk	0:1063a091a062	373
igorsk	0:1063a091a062	374	/** I2S select DMA bit */
igorsk	0:1063a091a062	375	#define I2S_DMA_1 ((uint8_t)(0))
igorsk	0:1063a091a062	376	#define I2S_DMA_2 ((uint8_t)(1))
igorsk	0:1063a091a062	377	#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)\|\|(n==I2S_DMA_2))
igorsk	0:1063a091a062	378
igorsk	0:1063a091a062	379	#define PARAM_I2S_DMA_DEPTH(n) ((n<=31))
igorsk	0:1063a091a062	380	#define PARAM_I2S_IRQ_LEVEL(n) ((n<=31))
igorsk	0:1063a091a062	381
igorsk	0:1063a091a062	382	#define PARAM_I2S_HALFPERIOD(n) ((n<512))
igorsk	0:1063a091a062	383
igorsk	0:1063a091a062	384	#define PARAM_I2S_BITRATE(n) ((n>=1)&&(n<=64))
igorsk	0:1063a091a062	385
igorsk	0:1063a091a062	386	/**
igorsk	0:1063a091a062	387	* @}
igorsk	0:1063a091a062	388	*/
igorsk	0:1063a091a062	389
igorsk	0:1063a091a062	390
igorsk	0:1063a091a062	391	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	392	/** @defgroup I2S_Public_Functions
igorsk	0:1063a091a062	393	* @{
igorsk	0:1063a091a062	394	*/
igorsk	0:1063a091a062	395
igorsk	0:1063a091a062	396	void I2S_Init(LPC_I2S_TypeDef *I2Sx);
igorsk	0:1063a091a062	397	void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
igorsk	0:1063a091a062	398
igorsk	0:1063a091a062	399	void I2S_Config(LPC_I2S_TypeDef I2Sx, uint8_t TRMode, I2S_CFG_Type ConfigStruct);
igorsk	0:1063a091a062	400	Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
igorsk	0:1063a091a062	401	void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
igorsk	0:1063a091a062	402	void I2S_ModeConfig(LPC_I2S_TypeDef I2Sx, I2S_MODEConf_Type ModeConfig, uint8_t TRMode);
igorsk	0:1063a091a062	403
igorsk	0:1063a091a062	404	void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
igorsk	0:1063a091a062	405	uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
igorsk	0:1063a091a062	406	void I2S_Start(LPC_I2S_TypeDef *I2Sx);
igorsk	0:1063a091a062	407	void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
igorsk	0:1063a091a062	408	void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
igorsk	0:1063a091a062	409	void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
igorsk	0:1063a091a062	410
igorsk	0:1063a091a062	411	void I2S_DMAConfig(LPC_I2S_TypeDef I2Sx, I2S_DMAConf_Type DMAConfig, uint8_t TRMode);
igorsk	0:1063a091a062	412	void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
igorsk	0:1063a091a062	413	void I2S_IRQConfig(LPC_I2S_TypeDef I2Sx, uint8_t TRMode, uint8_t level, fnI2SCbs_Type pfnI2SCbs);
igorsk	0:1063a091a062	414	void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
igorsk	0:1063a091a062	415	void I2S_IntHandler(void);
igorsk	0:1063a091a062	416	uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
igorsk	0:1063a091a062	417
igorsk	0:1063a091a062	418	/**
igorsk	0:1063a091a062	419	* @}
igorsk	0:1063a091a062	420	*/
igorsk	0:1063a091a062	421
igorsk	0:1063a091a062	422
igorsk	0:1063a091a062	423	#ifdef __cplusplus
igorsk	0:1063a091a062	424	}
igorsk	0:1063a091a062	425	#endif
igorsk	0:1063a091a062	426
igorsk	0:1063a091a062	427
igorsk	0:1063a091a062	428	#endif /* LPC17XX_SSP_H_ */
igorsk	0:1063a091a062	429
igorsk	0:1063a091a062	430	/**
igorsk	0:1063a091a062	431	* @}
igorsk	0:1063a091a062	432	*/
igorsk	0:1063a091a062	433
igorsk	0:1063a091a062	434	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_i2s.h@0:1063a091a062, 2010-02-17 (annotated)

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