DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_i2c.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_i2c.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for I2C firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 13. Apr. 2009
igorsk	0:1063a091a062	7	* @author : HieuNguyen
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup I2C
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_I2C_H_
igorsk	0:1063a091a062	28	#define LPC17XX_I2C_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34
igorsk	0:1063a091a062	35	#ifdef __cplusplus
igorsk	0:1063a091a062	36	extern "C"
igorsk	0:1063a091a062	37	{
igorsk	0:1063a091a062	38	#endif
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	42	/** @defgroup I2C_Private_Macros
igorsk	0:1063a091a062	43	* @{
igorsk	0:1063a091a062	44	*/
igorsk	0:1063a091a062	45
igorsk	0:1063a091a062	46	/** @defgroup I2C_REGISTER_BIT_DEFINITIONS
igorsk	0:1063a091a062	47	* @{
igorsk	0:1063a091a062	48	*/
igorsk	0:1063a091a062	49
igorsk	0:1063a091a062	50	/*****************************************************************//
igorsk	0:1063a091a062	51	* I2C Control Set register description
igorsk	0:1063a091a062	52	*********************************************************************/
igorsk	0:1063a091a062	53	#define I2C_I2CONSET_AA ((0x04)) /!< Assert acknowledge flag /
igorsk	0:1063a091a062	54	#define I2C_I2CONSET_SI ((0x08)) /!< I2C interrupt flag /
igorsk	0:1063a091a062	55	#define I2C_I2CONSET_STO ((0x10)) /!< STOP flag /
igorsk	0:1063a091a062	56	#define I2C_I2CONSET_STA ((0x20)) /!< START flag /
igorsk	0:1063a091a062	57	#define I2C_I2CONSET_I2EN ((0x40)) /!< I2C interface enable /
igorsk	0:1063a091a062	58
igorsk	0:1063a091a062	59
igorsk	0:1063a091a062	60	/*****************************************************************//
igorsk	0:1063a091a062	61	* I2C Control Clear register description
igorsk	0:1063a091a062	62	*********************************************************************/
igorsk	0:1063a091a062	63	/** Assert acknowledge Clear bit */
igorsk	0:1063a091a062	64	#define I2C_I2CONCLR_AAC ((1<<2))
igorsk	0:1063a091a062	65	/** I2C interrupt Clear bit */
igorsk	0:1063a091a062	66	#define I2C_I2CONCLR_SIC ((1<<3))
igorsk	0:1063a091a062	67	/** START flag Clear bit */
igorsk	0:1063a091a062	68	#define I2C_I2CONCLR_STAC ((1<<5))
igorsk	0:1063a091a062	69	/** I2C interface Disable bit */
igorsk	0:1063a091a062	70	#define I2C_I2CONCLR_I2ENC ((1<<6))
igorsk	0:1063a091a062	71
igorsk	0:1063a091a062	72
igorsk	0:1063a091a062	73	/******************************************************************//
igorsk	0:1063a091a062	74	* I2C Status Code definition (I2C Status register)
igorsk	0:1063a091a062	75	*********************************************************************/
igorsk	0:1063a091a062	76	/* Return Code in I2C status register */
igorsk	0:1063a091a062	77	#define I2C_STAT_CODE_BITMASK ((0xF8))
igorsk	0:1063a091a062	78
igorsk	0:1063a091a062	79	/* I2C return status code definitions ----------------------------- */
igorsk	0:1063a091a062	80
igorsk	0:1063a091a062	81	/** No relevant information */
igorsk	0:1063a091a062	82	#define I2C_I2STAT_NO_INF ((0xF8))
igorsk	0:1063a091a062	83
igorsk	0:1063a091a062	84	/* Master transmit mode -------------------------------------------- */
igorsk	0:1063a091a062	85	/** A start condition has been transmitted */
igorsk	0:1063a091a062	86	#define I2C_I2STAT_M_TX_START ((0x08))
igorsk	0:1063a091a062	87	/** A repeat start condition has been transmitted */
igorsk	0:1063a091a062	88	#define I2C_I2STAT_M_TX_RESTART ((0x10))
igorsk	0:1063a091a062	89	/** SLA+W has been transmitted, ACK has been received */
igorsk	0:1063a091a062	90	#define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
igorsk	0:1063a091a062	91	/** SLA+W has been transmitted, NACK has been received */
igorsk	0:1063a091a062	92	#define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
igorsk	0:1063a091a062	93	/** Data has been transmitted, ACK has been received */
igorsk	0:1063a091a062	94	#define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
igorsk	0:1063a091a062	95	/** Data has been transmitted, NACK has been received */
igorsk	0:1063a091a062	96	#define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
igorsk	0:1063a091a062	97	/** Arbitration lost in SLA+R/W or Data bytes */
igorsk	0:1063a091a062	98	#define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
igorsk	0:1063a091a062	99
igorsk	0:1063a091a062	100	/* Master receive mode -------------------------------------------- */
igorsk	0:1063a091a062	101	/** A start condition has been transmitted */
igorsk	0:1063a091a062	102	#define I2C_I2STAT_M_RX_START ((0x08))
igorsk	0:1063a091a062	103	/** A repeat start condition has been transmitted */
igorsk	0:1063a091a062	104	#define I2C_I2STAT_M_RX_RESTART ((0x10))
igorsk	0:1063a091a062	105	/** Arbitration lost */
igorsk	0:1063a091a062	106	#define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
igorsk	0:1063a091a062	107	/** SLA+R has been transmitted, ACK has been received */
igorsk	0:1063a091a062	108	#define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
igorsk	0:1063a091a062	109	/** SLA+R has been transmitted, NACK has been received */
igorsk	0:1063a091a062	110	#define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
igorsk	0:1063a091a062	111	/** Data has been received, ACK has been returned */
igorsk	0:1063a091a062	112	#define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
igorsk	0:1063a091a062	113	/** Data has been received, NACK has been return */
igorsk	0:1063a091a062	114	#define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
igorsk	0:1063a091a062	115
igorsk	0:1063a091a062	116	/* Slave receive mode -------------------------------------------- */
igorsk	0:1063a091a062	117	/** Own slave address has been received, ACK has been returned */
igorsk	0:1063a091a062	118	#define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
igorsk	0:1063a091a062	119
igorsk	0:1063a091a062	120	/** Arbitration lost in SLA+R/W as master */
igorsk	0:1063a091a062	121	#define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
igorsk	0:1063a091a062	122	/** Own SLA+W has been received, ACK returned */
igorsk	0:1063a091a062	123	//#define I2C_I2STAT_S_RX_SLAW_ACK ((0x68))
igorsk	0:1063a091a062	124
igorsk	0:1063a091a062	125	/** General call address has been received, ACK has been returned */
igorsk	0:1063a091a062	126	#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
igorsk	0:1063a091a062	127
igorsk	0:1063a091a062	128	/** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
igorsk	0:1063a091a062	129	#define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
igorsk	0:1063a091a062	130	/** General call address has been received, ACK has been returned */
igorsk	0:1063a091a062	131	//#define I2C_I2STAT_S_RX_GENCALL_ACK ((0x78))
igorsk	0:1063a091a062	132
igorsk	0:1063a091a062	133	/** Previously addressed with own SLV address;
igorsk	0:1063a091a062	134	* Data has been received, ACK has been return */
igorsk	0:1063a091a062	135	#define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
igorsk	0:1063a091a062	136	/** Previously addressed with own SLA;
igorsk	0:1063a091a062	137	* Data has been received and NOT ACK has been return */
igorsk	0:1063a091a062	138	#define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
igorsk	0:1063a091a062	139	/** Previously addressed with General Call;
igorsk	0:1063a091a062	140	* Data has been received and ACK has been return */
igorsk	0:1063a091a062	141	#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
igorsk	0:1063a091a062	142	/** Previously addressed with General Call;
igorsk	0:1063a091a062	143	* Data has been received and NOT ACK has been return */
igorsk	0:1063a091a062	144	#define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
igorsk	0:1063a091a062	145	/** A STOP condition or repeated START condition has
igorsk	0:1063a091a062	146	* been received while still addressed as SLV/REC
igorsk	0:1063a091a062	147	* (Slave Receive) or SLV/TRX (Slave Transmit) */
igorsk	0:1063a091a062	148	#define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
igorsk	0:1063a091a062	149
igorsk	0:1063a091a062	150	/** Slave transmit mode */
igorsk	0:1063a091a062	151	/** Own SLA+R has been received, ACK has been returned */
igorsk	0:1063a091a062	152	#define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
igorsk	0:1063a091a062	153
igorsk	0:1063a091a062	154	/** Arbitration lost in SLA+R/W as master */
igorsk	0:1063a091a062	155	#define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
igorsk	0:1063a091a062	156	/** Own SLA+R has been received, ACK has been returned */
igorsk	0:1063a091a062	157	//#define I2C_I2STAT_S_TX_SLAR_ACK ((0xB0))
igorsk	0:1063a091a062	158
igorsk	0:1063a091a062	159	/** Data has been transmitted, ACK has been received */
igorsk	0:1063a091a062	160	#define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
igorsk	0:1063a091a062	161	/** Data has been transmitted, NACK has been received */
igorsk	0:1063a091a062	162	#define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
igorsk	0:1063a091a062	163	/** Last data byte in I2DAT has been transmitted (AA = 0);
igorsk	0:1063a091a062	164	ACK has been received */
igorsk	0:1063a091a062	165	#define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
igorsk	0:1063a091a062	166
igorsk	0:1063a091a062	167	/** Time out in case of using I2C slave mode */
igorsk	0:1063a091a062	168	#define I2C_SLAVE_TIME_OUT 0x10000UL
igorsk	0:1063a091a062	169
igorsk	0:1063a091a062	170	/******************************************************************//
igorsk	0:1063a091a062	171	* I2C Data register definition
igorsk	0:1063a091a062	172	*********************************************************************/
igorsk	0:1063a091a062	173	/** Mask for I2DAT register*/
igorsk	0:1063a091a062	174	#define I2C_I2DAT_BITMASK ((0xFF))
igorsk	0:1063a091a062	175
igorsk	0:1063a091a062	176	/** Idle data value will be send out in slave mode in case of the actual
igorsk	0:1063a091a062	177	* expecting data requested from the master is greater than its sending data
igorsk	0:1063a091a062	178	* length that can be supported */
igorsk	0:1063a091a062	179	#define I2C_I2DAT_IDLE_CHAR (0xFF)
igorsk	0:1063a091a062	180
igorsk	0:1063a091a062	181
igorsk	0:1063a091a062	182	/******************************************************************//
igorsk	0:1063a091a062	183	* I2C Monitor mode control register description
igorsk	0:1063a091a062	184	*********************************************************************/
igorsk	0:1063a091a062	185	#define I2C_I2MMCTRL_MM_ENA ((1<<0)) /*< Monitor mode enable /
igorsk	0:1063a091a062	186	#define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /*< SCL output enable /
igorsk	0:1063a091a062	187	#define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /*< Select interrupt register match /
igorsk	0:1063a091a062	188	#define I2C_I2MMCTRL_BITMASK ((0x07)) /*< Mask for I2MMCTRL register /
igorsk	0:1063a091a062	189
igorsk	0:1063a091a062	190
igorsk	0:1063a091a062	191	/******************************************************************//
igorsk	0:1063a091a062	192	* I2C Data buffer register description
igorsk	0:1063a091a062	193	*********************************************************************/
igorsk	0:1063a091a062	194	/** I2C Data buffer register bit mask */
igorsk	0:1063a091a062	195	#define I2DATA_BUFFER_BITMASK ((0xFF))
igorsk	0:1063a091a062	196
igorsk	0:1063a091a062	197
igorsk	0:1063a091a062	198	/******************************************************************//
igorsk	0:1063a091a062	199	* I2C Slave Address registers definition
igorsk	0:1063a091a062	200	*********************************************************************/
igorsk	0:1063a091a062	201	/** General Call enable bit */
igorsk	0:1063a091a062	202	#define I2C_I2ADR_GC ((1<<0))
igorsk	0:1063a091a062	203	/** I2C Slave Address registers bit mask */
igorsk	0:1063a091a062	204	#define I2C_I2ADR_BITMASK ((0xFF))
igorsk	0:1063a091a062	205
igorsk	0:1063a091a062	206
igorsk	0:1063a091a062	207	/******************************************************************//
igorsk	0:1063a091a062	208	* I2C Mask Register definition
igorsk	0:1063a091a062	209	*********************************************************************/
igorsk	0:1063a091a062	210	/** I2C Mask Register mask field */
igorsk	0:1063a091a062	211	#define I2C_I2MASK_MASK(n) ((n&0xFE))
igorsk	0:1063a091a062	212
igorsk	0:1063a091a062	213
igorsk	0:1063a091a062	214	/******************************************************************//
igorsk	0:1063a091a062	215	* I2C SCL HIGH duty cycle Register definition
igorsk	0:1063a091a062	216	*********************************************************************/
igorsk	0:1063a091a062	217	/** I2C SCL HIGH duty cycle Register bit mask */
igorsk	0:1063a091a062	218	#define I2C_I2SCLH_BITMASK ((0xFFFF))
igorsk	0:1063a091a062	219
igorsk	0:1063a091a062	220
igorsk	0:1063a091a062	221	/******************************************************************//
igorsk	0:1063a091a062	222	* I2C SCL LOW duty cycle Register definition
igorsk	0:1063a091a062	223	*********************************************************************/
igorsk	0:1063a091a062	224	/** I2C SCL LOW duty cycle Register bit mask */
igorsk	0:1063a091a062	225	#define I2C_I2SCLL_BITMASK ((0xFFFF))
igorsk	0:1063a091a062	226
igorsk	0:1063a091a062	227	/**
igorsk	0:1063a091a062	228	* @}
igorsk	0:1063a091a062	229	*/
igorsk	0:1063a091a062	230
igorsk	0:1063a091a062	231	/**
igorsk	0:1063a091a062	232	* @}
igorsk	0:1063a091a062	233	*/
igorsk	0:1063a091a062	234
igorsk	0:1063a091a062	235
igorsk	0:1063a091a062	236
igorsk	0:1063a091a062	237	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	238	/** @defgroup I2C_Public_Types
igorsk	0:1063a091a062	239	* @{
igorsk	0:1063a091a062	240	*/
igorsk	0:1063a091a062	241
igorsk	0:1063a091a062	242	/** @brief I2C Own slave address setting structure */
igorsk	0:1063a091a062	243	typedef struct {
igorsk	0:1063a091a062	244	uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
igorsk	0:1063a091a062	245	should be in range from 0..3
igorsk	0:1063a091a062	246	*/
igorsk	0:1063a091a062	247	uint8_t SlaveAddr_7bit; /*< Value of 7-bit slave address /
igorsk	0:1063a091a062	248	uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
igorsk	0:1063a091a062	249	when I2C control being in Slave mode, should be:
igorsk	0:1063a091a062	250	- ENABLE: Enable General Call function.
igorsk	0:1063a091a062	251	- DISABLE: Disable General Call function.
igorsk	0:1063a091a062	252	*/
igorsk	0:1063a091a062	253	uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
igorsk	0:1063a091a062	254	which is set to '1' will cause an automatic compare on
igorsk	0:1063a091a062	255	the corresponding bit of the received address when it
igorsk	0:1063a091a062	256	is compared to the SlaveAddr_7bit value associated with this
igorsk	0:1063a091a062	257	mask register. In other words, bits in SlaveAddr_7bit value
igorsk	0:1063a091a062	258	which are masked are not taken into account in determining
igorsk	0:1063a091a062	259	an address match
igorsk	0:1063a091a062	260	*/
igorsk	0:1063a091a062	261	} I2C_OWNSLAVEADDR_CFG_Type;
igorsk	0:1063a091a062	262
igorsk	0:1063a091a062	263
igorsk	0:1063a091a062	264	/** @brief Master transfer setup data structure definitions */
igorsk	0:1063a091a062	265	typedef struct
igorsk	0:1063a091a062	266	{
igorsk	0:1063a091a062	267	uint32_t sl_addr7bit; /*< Slave address in 7bit mode /
igorsk	0:1063a091a062	268	uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
igorsk	0:1063a091a062	269	is not used */
igorsk	0:1063a091a062	270	uint32_t tx_length; /**< Transmit data length - 0 if data transmit
igorsk	0:1063a091a062	271	is not used*/
igorsk	0:1063a091a062	272	uint32_t tx_count; /*< Current Transmit data counter /
igorsk	0:1063a091a062	273	uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
igorsk	0:1063a091a062	274	is not used */
igorsk	0:1063a091a062	275	uint32_t rx_length; /**< Receive data length - 0 if data receive is
igorsk	0:1063a091a062	276	not used */
igorsk	0:1063a091a062	277	uint32_t rx_count; /*< Current Receive data counter /
igorsk	0:1063a091a062	278	uint32_t retransmissions_max; /*< Max Re-Transmission value /
igorsk	0:1063a091a062	279	uint32_t retransmissions_count; /*< Current Re-Transmission counter /
igorsk	0:1063a091a062	280	uint32_t status; /*< Current status of I2C activity /
igorsk	0:1063a091a062	281	void (callback)(void); /*< Pointer to Call back function when transmission complete
igorsk	0:1063a091a062	282	used in interrupt transfer mode */
igorsk	0:1063a091a062	283	} I2C_M_SETUP_Type;
igorsk	0:1063a091a062	284
igorsk	0:1063a091a062	285
igorsk	0:1063a091a062	286	/** @brief Slave transfer setup data structure definitions */
igorsk	0:1063a091a062	287	typedef struct
igorsk	0:1063a091a062	288	{
igorsk	0:1063a091a062	289	uint8_t* tx_data;
igorsk	0:1063a091a062	290	uint32_t tx_length;
igorsk	0:1063a091a062	291	uint32_t tx_count;
igorsk	0:1063a091a062	292	uint8_t* rx_data;
igorsk	0:1063a091a062	293	uint32_t rx_length;
igorsk	0:1063a091a062	294	uint32_t rx_count;
igorsk	0:1063a091a062	295	uint32_t status;
igorsk	0:1063a091a062	296	void (*callback)(void);
igorsk	0:1063a091a062	297	} I2C_S_SETUP_Type;
igorsk	0:1063a091a062	298
igorsk	0:1063a091a062	299	/**
igorsk	0:1063a091a062	300	* @brief Transfer option type definitions
igorsk	0:1063a091a062	301	*/
igorsk	0:1063a091a062	302	typedef enum {
igorsk	0:1063a091a062	303	I2C_TRANSFER_POLLING = 0, /*< Transfer in polling mode /
igorsk	0:1063a091a062	304	I2C_TRANSFER_INTERRUPT /*< Transfer in interrupt mode /
igorsk	0:1063a091a062	305	} I2C_TRANSFER_OPT_Type;
igorsk	0:1063a091a062	306
igorsk	0:1063a091a062	307
igorsk	0:1063a091a062	308	/**
igorsk	0:1063a091a062	309	* @}
igorsk	0:1063a091a062	310	*/
igorsk	0:1063a091a062	311
igorsk	0:1063a091a062	312
igorsk	0:1063a091a062	313	/* Public Macros -------------------------------------------------------------- */
igorsk	0:1063a091a062	314	/** @defgroup I2C_Public_Macros
igorsk	0:1063a091a062	315	* @{
igorsk	0:1063a091a062	316	*/
igorsk	0:1063a091a062	317
igorsk	0:1063a091a062	318	#define PARAM_I2C_SLAVEADDR_CH(n) ((n<=3))
igorsk	0:1063a091a062	319
igorsk	0:1063a091a062	320	/** Macro to determine if it is valid SSP port number */
igorsk	0:1063a091a062	321	#define PARAM_I2Cx(n) ((((uint32_t )n)==((uint32_t )LPC_I2C0)) \
igorsk	0:1063a091a062	322	\|\| (((uint32_t )n)==((uint32_t )LPC_I2C1)) \
igorsk	0:1063a091a062	323	\|\| (((uint32_t )n)==((uint32_t )LPC_I2C2)))
igorsk	0:1063a091a062	324
igorsk	0:1063a091a062	325	/* I2C status values */
igorsk	0:1063a091a062	326	#define I2C_SETUP_STATUS_ARBF (1<<8) /*< Arbitration false /
igorsk	0:1063a091a062	327	#define I2C_SETUP_STATUS_NOACKF (1<<9) /*< No ACK returned /
igorsk	0:1063a091a062	328	#define I2C_SETUP_STATUS_DONE (1<<10) /*< Status DONE /
igorsk	0:1063a091a062	329
igorsk	0:1063a091a062	330
igorsk	0:1063a091a062	331	/*******************************************************************//
igorsk	0:1063a091a062	332	* I2C monitor control configuration defines
igorsk	0:1063a091a062	333	**********************************************************************/
igorsk	0:1063a091a062	334	#define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /*< SCL output enable /
igorsk	0:1063a091a062	335	#define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /*< Select interrupt register match /
igorsk	0:1063a091a062	336
igorsk	0:1063a091a062	337	#define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) \|\| (I2C_MONITOR_CFG_MATCHALL))
igorsk	0:1063a091a062	338
igorsk	0:1063a091a062	339	/**
igorsk	0:1063a091a062	340	* @}
igorsk	0:1063a091a062	341	*/
igorsk	0:1063a091a062	342
igorsk	0:1063a091a062	343
igorsk	0:1063a091a062	344	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	345	/** @defgroup I2C_Public_Functions
igorsk	0:1063a091a062	346	* @{
igorsk	0:1063a091a062	347	*/
igorsk	0:1063a091a062	348
igorsk	0:1063a091a062	349	void I2C_SetClock (LPC_I2C_TypeDef *I2Cx, uint32_t target_clock);
igorsk	0:1063a091a062	350	void I2C_DeInit(LPC_I2C_TypeDef* I2Cx);
igorsk	0:1063a091a062	351	void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate);
igorsk	0:1063a091a062	352	void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, FunctionalState NewState);
igorsk	0:1063a091a062	353
igorsk	0:1063a091a062	354	Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \
igorsk	0:1063a091a062	355	I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
igorsk	0:1063a091a062	356	Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \
igorsk	0:1063a091a062	357	I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
igorsk	0:1063a091a062	358
igorsk	0:1063a091a062	359	void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef I2Cx, I2C_OWNSLAVEADDR_CFG_Type OwnSlaveAddrConfigStruct);
igorsk	0:1063a091a062	360	uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx);
igorsk	0:1063a091a062	361
igorsk	0:1063a091a062	362	void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
igorsk	0:1063a091a062	363	void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState);
igorsk	0:1063a091a062	364	uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx);
igorsk	0:1063a091a062	365
igorsk	0:1063a091a062	366	void I2C0_StdIntHandler(void);
igorsk	0:1063a091a062	367	void I2C1_StdIntHandler(void);
igorsk	0:1063a091a062	368	void I2C2_StdIntHandler(void);
igorsk	0:1063a091a062	369
igorsk	0:1063a091a062	370
igorsk	0:1063a091a062	371	/**
igorsk	0:1063a091a062	372	* @}
igorsk	0:1063a091a062	373	*/
igorsk	0:1063a091a062	374
igorsk	0:1063a091a062	375
igorsk	0:1063a091a062	376	#ifdef __cplusplus
igorsk	0:1063a091a062	377	}
igorsk	0:1063a091a062	378	#endif
igorsk	0:1063a091a062	379
igorsk	0:1063a091a062	380	#endif /* LPC17XX_I2C_H_ */
igorsk	0:1063a091a062	381
igorsk	0:1063a091a062	382	/**
igorsk	0:1063a091a062	383	* @}
igorsk	0:1063a091a062	384	*/
igorsk	0:1063a091a062	385
igorsk	0:1063a091a062	386	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_i2c.h@0:1063a091a062, 2010-02-17 (annotated)

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