DriverLibrary - NXP's driver library for LPC17xx, ported to mbed'…

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Igor Skochinsky / Mbed 2 deprecated DriverLibrary

NXP's driver library for LPC17xx, ported to mbed's online compiler. Not tested! I had to fix a lot of warings and found a couple of pretty obvious bugs, so the chances are there are more. Original: http://ics.nxp.com/support/documents/microcontrollers/zip/lpc17xx.cmsis.driver.library.zip

Dependencies: mbed

include/lpc17xx_gpdma.h@0:1063a091a062, 2010-02-17 (annotated)

Committer:: igorsk
Date:: Wed Feb 17 16:22:39 2010 +0000
Revision:: 0:1063a091a062

Who changed what in which revision?

User	Revision	Line number	New contents of line
igorsk	0:1063a091a062	1	/*********************************************************************//
igorsk	0:1063a091a062	2	* @file : lpc17xx_gpdma.h
igorsk	0:1063a091a062	3	* @brief : Contains all macro definitions and function prototypes
igorsk	0:1063a091a062	4	* support for GPDMA firmware library on LPC17xx
igorsk	0:1063a091a062	5	* @version : 1.0
igorsk	0:1063a091a062	6	* @date : 20. Apr. 2009
igorsk	0:1063a091a062	7	* @author : HieuNguyen
igorsk	0:1063a091a062	8	**************************************************************************
igorsk	0:1063a091a062	9	* Software that is described herein is for illustrative purposes only
igorsk	0:1063a091a062	10	* which provides customers with programming information regarding the
igorsk	0:1063a091a062	11	* products. This software is supplied "AS IS" without any warranties.
igorsk	0:1063a091a062	12	* NXP Semiconductors assumes no responsibility or liability for the
igorsk	0:1063a091a062	13	* use of the software, conveys no license or title under any patent,
igorsk	0:1063a091a062	14	* copyright, or mask work right to the product. NXP Semiconductors
igorsk	0:1063a091a062	15	* reserves the right to make changes in the software without
igorsk	0:1063a091a062	16	* notification. NXP Semiconductors also make no representation or
igorsk	0:1063a091a062	17	* warranty that such application will be suitable for the specified
igorsk	0:1063a091a062	18	* use without further testing or modification.
igorsk	0:1063a091a062	19	**************************************************************************/
igorsk	0:1063a091a062	20
igorsk	0:1063a091a062	21	/* Peripheral group ----------------------------------------------------------- */
igorsk	0:1063a091a062	22	/** @defgroup GPDMA
igorsk	0:1063a091a062	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
igorsk	0:1063a091a062	24	* @{
igorsk	0:1063a091a062	25	*/
igorsk	0:1063a091a062	26
igorsk	0:1063a091a062	27	#ifndef LPC17XX_GPDMA_H_
igorsk	0:1063a091a062	28	#define LPC17XX_GPDMA_H_
igorsk	0:1063a091a062	29
igorsk	0:1063a091a062	30	/* Includes ------------------------------------------------------------------- */
igorsk	0:1063a091a062	31	#include "cmsis.h"
igorsk	0:1063a091a062	32	#include "lpc_types.h"
igorsk	0:1063a091a062	33
igorsk	0:1063a091a062	34
igorsk	0:1063a091a062	35	#ifdef __cplusplus
igorsk	0:1063a091a062	36	extern "C"
igorsk	0:1063a091a062	37	{
igorsk	0:1063a091a062	38	#endif
igorsk	0:1063a091a062	39
igorsk	0:1063a091a062	40
igorsk	0:1063a091a062	41	/* Private Macros ------------------------------------------------------------- */
igorsk	0:1063a091a062	42	/** @defgroup GPDMA_Private_Macros
igorsk	0:1063a091a062	43	* @{
igorsk	0:1063a091a062	44	*/
igorsk	0:1063a091a062	45
igorsk	0:1063a091a062	46	/** @defgroup DMA_REGISTER_BIT_DEFINITIONS
igorsk	0:1063a091a062	47	* @{
igorsk	0:1063a091a062	48	*/
igorsk	0:1063a091a062	49
igorsk	0:1063a091a062	50	/** Macros define for DMA interrupt */
igorsk	0:1063a091a062	51	/** DMA Interrupt Status register */
igorsk	0:1063a091a062	52	#define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	53	#define GPDMA_DMACIntStat_BITMASK ((0xFF))
igorsk	0:1063a091a062	54
igorsk	0:1063a091a062	55	/** DMA Interrupt Terminal Count Request Status register */
igorsk	0:1063a091a062	56	#define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	57	#define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
igorsk	0:1063a091a062	58
igorsk	0:1063a091a062	59	/** DMA Interrupt Terminal Count Request Clear register */
igorsk	0:1063a091a062	60	#define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	61	#define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
igorsk	0:1063a091a062	62
igorsk	0:1063a091a062	63	/** DMA Interrupt Error Status register */
igorsk	0:1063a091a062	64	#define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	65	#define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
igorsk	0:1063a091a062	66
igorsk	0:1063a091a062	67	/** DMA Interrupt Error Clear register */
igorsk	0:1063a091a062	68	#define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	69	#define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
igorsk	0:1063a091a062	70
igorsk	0:1063a091a062	71	/** DMA Raw Interrupt Terminal Count Status register */
igorsk	0:1063a091a062	72	#define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	73	#define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
igorsk	0:1063a091a062	74
igorsk	0:1063a091a062	75	/** DMA Raw Error Interrupt Status register */
igorsk	0:1063a091a062	76	#define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	77	#define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
igorsk	0:1063a091a062	78
igorsk	0:1063a091a062	79	/** DMA Enabled Channel register */
igorsk	0:1063a091a062	80	#define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
igorsk	0:1063a091a062	81	#define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
igorsk	0:1063a091a062	82
igorsk	0:1063a091a062	83
igorsk	0:1063a091a062	84	/** Macro defines for DMA Software Burst Request register */
igorsk	0:1063a091a062	85	#define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
igorsk	0:1063a091a062	86	#define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
igorsk	0:1063a091a062	87
igorsk	0:1063a091a062	88	/** Macro defines for DMA Software Single Request register */
igorsk	0:1063a091a062	89	#define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
igorsk	0:1063a091a062	90	#define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
igorsk	0:1063a091a062	91
igorsk	0:1063a091a062	92	/** Macro defines for DMA Software Last Burst Request register */
igorsk	0:1063a091a062	93	#define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
igorsk	0:1063a091a062	94	#define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
igorsk	0:1063a091a062	95
igorsk	0:1063a091a062	96	/** Macro defines for DMA Software Last Single Request register */
igorsk	0:1063a091a062	97	#define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
igorsk	0:1063a091a062	98	#define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
igorsk	0:1063a091a062	99
igorsk	0:1063a091a062	100	/** DMA Configuration register bit description*/
igorsk	0:1063a091a062	101	#define GPDMA_DMACConfig_E ((0x01)) /*< DMA Controller enable/
igorsk	0:1063a091a062	102	#define GPDMA_DMACConfig_M ((0x02)) /*< AHB Master endianness configuration/
igorsk	0:1063a091a062	103	#define GPDMA_DMACConfig_BITMASK ((0x03))
igorsk	0:1063a091a062	104
igorsk	0:1063a091a062	105
igorsk	0:1063a091a062	106	/** Macro defines for DMA Synchronization register */
igorsk	0:1063a091a062	107	#define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
igorsk	0:1063a091a062	108	#define GPDMA_DMACSync_BITMASK ((0xFFFF))
igorsk	0:1063a091a062	109
igorsk	0:1063a091a062	110	/** Macro defines for DMA Request Select register */
igorsk	0:1063a091a062	111	#define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
igorsk	0:1063a091a062	112	#define GPDMA_DMAReqSel_BITMASK ((0xFF))
igorsk	0:1063a091a062	113
igorsk	0:1063a091a062	114	/** DMA Channel Linked List Item registers bit mask*/
igorsk	0:1063a091a062	115	#define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
igorsk	0:1063a091a062	116
igorsk	0:1063a091a062	117	/** DMA channel control registers bit description */
igorsk	0:1063a091a062	118	#define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /*< Transfer size/
igorsk	0:1063a091a062	119	#define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /*< Source burst size/
igorsk	0:1063a091a062	120	#define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /*< Destination burst size/
igorsk	0:1063a091a062	121	#define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /*< Source transfer width/
igorsk	0:1063a091a062	122	#define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /*< Destination transfer width/
igorsk	0:1063a091a062	123	#define GPDMA_DMACCxControl_SI ((1UL<<26)) /*< Source increment/
igorsk	0:1063a091a062	124	#define GPDMA_DMACCxControl_DI ((1UL<<27)) /*< Destination increment/
igorsk	0:1063a091a062	125	#define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /*< Indicates that the access is in user mode or privileged mode/
igorsk	0:1063a091a062	126	#define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /*< Indicates that the access is bufferable or not bufferable/
igorsk	0:1063a091a062	127	#define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /*< Indicates that the access is cacheable or not cacheable/
igorsk	0:1063a091a062	128	#define GPDMA_DMACCxControl_I ((1UL<<31)) /*< Terminal count interrupt enable bit /
igorsk	0:1063a091a062	129	/** DMA channel control registers bit mask */
igorsk	0:1063a091a062	130	#define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
igorsk	0:1063a091a062	131
igorsk	0:1063a091a062	132
igorsk	0:1063a091a062	133	/** DMA Channel Configuration registers bit description*/
igorsk	0:1063a091a062	134	#define GPDMA_DMACCxConfig_E ((1UL<<0)) /*< DMA control enable/
igorsk	0:1063a091a062	135	#define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /*< Source peripheral/
igorsk	0:1063a091a062	136	#define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /*< Destination peripheral/
igorsk	0:1063a091a062	137	#define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /*< This value indicates the type of transfer/
igorsk	0:1063a091a062	138	#define GPDMA_DMACCxConfig_IE ((1UL<<14)) /*< Interrupt error mask/
igorsk	0:1063a091a062	139	#define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /*< Terminal count interrupt mask/
igorsk	0:1063a091a062	140	#define GPDMA_DMACCxConfig_L ((1UL<<16)) /*< Lock/
igorsk	0:1063a091a062	141	#define GPDMA_DMACCxConfig_A ((1UL<<17)) /*< Active/
igorsk	0:1063a091a062	142	#define GPDMA_DMACCxConfig_H ((1UL<<18)) /*< Halt/
igorsk	0:1063a091a062	143	/** DMA Channel Configuration registers bit mask */
igorsk	0:1063a091a062	144	#define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
igorsk	0:1063a091a062	145
igorsk	0:1063a091a062	146
igorsk	0:1063a091a062	147	/**
igorsk	0:1063a091a062	148	* @}
igorsk	0:1063a091a062	149	*/
igorsk	0:1063a091a062	150
igorsk	0:1063a091a062	151	/**
igorsk	0:1063a091a062	152	* @}
igorsk	0:1063a091a062	153	*/
igorsk	0:1063a091a062	154
igorsk	0:1063a091a062	155
igorsk	0:1063a091a062	156	/* Public Types --------------------------------------------------------------- */
igorsk	0:1063a091a062	157	/** @defgroup GPDMA_Public_Types
igorsk	0:1063a091a062	158	* @{
igorsk	0:1063a091a062	159	*/
igorsk	0:1063a091a062	160
igorsk	0:1063a091a062	161
igorsk	0:1063a091a062	162	/**
igorsk	0:1063a091a062	163	* @brief GPDMA Channel configuration structure type definition
igorsk	0:1063a091a062	164	*/
igorsk	0:1063a091a062	165	typedef struct {
igorsk	0:1063a091a062	166	uint32_t ChannelNum; /**< DMA channel number, should be in
igorsk	0:1063a091a062	167	range from 0 to 7.
igorsk	0:1063a091a062	168	Note: DMA channel 0 has the highest priority
igorsk	0:1063a091a062	169	and DMA channel 7 the lowest priority.
igorsk	0:1063a091a062	170	*/
igorsk	0:1063a091a062	171	uint32_t TransferSize; /*< Length/Size of transfer /
igorsk	0:1063a091a062	172	uint32_t TransferWidth; /*< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only /
igorsk	0:1063a091a062	173	uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
igorsk	0:1063a091a062	174	GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
igorsk	0:1063a091a062	175	uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
igorsk	0:1063a091a062	176	GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
igorsk	0:1063a091a062	177	uint32_t TransferType; /**< Transfer Type, should be one of the following:
igorsk	0:1063a091a062	178	- GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
igorsk	0:1063a091a062	179	- GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
igorsk	0:1063a091a062	180	- GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
igorsk	0:1063a091a062	181	- GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
igorsk	0:1063a091a062	182	*/
igorsk	0:1063a091a062	183	uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
igorsk	0:1063a091a062	184	GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
igorsk	0:1063a091a062	185	following:
igorsk	0:1063a091a062	186	- GPDMA_CONN_SSP0_Tx: SSP0, Tx
igorsk	0:1063a091a062	187	- GPDMA_CONN_SSP0_Rx: SSP0, Rx
igorsk	0:1063a091a062	188	- GPDMA_CONN_SSP1_Tx: SSP1, Tx
igorsk	0:1063a091a062	189	- GPDMA_CONN_SSP1_Rx: SSP1, Rx
igorsk	0:1063a091a062	190	- GPDMA_CONN_ADC: ADC
igorsk	0:1063a091a062	191	- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
igorsk	0:1063a091a062	192	- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
igorsk	0:1063a091a062	193	- GPDMA_CONN_DAC: DAC
igorsk	0:1063a091a062	194	- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
igorsk	0:1063a091a062	195	- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
igorsk	0:1063a091a062	196	- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
igorsk	0:1063a091a062	197	- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
igorsk	0:1063a091a062	198	- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
igorsk	0:1063a091a062	199	- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
igorsk	0:1063a091a062	200	- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
igorsk	0:1063a091a062	201	- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
igorsk	0:1063a091a062	202	*/
igorsk	0:1063a091a062	203	uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
igorsk	0:1063a091a062	204	GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
igorsk	0:1063a091a062	205	following:
igorsk	0:1063a091a062	206	- GPDMA_CONN_SSP0_Tx: SSP0, Tx
igorsk	0:1063a091a062	207	- GPDMA_CONN_SSP0_Rx: SSP0, Rx
igorsk	0:1063a091a062	208	- GPDMA_CONN_SSP1_Tx: SSP1, Tx
igorsk	0:1063a091a062	209	- GPDMA_CONN_SSP1_Rx: SSP1, Rx
igorsk	0:1063a091a062	210	- GPDMA_CONN_ADC: ADC
igorsk	0:1063a091a062	211	- GPDMA_CONN_I2S_Channel_0: I2S Channel 0
igorsk	0:1063a091a062	212	- GPDMA_CONN_I2S_Channel_1: I2S Channel 1
igorsk	0:1063a091a062	213	- GPDMA_CONN_DAC: DAC
igorsk	0:1063a091a062	214	- GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
igorsk	0:1063a091a062	215	- GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
igorsk	0:1063a091a062	216	- GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
igorsk	0:1063a091a062	217	- GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
igorsk	0:1063a091a062	218	- GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
igorsk	0:1063a091a062	219	- GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
igorsk	0:1063a091a062	220	- GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
igorsk	0:1063a091a062	221	- GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
igorsk	0:1063a091a062	222	*/
igorsk	0:1063a091a062	223	uint32_t DMALLI; /**< Linker List Item structure data address
igorsk	0:1063a091a062	224	if there's no Linker List, set as '0'
igorsk	0:1063a091a062	225	*/
igorsk	0:1063a091a062	226	} GPDMA_Channel_CFG_Type;
igorsk	0:1063a091a062	227
igorsk	0:1063a091a062	228
igorsk	0:1063a091a062	229	/**
igorsk	0:1063a091a062	230	* @brief GPDMA Linker List Item structure type definition
igorsk	0:1063a091a062	231	*/
igorsk	0:1063a091a062	232	typedef struct {
igorsk	0:1063a091a062	233	uint32_t SrcAddr; /*< Source Address /
igorsk	0:1063a091a062	234	uint32_t DstAddr; /*< Destination address /
igorsk	0:1063a091a062	235	uint32_t NextLLI; /*< Next LLI address, otherwise set to '0' /
igorsk	0:1063a091a062	236	uint32_t Control; /*< GPDMA Control of this LLI /
igorsk	0:1063a091a062	237	} GPDMA_LLI_Type;
igorsk	0:1063a091a062	238
igorsk	0:1063a091a062	239
igorsk	0:1063a091a062	240	/** GPDMA call-back function type definitions */
igorsk	0:1063a091a062	241	typedef void (fnGPDMACbs_Type)(uint32_t channelStatus);
igorsk	0:1063a091a062	242
igorsk	0:1063a091a062	243
igorsk	0:1063a091a062	244	/**
igorsk	0:1063a091a062	245	* @}
igorsk	0:1063a091a062	246	*/
igorsk	0:1063a091a062	247
igorsk	0:1063a091a062	248
igorsk	0:1063a091a062	249	/* Public Macros -------------------------------------------------------------- */
igorsk	0:1063a091a062	250	/** @defgroup GPDMA_Public_Macros
igorsk	0:1063a091a062	251	* @{
igorsk	0:1063a091a062	252	*/
igorsk	0:1063a091a062	253
igorsk	0:1063a091a062	254	#define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7))
igorsk	0:1063a091a062	255
igorsk	0:1063a091a062	256	/** DMA Connection number definitions */
igorsk	0:1063a091a062	257	#define GPDMA_CONN_SSP0_Tx ((0UL)) /*< SSP0 Tx /
igorsk	0:1063a091a062	258	#define GPDMA_CONN_SSP0_Rx ((1UL)) /*< SSP0 Rx /
igorsk	0:1063a091a062	259	#define GPDMA_CONN_SSP1_Tx ((2UL)) /*< SSP1 Tx /
igorsk	0:1063a091a062	260	#define GPDMA_CONN_SSP1_Rx ((3UL)) /*< SSP1 Rx /
igorsk	0:1063a091a062	261	#define GPDMA_CONN_ADC ((4UL)) /*< ADC /
igorsk	0:1063a091a062	262	#define GPDMA_CONN_I2S_Channel_0 ((5UL)) /*< I2S channel 0 /
igorsk	0:1063a091a062	263	#define GPDMA_CONN_I2S_Channel_1 ((6UL)) /*< I2S channel 1 /
igorsk	0:1063a091a062	264	#define GPDMA_CONN_DAC ((7UL)) /*< DAC /
igorsk	0:1063a091a062	265	#define GPDMA_CONN_UART0_Tx ((8UL)) /*< UART0 Tx /
igorsk	0:1063a091a062	266	#define GPDMA_CONN_UART0_Rx ((9UL)) /*< UART0 Rx /
igorsk	0:1063a091a062	267	#define GPDMA_CONN_UART1_Tx ((10UL)) /*< UART1 Tx /
igorsk	0:1063a091a062	268	#define GPDMA_CONN_UART1_Rx ((11UL)) /*< UART1 Rx /
igorsk	0:1063a091a062	269	#define GPDMA_CONN_UART2_Tx ((12UL)) /*< UART2 Tx /
igorsk	0:1063a091a062	270	#define GPDMA_CONN_UART2_Rx ((13UL)) /*< UART2 Rx /
igorsk	0:1063a091a062	271	#define GPDMA_CONN_UART3_Tx ((14UL)) /*< UART3 Tx /
igorsk	0:1063a091a062	272	#define GPDMA_CONN_UART3_Rx ((15UL)) /*< UART3 Rx /
igorsk	0:1063a091a062	273	#define GPDMA_CONN_MAT0_0 ((16UL)) /*< MAT0.0 /
igorsk	0:1063a091a062	274	#define GPDMA_CONN_MAT0_1 ((17UL)) /*< MAT0.1 /
igorsk	0:1063a091a062	275	#define GPDMA_CONN_MAT1_0 ((18UL)) /*< MAT1.0 /
igorsk	0:1063a091a062	276	#define GPDMA_CONN_MAT1_1 ((19UL)) /*< MAT1.1 /
igorsk	0:1063a091a062	277	#define GPDMA_CONN_MAT2_0 ((20UL)) /*< MAT2.0 /
igorsk	0:1063a091a062	278	#define GPDMA_CONN_MAT2_1 ((21UL)) /*< MAT2.1 /
igorsk	0:1063a091a062	279	#define GPDMA_CONN_MAT3_0 ((22UL)) /*< MAT3.0 /
igorsk	0:1063a091a062	280	#define GPDMA_CONN_MAT3_1 ((23UL)) /*< MAT3.1 /
igorsk	0:1063a091a062	281
igorsk	0:1063a091a062	282	#define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) \|\| (n==GPDMA_CONN_SSP0_Rx) \
igorsk	0:1063a091a062	283	\|\| (n==GPDMA_CONN_SSP1_Tx) \|\| (n==GPDMA_CONN_SSP1_Rx) \
igorsk	0:1063a091a062	284	\|\| (n==GPDMA_CONN_ADC) \|\| (n==GPDMA_CONN_I2S_Channel_0) \
igorsk	0:1063a091a062	285	\|\| (n==GPDMA_CONN_I2S_Channel_1) \|\| (n==GPDMA_CONN_DAC) \
igorsk	0:1063a091a062	286	\|\| (n==GPDMA_CONN_UART0_Tx) \|\| (n==GPDMA_CONN_UART0_Rx) \
igorsk	0:1063a091a062	287	\|\| (n==GPDMA_CONN_UART1_Tx) \|\| (n==GPDMA_CONN_UART1_Rx) \
igorsk	0:1063a091a062	288	\|\| (n==GPDMA_CONN_UART2_Tx) \|\| (n==GPDMA_CONN_UART2_Rx) \
igorsk	0:1063a091a062	289	\|\| (n==GPDMA_CONN_UART3_Tx) \|\| (n==GPDMA_CONN_UART3_Rx) \
igorsk	0:1063a091a062	290	\|\| (n==GPDMA_CONN_MAT0_0) \|\| (n==GPDMA_CONN_MAT0_1) \
igorsk	0:1063a091a062	291	\|\| (n==GPDMA_CONN_MAT1_0) \|\| (n==GPDMA_CONN_MAT1_1) \
igorsk	0:1063a091a062	292	\|\| (n==GPDMA_CONN_MAT2_0) \|\| (n==GPDMA_CONN_MAT2_1) \
igorsk	0:1063a091a062	293	\|\| (n==GPDMA_CONN_MAT3_0) \|\| (n==GPDMA_CONN_MAT3_1))
igorsk	0:1063a091a062	294
igorsk	0:1063a091a062	295
igorsk	0:1063a091a062	296	/** GPDMA Transfer type definitions */
igorsk	0:1063a091a062	297	#define GPDMA_TRANSFERTYPE_M2M ((0UL)) /*< Memory to memory - DMA control /
igorsk	0:1063a091a062	298	#define GPDMA_TRANSFERTYPE_M2P ((1UL)) /*< Memory to peripheral - DMA control /
igorsk	0:1063a091a062	299	#define GPDMA_TRANSFERTYPE_P2M ((2UL)) /*< Peripheral to memory - DMA control /
igorsk	0:1063a091a062	300	#define GPDMA_TRANSFERTYPE_P2P ((3UL)) /*< Source peripheral to destination peripheral - DMA control /
igorsk	0:1063a091a062	301
igorsk	0:1063a091a062	302
igorsk	0:1063a091a062	303	#define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)\|\|(n==GPDMA_TRANSFERTYPE_M2P) \
igorsk	0:1063a091a062	304	\|\|(n==GPDMA_TRANSFERTYPE_P2M)\|\|(n==GPDMA_TRANSFERTYPE_P2P))
igorsk	0:1063a091a062	305
igorsk	0:1063a091a062	306
igorsk	0:1063a091a062	307	/** Burst size in Source and Destination definitions */
igorsk	0:1063a091a062	308	#define GPDMA_BSIZE_1 ((0UL)) /*< Burst size = 1 /
igorsk	0:1063a091a062	309	#define GPDMA_BSIZE_4 ((1UL)) /*< Burst size = 4 /
igorsk	0:1063a091a062	310	#define GPDMA_BSIZE_8 ((2UL)) /*< Burst size = 8 /
igorsk	0:1063a091a062	311	#define GPDMA_BSIZE_16 ((3UL)) /*< Burst size = 16 /
igorsk	0:1063a091a062	312	#define GPDMA_BSIZE_32 ((4UL)) /*< Burst size = 32 /
igorsk	0:1063a091a062	313	#define GPDMA_BSIZE_64 ((5UL)) /*< Burst size = 64 /
igorsk	0:1063a091a062	314	#define GPDMA_BSIZE_128 ((6UL)) /*< Burst size = 128 /
igorsk	0:1063a091a062	315	#define GPDMA_BSIZE_256 ((7UL)) /*< Burst size = 256 /
igorsk	0:1063a091a062	316
igorsk	0:1063a091a062	317	#define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) \|\| (n==GPDMA_BSIZE_4) \
igorsk	0:1063a091a062	318	\|\| (n==GPDMA_BSIZE_8) \|\| (n==GPDMA_BSIZE_16) \
igorsk	0:1063a091a062	319	\|\| (n==GPDMA_BSIZE_32) \|\| (n==GPDMA_BSIZE_64) \
igorsk	0:1063a091a062	320	\|\| (n==GPDMA_BSIZE_128) \|\| (n==GPDMA_BSIZE_256))
igorsk	0:1063a091a062	321
igorsk	0:1063a091a062	322
igorsk	0:1063a091a062	323	/** Width in Source transfer width and Destination transfer width definitions */
igorsk	0:1063a091a062	324	#define GPDMA_WIDTH_BYTE ((0UL)) /*< Width = 1 byte /
igorsk	0:1063a091a062	325	#define GPDMA_WIDTH_HALFWORD ((1UL)) /*< Width = 2 bytes /
igorsk	0:1063a091a062	326	#define GPDMA_WIDTH_WORD ((2UL)) /*< Width = 4 bytes /
igorsk	0:1063a091a062	327
igorsk	0:1063a091a062	328	#define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) \|\| (n==GPDMA_WIDTH_HALFWORD) \
igorsk	0:1063a091a062	329	\|\| (n==GPDMA_WIDTH_WORD))
igorsk	0:1063a091a062	330
igorsk	0:1063a091a062	331
igorsk	0:1063a091a062	332	/** DMA Request Select Mode definitions */
igorsk	0:1063a091a062	333	#define GPDMA_REQSEL_UART ((0UL)) /*< UART TX/RX is selected /
igorsk	0:1063a091a062	334	#define GPDMA_REQSEL_TIMER ((1UL)) /*< Timer match is selected /
igorsk	0:1063a091a062	335
igorsk	0:1063a091a062	336	#define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) \|\| (n==GPDMA_REQSEL_TIMER))
igorsk	0:1063a091a062	337
igorsk	0:1063a091a062	338	/** GPDMA Status type definitions */
igorsk	0:1063a091a062	339	/** GPDMA Interrupt Status */
igorsk	0:1063a091a062	340	#define GPDMA_STAT_INT ((0UL))
igorsk	0:1063a091a062	341	/** GPDMA Interrupt Terminal Count Request Status */
igorsk	0:1063a091a062	342	#define GPDMA_STAT_INTTC ((1UL))
igorsk	0:1063a091a062	343	/** GPDMA Interrupt Error Status */
igorsk	0:1063a091a062	344	#define GPDMA_STAT_INTERR ((2UL))
igorsk	0:1063a091a062	345	/** GPDMA Raw Interrupt Terminal Count Status */
igorsk	0:1063a091a062	346	#define GPDMA_STAT_RAWINTTC ((3UL))
igorsk	0:1063a091a062	347	/** GPDMA Raw Error Interrupt Status */
igorsk	0:1063a091a062	348	#define GPDMA_STAT_RAWINTERR ((4UL))
igorsk	0:1063a091a062	349	/** DMA Enabled Channel Status */
igorsk	0:1063a091a062	350	#define GPDMA_STAT_ENABLED_CH ((5UL))
igorsk	0:1063a091a062	351
igorsk	0:1063a091a062	352	#define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) \|\| (n==GPDMA_STAT_INTTC) \
igorsk	0:1063a091a062	353	\|\| (n==GPDMA_STAT_INTERR) \|\| (n==GPDMA_STAT_RAWINTTC) \
igorsk	0:1063a091a062	354	\|\| (n==GPDMA_STAT_RAWINTERR) \|\| (n==GPDMA_STAT_ENABLED_CH))
igorsk	0:1063a091a062	355
igorsk	0:1063a091a062	356	/** GPDMA status type definition that can be clear */
igorsk	0:1063a091a062	357	/** GPDMA Interrupt Terminal Count Request Clear */
igorsk	0:1063a091a062	358	#define GPDMA_STATCLR_INTTC ((0UL))
igorsk	0:1063a091a062	359	/** GPDMA Interrupt Error Clear */
igorsk	0:1063a091a062	360	#define GPDMA_STATCLR_INTERR ((1UL))
igorsk	0:1063a091a062	361
igorsk	0:1063a091a062	362	#define GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) \|\| (n==GPDMA_STATCLR_INTERR))
igorsk	0:1063a091a062	363
igorsk	0:1063a091a062	364	/**
igorsk	0:1063a091a062	365	* @}
igorsk	0:1063a091a062	366	*/
igorsk	0:1063a091a062	367
igorsk	0:1063a091a062	368
igorsk	0:1063a091a062	369	/* Public Functions ----------------------------------------------------------- */
igorsk	0:1063a091a062	370	/** @defgroup GPDMA_Public_Functions
igorsk	0:1063a091a062	371	* @{
igorsk	0:1063a091a062	372	*/
igorsk	0:1063a091a062	373
igorsk	0:1063a091a062	374	void GPDMA_Init(void);
igorsk	0:1063a091a062	375	Status GPDMA_Setup(GPDMA_Channel_CFG_Type GPDMAChannelConfig, fnGPDMACbs_Type pfnGPDMACbs);
igorsk	0:1063a091a062	376	void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
igorsk	0:1063a091a062	377	void GPDMA_IntHandler(void);
igorsk	0:1063a091a062	378
igorsk	0:1063a091a062	379	/**
igorsk	0:1063a091a062	380	* @}
igorsk	0:1063a091a062	381	*/
igorsk	0:1063a091a062	382
igorsk	0:1063a091a062	383
igorsk	0:1063a091a062	384	#ifdef __cplusplus
igorsk	0:1063a091a062	385	}
igorsk	0:1063a091a062	386	#endif
igorsk	0:1063a091a062	387
igorsk	0:1063a091a062	388	#endif /* LPC17XX_GPDMA_H_ */
igorsk	0:1063a091a062	389
igorsk	0:1063a091a062	390	/**
igorsk	0:1063a091a062	391	* @}
igorsk	0:1063a091a062	392	*/
igorsk	0:1063a091a062	393
igorsk	0:1063a091a062	394	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	17 Feb 2010
Imports:	121
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	5

include/lpc17xx_gpdma.h@0:1063a091a062, 2010-02-17 (annotated)

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