Lukasz Uszko
SX1278 RA-01, RA-02 LoRa library
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registers.h
00001 /** 00002 * @brief: SX1278 LoRa and FSK modem registers and bits definitions 00003 * @author: SEMTECH, modified by luk6xff 00004 * @email: luszko@op.pl 00005 * @date: 2019-11-15 00006 */ 00007 00008 #ifndef __REGISTERS_H__ 00009 #define __REGISTERS_H__ 00010 00011 /*! 00012 * ============================================================================ 00013 * SX1278 LoRa Internal registers Address 00014 * ============================================================================ 00015 */ 00016 #define REG_LR_FIFO 0x00 00017 // Common settings 00018 #define REG_LR_OPMODE 0x01 00019 #define REG_LR_FRFMSB 0x06 00020 #define REG_LR_FRFMID 0x07 00021 #define REG_LR_FRFLSB 0x08 00022 // Tx settings 00023 #define REG_LR_PACONFIG 0x09 00024 #define REG_LR_PARAMP 0x0A 00025 #define REG_LR_OCP 0x0B 00026 // Rx settings 00027 #define REG_LR_LNA 0x0C 00028 // LoRa registers 00029 #define REG_LR_FIFOADDRPTR 0x0D 00030 #define REG_LR_FIFOTXBASEADDR 0x0E 00031 #define REG_LR_FIFORXBASEADDR 0x0F 00032 #define REG_LR_FIFORXCURRENTADDR 0x10 00033 #define REG_LR_IRQFLAGSMASK 0x11 00034 #define REG_LR_IRQFLAGS 0x12 00035 #define REG_LR_RXNBBYTES 0x13 00036 #define REG_LR_RXHEADERCNTVALUEMSB 0x14 00037 #define REG_LR_RXHEADERCNTVALUELSB 0x15 00038 #define REG_LR_RXPACKETCNTVALUEMSB 0x16 00039 #define REG_LR_RXPACKETCNTVALUELSB 0x17 00040 #define REG_LR_MODEMSTAT 0x18 00041 #define REG_LR_PKTSNRVALUE 0x19 00042 #define REG_LR_PKTRSSIVALUE 0x1A 00043 #define REG_LR_RSSIVALUE 0x1B 00044 #define REG_LR_HOPCHANNEL 0x1C 00045 #define REG_LR_MODEMCONFIG1 0x1D 00046 #define REG_LR_MODEMCONFIG2 0x1E 00047 #define REG_LR_SYMBTIMEOUTLSB 0x1F 00048 #define REG_LR_PREAMBLEMSB 0x20 00049 #define REG_LR_PREAMBLELSB 0x21 00050 #define REG_LR_PAYLOADLENGTH 0x22 00051 #define REG_LR_PAYLOADMAXLENGTH 0x23 00052 #define REG_LR_HOPPERIOD 0x24 00053 #define REG_LR_FIFORXBYTEADDR 0x25 00054 #define REG_LR_MODEMCONFIG3 0x26 00055 #define REG_LR_FEIMSB 0x28 00056 #define REG_LR_FEIMID 0x29 00057 #define REG_LR_FEILSB 0x2A 00058 #define REG_LR_RSSIWIDEBAND 0x2C 00059 #define REG_LR_IFFREQ1 0x2F 00060 #define REG_LR_IFFREQ2 0x30 00061 #define REG_LR_DETECTOPTIMIZE 0x31 00062 #define REG_LR_INVERTIQ 0x33 00063 #define REG_LR_HIGHBWOPTIMIZE1 0x36 00064 #define REG_LR_DETECTIONTHRESHOLD 0x37 00065 #define REG_LR_SYNCWORD 0x39 00066 #define REG_LR_HIGHBWOPTIMIZE2 0x3A 00067 #define REG_LR_INVERTIQ2 0x3B 00068 00069 // end of documented register in datasheet 00070 // I/O settings 00071 #define REG_LR_DIOMAPPING1 0x40 00072 #define REG_LR_DIOMAPPING2 0x41 00073 // Version 00074 #define REG_LR_VERSION 0x42 00075 // Additional settings 00076 #define REG_LR_PLLHOP 0x44 00077 #define REG_LR_TCXO 0x4B 00078 #define REG_LR_PADAC 0x4D 00079 #define REG_LR_FORMERTEMP 0x5B 00080 #define REG_LR_BITRATEFRAC 0x5D 00081 #define REG_LR_AGCREF 0x61 00082 #define REG_LR_AGCTHRESH1 0x62 00083 #define REG_LR_AGCTHRESH2 0x63 00084 #define REG_LR_AGCTHRESH3 0x64 00085 #define REG_LR_PLL 0x70 00086 00087 /*! 00088 * ============================================================================ 00089 * SX1276 LoRa bits control definition 00090 * ============================================================================ 00091 */ 00092 00093 /*! 00094 * RegFifo 00095 */ 00096 00097 /*! 00098 * RegOpMode 00099 */ 00100 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F 00101 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default 00102 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 00103 00104 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF 00105 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 00106 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default 00107 00108 #define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 00109 #define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default 00110 #define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 00111 00112 #define RFLR_OPMODE_MASK 0xF8 00113 #define RFLR_OPMODE_SLEEP 0x00 00114 #define RFLR_OPMODE_STANDBY 0x01 // Default 00115 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 00116 #define RFLR_OPMODE_TRANSMITTER 0x03 00117 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 00118 #define RFLR_OPMODE_RECEIVER 0x05 00119 // LoRa specific modes 00120 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 00121 #define RFLR_OPMODE_CAD 0x07 00122 00123 /*! 00124 * RegFrf (MHz) 00125 */ 00126 #define RFLR_FRFMSB_434_MHZ 0x6C // Default 00127 #define RFLR_FRFMID_434_MHZ 0x80 // Default 00128 #define RFLR_FRFLSB_434_MHZ 0x00 // Default 00129 00130 /*! 00131 * RegPaConfig 00132 */ 00133 #define RFLR_PACONFIG_PASELECT_MASK 0x7F 00134 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 00135 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default 00136 00137 #define RFLR_PACONFIG_MAX_POWER_MASK 0x8F 00138 00139 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 00140 00141 /*! 00142 * RegPaRamp 00143 */ 00144 #define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF 00145 #define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 00146 #define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default 00147 00148 #define RFLR_PARAMP_MASK 0xF0 00149 #define RFLR_PARAMP_3400_US 0x00 00150 #define RFLR_PARAMP_2000_US 0x01 00151 #define RFLR_PARAMP_1000_US 0x02 00152 #define RFLR_PARAMP_0500_US 0x03 00153 #define RFLR_PARAMP_0250_US 0x04 00154 #define RFLR_PARAMP_0125_US 0x05 00155 #define RFLR_PARAMP_0100_US 0x06 00156 #define RFLR_PARAMP_0062_US 0x07 00157 #define RFLR_PARAMP_0050_US 0x08 00158 #define RFLR_PARAMP_0040_US 0x09 // Default 00159 #define RFLR_PARAMP_0031_US 0x0A 00160 #define RFLR_PARAMP_0025_US 0x0B 00161 #define RFLR_PARAMP_0020_US 0x0C 00162 #define RFLR_PARAMP_0015_US 0x0D 00163 #define RFLR_PARAMP_0012_US 0x0E 00164 #define RFLR_PARAMP_0010_US 0x0F 00165 00166 /*! 00167 * RegOcp 00168 */ 00169 #define RFLR_OCP_MASK 0xDF 00170 #define RFLR_OCP_ON 0x20 // Default 00171 #define RFLR_OCP_OFF 0x00 00172 00173 #define RFLR_OCP_TRIM_MASK 0xE0 00174 #define RFLR_OCP_TRIM_045_MA 0x00 00175 #define RFLR_OCP_TRIM_050_MA 0x01 00176 #define RFLR_OCP_TRIM_055_MA 0x02 00177 #define RFLR_OCP_TRIM_060_MA 0x03 00178 #define RFLR_OCP_TRIM_065_MA 0x04 00179 #define RFLR_OCP_TRIM_070_MA 0x05 00180 #define RFLR_OCP_TRIM_075_MA 0x06 00181 #define RFLR_OCP_TRIM_080_MA 0x07 00182 #define RFLR_OCP_TRIM_085_MA 0x08 00183 #define RFLR_OCP_TRIM_090_MA 0x09 00184 #define RFLR_OCP_TRIM_095_MA 0x0A 00185 #define RFLR_OCP_TRIM_100_MA 0x0B // Default 00186 #define RFLR_OCP_TRIM_105_MA 0x0C 00187 #define RFLR_OCP_TRIM_110_MA 0x0D 00188 #define RFLR_OCP_TRIM_115_MA 0x0E 00189 #define RFLR_OCP_TRIM_120_MA 0x0F 00190 #define RFLR_OCP_TRIM_130_MA 0x10 00191 #define RFLR_OCP_TRIM_140_MA 0x11 00192 #define RFLR_OCP_TRIM_150_MA 0x12 00193 #define RFLR_OCP_TRIM_160_MA 0x13 00194 #define RFLR_OCP_TRIM_170_MA 0x14 00195 #define RFLR_OCP_TRIM_180_MA 0x15 00196 #define RFLR_OCP_TRIM_190_MA 0x16 00197 #define RFLR_OCP_TRIM_200_MA 0x17 00198 #define RFLR_OCP_TRIM_210_MA 0x18 00199 #define RFLR_OCP_TRIM_220_MA 0x19 00200 #define RFLR_OCP_TRIM_230_MA 0x1A 00201 #define RFLR_OCP_TRIM_240_MA 0x1B 00202 00203 /*! 00204 * RegLna 00205 */ 00206 #define RFLR_LNA_GAIN_MASK 0x1F 00207 #define RFLR_LNA_GAIN_G1 0x20 // Default 00208 #define RFLR_LNA_GAIN_G2 0x40 00209 #define RFLR_LNA_GAIN_G3 0x60 00210 #define RFLR_LNA_GAIN_G4 0x80 00211 #define RFLR_LNA_GAIN_G5 0xA0 00212 #define RFLR_LNA_GAIN_G6 0xC0 00213 00214 #define RFLR_LNA_BOOST_LF_MASK 0xE7 00215 #define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default 00216 00217 #define RFLR_LNA_BOOST_HF_MASK 0xFC 00218 #define RFLR_LNA_BOOST_HF_OFF 0x00 // Default 00219 #define RFLR_LNA_BOOST_HF_ON 0x03 00220 00221 /*! 00222 * RegFifoAddrPtr 00223 */ 00224 #define RFLR_FIFOADDRPTR 0x00 // Default 00225 00226 /*! 00227 * RegFifoTxBaseAddr 00228 */ 00229 #define RFLR_FIFOTXBASEADDR 0x80 // Default 00230 00231 /*! 00232 * RegFifoTxBaseAddr 00233 */ 00234 #define RFLR_FIFORXBASEADDR 0x00 // Default 00235 00236 /*! 00237 * RegFifoRxCurrentAddr (Read Only) 00238 */ 00239 00240 /*! 00241 * RegIrqFlagsMask 00242 */ 00243 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 00244 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 00245 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 00246 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 00247 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 00248 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 00249 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 00250 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 00251 00252 /*! 00253 * RegIrqFlags 00254 */ 00255 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 00256 #define RFLR_IRQFLAGS_RXDONE 0x40 00257 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 00258 #define RFLR_IRQFLAGS_VALIDHEADER 0x10 00259 #define RFLR_IRQFLAGS_TXDONE 0x08 00260 #define RFLR_IRQFLAGS_CADDONE 0x04 00261 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 00262 #define RFLR_IRQFLAGS_CADDETECTED 0x01 00263 00264 /*! 00265 * RegFifoRxNbBytes (Read Only) 00266 */ 00267 00268 /*! 00269 * RegRxHeaderCntValueMsb (Read Only) 00270 */ 00271 00272 /*! 00273 * RegRxHeaderCntValueLsb (Read Only) 00274 */ 00275 00276 /*! 00277 * RegRxPacketCntValueMsb (Read Only) 00278 */ 00279 00280 /*! 00281 * RegRxPacketCntValueLsb (Read Only) 00282 */ 00283 00284 /*! 00285 * RegModemStat (Read Only) 00286 */ 00287 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F 00288 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 00289 00290 /*! 00291 * RegPktSnrValue (Read Only) 00292 */ 00293 00294 /*! 00295 * RegPktRssiValue (Read Only) 00296 */ 00297 00298 /*! 00299 * RegRssiValue (Read Only) 00300 */ 00301 00302 /*! 00303 * RegHopChannel (Read Only) 00304 */ 00305 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F 00306 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 00307 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default 00308 00309 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF 00310 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 00311 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default 00312 00313 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F 00314 00315 /*! 00316 * RegModemConfig1 00317 */ 00318 #define RFLR_MODEMCONFIG1_BW_MASK 0x0F 00319 #define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 00320 #define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 00321 #define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 00322 #define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 00323 #define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 00324 #define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 00325 #define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 00326 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default 00327 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 00328 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 00329 00330 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 00331 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 00332 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default 00333 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 00334 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 00335 00336 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE 00337 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 00338 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default 00339 00340 /*! 00341 * RegModemConfig2 00342 */ 00343 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F 00344 #define RFLR_MODEMCONFIG2_SF_6 0x60 00345 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default 00346 #define RFLR_MODEMCONFIG2_SF_8 0x80 00347 #define RFLR_MODEMCONFIG2_SF_9 0x90 00348 #define RFLR_MODEMCONFIG2_SF_10 0xA0 00349 #define RFLR_MODEMCONFIG2_SF_11 0xB0 00350 #define RFLR_MODEMCONFIG2_SF_12 0xC0 00351 00352 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 00353 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 00354 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 00355 00356 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB 00357 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 00358 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default 00359 00360 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC 00361 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default 00362 00363 /*! 00364 * RegSymbTimeoutLsb 00365 */ 00366 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default 00367 00368 /*! 00369 * RegPreambleLengthMsb 00370 */ 00371 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default 00372 00373 /*! 00374 * RegPreambleLengthLsb 00375 */ 00376 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default 00377 00378 /*! 00379 * RegPayloadLength 00380 */ 00381 #define RFLR_PAYLOADLENGTH 0x0E // Default 00382 00383 /*! 00384 * RegPayloadMaxLength 00385 */ 00386 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default 00387 00388 /*! 00389 * RegHopPeriod 00390 */ 00391 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default 00392 00393 /*! 00394 * RegFifoRxByteAddr (Read Only) 00395 */ 00396 00397 /*! 00398 * RegModemConfig3 00399 */ 00400 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 00401 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 00402 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default 00403 00404 #define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB 00405 #define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default 00406 #define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 00407 00408 /*! 00409 * RegFeiMsb (Read Only) 00410 */ 00411 00412 /*! 00413 * RegFeiMid (Read Only) 00414 */ 00415 00416 /*! 00417 * RegFeiLsb (Read Only) 00418 */ 00419 00420 /*! 00421 * RegRssiWideband (Read Only) 00422 */ 00423 00424 /*! 00425 * RegDetectOptimize 00426 */ 00427 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 00428 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default 00429 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 00430 00431 /*! 00432 * RegInvertIQ 00433 */ 00434 #define RFLR_INVERTIQ_RX_MASK 0xBF 00435 #define RFLR_INVERTIQ_RX_OFF 0x00 00436 #define RFLR_INVERTIQ_RX_ON 0x40 00437 #define RFLR_INVERTIQ_TX_MASK 0xFE 00438 #define RFLR_INVERTIQ_TX_OFF 0x01 00439 #define RFLR_INVERTIQ_TX_ON 0x00 00440 00441 /*! 00442 * RegDetectionThreshold 00443 */ 00444 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default 00445 #define RFLR_DETECTIONTHRESH_SF6 0x0C 00446 00447 /*! 00448 * RegInvertIQ2 00449 */ 00450 #define RFLR_INVERTIQ2_ON 0x19 00451 #define RFLR_INVERTIQ2_OFF 0x1D 00452 00453 /*! 00454 * RegDioMapping1 00455 */ 00456 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F 00457 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default 00458 #define RFLR_DIOMAPPING1_DIO0_01 0x40 00459 #define RFLR_DIOMAPPING1_DIO0_10 0x80 00460 #define RFLR_DIOMAPPING1_DIO0_11 0xC0 00461 00462 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF 00463 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default 00464 #define RFLR_DIOMAPPING1_DIO1_01 0x10 00465 #define RFLR_DIOMAPPING1_DIO1_10 0x20 00466 #define RFLR_DIOMAPPING1_DIO1_11 0x30 00467 00468 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 00469 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default 00470 #define RFLR_DIOMAPPING1_DIO2_01 0x04 00471 #define RFLR_DIOMAPPING1_DIO2_10 0x08 00472 #define RFLR_DIOMAPPING1_DIO2_11 0x0C 00473 00474 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC 00475 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default 00476 #define RFLR_DIOMAPPING1_DIO3_01 0x01 00477 #define RFLR_DIOMAPPING1_DIO3_10 0x02 00478 #define RFLR_DIOMAPPING1_DIO3_11 0x03 00479 00480 /*! 00481 * RegDioMapping2 00482 */ 00483 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F 00484 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default 00485 #define RFLR_DIOMAPPING2_DIO4_01 0x40 00486 #define RFLR_DIOMAPPING2_DIO4_10 0x80 00487 #define RFLR_DIOMAPPING2_DIO4_11 0xC0 00488 00489 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF 00490 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default 00491 #define RFLR_DIOMAPPING2_DIO5_01 0x10 00492 #define RFLR_DIOMAPPING2_DIO5_10 0x20 00493 #define RFLR_DIOMAPPING2_DIO5_11 0x30 00494 00495 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE 00496 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 00497 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default 00498 00499 /*! 00500 * RegVersion (Read Only) 00501 */ 00502 00503 /*! 00504 * RegPllHop 00505 */ 00506 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F 00507 #define RFLR_PLLHOP_FASTHOP_ON 0x80 00508 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default 00509 00510 /*! 00511 * RegTcxo 00512 */ 00513 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF 00514 #define RFLR_TCXO_TCXOINPUT_ON 0x10 00515 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default 00516 00517 /*! 00518 * RegPaDac 00519 */ 00520 #define RFLR_PADAC_20DBM_MASK 0xF8 00521 #define RFLR_PADAC_20DBM_ON 0x07 00522 #define RFLR_PADAC_20DBM_OFF 0x04 // Default 00523 00524 /*! 00525 * RegFormerTemp 00526 */ 00527 00528 /*! 00529 * RegBitrateFrac 00530 */ 00531 #define RF_BITRATEFRAC_MASK 0xF0 00532 00533 /*! 00534 * RegAgcRef 00535 */ 00536 00537 /*! 00538 * RegAgcThresh1 00539 */ 00540 00541 /*! 00542 * RegAgcThresh2 00543 */ 00544 00545 /*! 00546 * RegAgcThresh3 00547 */ 00548 00549 /*! 00550 * RegPll 00551 */ 00552 #define RF_PLL_BANDWIDTH_MASK 0x3F 00553 #define RF_PLL_BANDWIDTH_75 0x00 00554 #define RF_PLL_BANDWIDTH_150 0x40 00555 #define RF_PLL_BANDWIDTH_225 0x80 00556 #define RF_PLL_BANDWIDTH_300 0xC0 // Default 00557 00558 00559 00560 /*! 00561 * ============================================================================ 00562 * SX1278 FSK Internal registers Address 00563 * ============================================================================ 00564 */ 00565 #define REG_FIFO 0x00 00566 // Common settings 00567 #define REG_OPMODE 0x01 00568 #define REG_BITRATEMSB 0x02 00569 #define REG_BITRATELSB 0x03 00570 #define REG_FDEVMSB 0x04 00571 #define REG_FDEVLSB 0x05 00572 #define REG_FRFMSB 0x06 00573 #define REG_FRFMID 0x07 00574 #define REG_FRFLSB 0x08 00575 // Tx settings 00576 #define REG_PACONFIG 0x09 00577 #define REG_PARAMP 0x0A 00578 #define REG_OCP 0x0B 00579 // Rx settings 00580 #define REG_LNA 0x0C 00581 #define REG_RXCONFIG 0x0D 00582 #define REG_RSSICONFIG 0x0E 00583 #define REG_RSSICOLLISION 0x0F 00584 #define REG_RSSITHRESH 0x10 00585 #define REG_RSSIVALUE 0x11 00586 #define REG_RXBW 0x12 00587 #define REG_AFCBW 0x13 00588 #define REG_OOKPEAK 0x14 00589 #define REG_OOKFIX 0x15 00590 #define REG_OOKAVG 0x16 00591 #define REG_RES17 0x17 00592 #define REG_RES18 0x18 00593 #define REG_RES19 0x19 00594 #define REG_AFCFEI 0x1A 00595 #define REG_AFCMSB 0x1B 00596 #define REG_AFCLSB 0x1C 00597 #define REG_FEIMSB 0x1D 00598 #define REG_FEILSB 0x1E 00599 #define REG_PREAMBLEDETECT 0x1F 00600 #define REG_RXTIMEOUT1 0x20 00601 #define REG_RXTIMEOUT2 0x21 00602 #define REG_RXTIMEOUT3 0x22 00603 #define REG_RXDELAY 0x23 00604 // Oscillator settings 00605 #define REG_OSC 0x24 00606 // Packet handler settings 00607 #define REG_PREAMBLEMSB 0x25 00608 #define REG_PREAMBLELSB 0x26 00609 #define REG_SYNCCONFIG 0x27 00610 #define REG_SYNCVALUE1 0x28 00611 #define REG_SYNCVALUE2 0x29 00612 #define REG_SYNCVALUE3 0x2A 00613 #define REG_SYNCVALUE4 0x2B 00614 #define REG_SYNCVALUE5 0x2C 00615 #define REG_SYNCVALUE6 0x2D 00616 #define REG_SYNCVALUE7 0x2E 00617 #define REG_SYNCVALUE8 0x2F 00618 #define REG_PACKETCONFIG1 0x30 00619 #define REG_PACKETCONFIG2 0x31 00620 #define REG_PAYLOADLENGTH 0x32 00621 #define REG_NODEADRS 0x33 00622 #define REG_BROADCASTADRS 0x34 00623 #define REG_FIFOTHRESH 0x35 00624 // SM settings 00625 #define REG_SEQCONFIG1 0x36 00626 #define REG_SEQCONFIG2 0x37 00627 #define REG_TIMERRESOL 0x38 00628 #define REG_TIMER1COEF 0x39 00629 #define REG_TIMER2COEF 0x3A 00630 // Service settings 00631 #define REG_IMAGECAL 0x3B 00632 #define REG_TEMP 0x3C 00633 #define REG_LOWBAT 0x3D 00634 // Status 00635 #define REG_IRQFLAGS1 0x3E 00636 #define REG_IRQFLAGS2 0x3F 00637 // I/O settings 00638 #define REG_DIOMAPPING1 0x40 00639 #define REG_DIOMAPPING2 0x41 00640 // Version 00641 #define REG_VERSION 0x42 00642 // Additional settings 00643 #define REG_PLLHOP 0x44 00644 #define REG_TCXO 0x4B 00645 #define REG_PADAC 0x4D 00646 #define REG_FORMERTEMP 0x5B 00647 #define REG_BITRATEFRAC 0x5D 00648 #define REG_AGCREF 0x61 00649 #define REG_AGCTHRESH1 0x62 00650 #define REG_AGCTHRESH2 0x63 00651 #define REG_AGCTHRESH3 0x64 00652 #define REG_PLL 0x70 00653 00654 /*! 00655 * ============================================================================ 00656 * SX1276 FSK bits control definition 00657 * ============================================================================ 00658 */ 00659 00660 /*! 00661 * RegFifo 00662 */ 00663 00664 /*! 00665 * RegOpMode 00666 */ 00667 #define RF_OPMODE_LONGRANGEMODE_MASK 0x7F 00668 #define RF_OPMODE_LONGRANGEMODE_OFF 0x00 00669 #define RF_OPMODE_LONGRANGEMODE_ON 0x80 00670 00671 #define RF_OPMODE_MODULATIONTYPE_MASK 0x9F 00672 #define RF_OPMODE_MODULATIONTYPE_FSK 0x00 // Default 00673 #define RF_OPMODE_MODULATIONTYPE_OOK 0x20 00674 00675 #define RF_OPMODE_MODULATIONSHAPING_MASK 0xE7 00676 #define RF_OPMODE_MODULATIONSHAPING_00 0x00 // Default 00677 #define RF_OPMODE_MODULATIONSHAPING_01 0x08 00678 #define RF_OPMODE_MODULATIONSHAPING_10 0x10 00679 #define RF_OPMODE_MODULATIONSHAPING_11 0x18 00680 00681 #define RF_OPMODE_MASK 0xF8 00682 #define RF_OPMODE_SLEEP 0x00 00683 #define RF_OPMODE_STANDBY 0x01 // Default 00684 #define RF_OPMODE_SYNTHESIZER_TX 0x02 00685 #define RF_OPMODE_TRANSMITTER 0x03 00686 #define RF_OPMODE_SYNTHESIZER_RX 0x04 00687 #define RF_OPMODE_RECEIVER 0x05 00688 00689 /*! 00690 * RegBitRate (bits/sec) 00691 */ 00692 #define RF_BITRATEMSB_1200_BPS 0x68 00693 #define RF_BITRATELSB_1200_BPS 0x2B 00694 #define RF_BITRATEMSB_2400_BPS 0x34 00695 #define RF_BITRATELSB_2400_BPS 0x15 00696 #define RF_BITRATEMSB_4800_BPS 0x1A // Default 00697 #define RF_BITRATELSB_4800_BPS 0x0B // Default 00698 #define RF_BITRATEMSB_9600_BPS 0x0D 00699 #define RF_BITRATELSB_9600_BPS 0x05 00700 #define RF_BITRATEMSB_15000_BPS 0x08 00701 #define RF_BITRATELSB_15000_BPS 0x55 00702 #define RF_BITRATEMSB_19200_BPS 0x06 00703 #define RF_BITRATELSB_19200_BPS 0x83 00704 #define RF_BITRATEMSB_38400_BPS 0x03 00705 #define RF_BITRATELSB_38400_BPS 0x41 00706 #define RF_BITRATEMSB_76800_BPS 0x01 00707 #define RF_BITRATELSB_76800_BPS 0xA1 00708 #define RF_BITRATEMSB_153600_BPS 0x00 00709 #define RF_BITRATELSB_153600_BPS 0xD0 00710 #define RF_BITRATEMSB_57600_BPS 0x02 00711 #define RF_BITRATELSB_57600_BPS 0x2C 00712 #define RF_BITRATEMSB_115200_BPS 0x01 00713 #define RF_BITRATELSB_115200_BPS 0x16 00714 #define RF_BITRATEMSB_12500_BPS 0x0A 00715 #define RF_BITRATELSB_12500_BPS 0x00 00716 #define RF_BITRATEMSB_25000_BPS 0x05 00717 #define RF_BITRATELSB_25000_BPS 0x00 00718 #define RF_BITRATEMSB_50000_BPS 0x02 00719 #define RF_BITRATELSB_50000_BPS 0x80 00720 #define RF_BITRATEMSB_100000_BPS 0x01 00721 #define RF_BITRATELSB_100000_BPS 0x40 00722 #define RF_BITRATEMSB_150000_BPS 0x00 00723 #define RF_BITRATELSB_150000_BPS 0xD5 00724 #define RF_BITRATEMSB_200000_BPS 0x00 00725 #define RF_BITRATELSB_200000_BPS 0xA0 00726 #define RF_BITRATEMSB_250000_BPS 0x00 00727 #define RF_BITRATELSB_250000_BPS 0x80 00728 #define RF_BITRATEMSB_32768_BPS 0x03 00729 #define RF_BITRATELSB_32768_BPS 0xD1 00730 00731 /*! 00732 * RegFdev (Hz) 00733 */ 00734 #define RF_FDEVMSB_2000_HZ 0x00 00735 #define RF_FDEVLSB_2000_HZ 0x21 00736 #define RF_FDEVMSB_5000_HZ 0x00 // Default 00737 #define RF_FDEVLSB_5000_HZ 0x52 // Default 00738 #define RF_FDEVMSB_10000_HZ 0x00 00739 #define RF_FDEVLSB_10000_HZ 0xA4 00740 #define RF_FDEVMSB_15000_HZ 0x00 00741 #define RF_FDEVLSB_15000_HZ 0xF6 00742 #define RF_FDEVMSB_20000_HZ 0x01 00743 #define RF_FDEVLSB_20000_HZ 0x48 00744 #define RF_FDEVMSB_25000_HZ 0x01 00745 #define RF_FDEVLSB_25000_HZ 0x9A 00746 #define RF_FDEVMSB_30000_HZ 0x01 00747 #define RF_FDEVLSB_30000_HZ 0xEC 00748 #define RF_FDEVMSB_35000_HZ 0x02 00749 #define RF_FDEVLSB_35000_HZ 0x3D 00750 #define RF_FDEVMSB_40000_HZ 0x02 00751 #define RF_FDEVLSB_40000_HZ 0x8F 00752 #define RF_FDEVMSB_45000_HZ 0x02 00753 #define RF_FDEVLSB_45000_HZ 0xE1 00754 #define RF_FDEVMSB_50000_HZ 0x03 00755 #define RF_FDEVLSB_50000_HZ 0x33 00756 #define RF_FDEVMSB_55000_HZ 0x03 00757 #define RF_FDEVLSB_55000_HZ 0x85 00758 #define RF_FDEVMSB_60000_HZ 0x03 00759 #define RF_FDEVLSB_60000_HZ 0xD7 00760 #define RF_FDEVMSB_65000_HZ 0x04 00761 #define RF_FDEVLSB_65000_HZ 0x29 00762 #define RF_FDEVMSB_70000_HZ 0x04 00763 #define RF_FDEVLSB_70000_HZ 0x7B 00764 #define RF_FDEVMSB_75000_HZ 0x04 00765 #define RF_FDEVLSB_75000_HZ 0xCD 00766 #define RF_FDEVMSB_80000_HZ 0x05 00767 #define RF_FDEVLSB_80000_HZ 0x1F 00768 #define RF_FDEVMSB_85000_HZ 0x05 00769 #define RF_FDEVLSB_85000_HZ 0x71 00770 #define RF_FDEVMSB_90000_HZ 0x05 00771 #define RF_FDEVLSB_90000_HZ 0xC3 00772 #define RF_FDEVMSB_95000_HZ 0x06 00773 #define RF_FDEVLSB_95000_HZ 0x14 00774 #define RF_FDEVMSB_100000_HZ 0x06 00775 #define RF_FDEVLSB_100000_HZ 0x66 00776 #define RF_FDEVMSB_110000_HZ 0x07 00777 #define RF_FDEVLSB_110000_HZ 0x0A 00778 #define RF_FDEVMSB_120000_HZ 0x07 00779 #define RF_FDEVLSB_120000_HZ 0xAE 00780 #define RF_FDEVMSB_130000_HZ 0x08 00781 #define RF_FDEVLSB_130000_HZ 0x52 00782 #define RF_FDEVMSB_140000_HZ 0x08 00783 #define RF_FDEVLSB_140000_HZ 0xF6 00784 #define RF_FDEVMSB_150000_HZ 0x09 00785 #define RF_FDEVLSB_150000_HZ 0x9A 00786 #define RF_FDEVMSB_160000_HZ 0x0A 00787 #define RF_FDEVLSB_160000_HZ 0x3D 00788 #define RF_FDEVMSB_170000_HZ 0x0A 00789 #define RF_FDEVLSB_170000_HZ 0xE1 00790 #define RF_FDEVMSB_180000_HZ 0x0B 00791 #define RF_FDEVLSB_180000_HZ 0x85 00792 #define RF_FDEVMSB_190000_HZ 0x0C 00793 #define RF_FDEVLSB_190000_HZ 0x29 00794 #define RF_FDEVMSB_200000_HZ 0x0C 00795 #define RF_FDEVLSB_200000_HZ 0xCD 00796 00797 /*! 00798 * RegFrf (MHz) 00799 */ 00800 #define RF_FRFMSB_863_MHZ 0xD7 00801 #define RF_FRFMID_863_MHZ 0xC0 00802 #define RF_FRFLSB_863_MHZ 0x00 00803 #define RF_FRFMSB_864_MHZ 0xD8 00804 #define RF_FRFMID_864_MHZ 0x00 00805 #define RF_FRFLSB_864_MHZ 0x00 00806 #define RF_FRFMSB_865_MHZ 0xD8 00807 #define RF_FRFMID_865_MHZ 0x40 00808 #define RF_FRFLSB_865_MHZ 0x00 00809 #define RF_FRFMSB_866_MHZ 0xD8 00810 #define RF_FRFMID_866_MHZ 0x80 00811 #define RF_FRFLSB_866_MHZ 0x00 00812 #define RF_FRFMSB_867_MHZ 0xD8 00813 #define RF_FRFMID_867_MHZ 0xC0 00814 #define RF_FRFLSB_867_MHZ 0x00 00815 #define RF_FRFMSB_868_MHZ 0xD9 00816 #define RF_FRFMID_868_MHZ 0x00 00817 #define RF_FRFLSB_868_MHZ 0x00 00818 #define RF_FRFMSB_869_MHZ 0xD9 00819 #define RF_FRFMID_869_MHZ 0x40 00820 #define RF_FRFLSB_869_MHZ 0x00 00821 #define RF_FRFMSB_870_MHZ 0xD9 00822 #define RF_FRFMID_870_MHZ 0x80 00823 #define RF_FRFLSB_870_MHZ 0x00 00824 00825 #define RF_FRFMSB_902_MHZ 0xE1 00826 #define RF_FRFMID_902_MHZ 0x80 00827 #define RF_FRFLSB_902_MHZ 0x00 00828 #define RF_FRFMSB_903_MHZ 0xE1 00829 #define RF_FRFMID_903_MHZ 0xC0 00830 #define RF_FRFLSB_903_MHZ 0x00 00831 #define RF_FRFMSB_904_MHZ 0xE2 00832 #define RF_FRFMID_904_MHZ 0x00 00833 #define RF_FRFLSB_904_MHZ 0x00 00834 #define RF_FRFMSB_905_MHZ 0xE2 00835 #define RF_FRFMID_905_MHZ 0x40 00836 #define RF_FRFLSB_905_MHZ 0x00 00837 #define RF_FRFMSB_906_MHZ 0xE2 00838 #define RF_FRFMID_906_MHZ 0x80 00839 #define RF_FRFLSB_906_MHZ 0x00 00840 #define RF_FRFMSB_907_MHZ 0xE2 00841 #define RF_FRFMID_907_MHZ 0xC0 00842 #define RF_FRFLSB_907_MHZ 0x00 00843 #define RF_FRFMSB_908_MHZ 0xE3 00844 #define RF_FRFMID_908_MHZ 0x00 00845 #define RF_FRFLSB_908_MHZ 0x00 00846 #define RF_FRFMSB_909_MHZ 0xE3 00847 #define RF_FRFMID_909_MHZ 0x40 00848 #define RF_FRFLSB_909_MHZ 0x00 00849 #define RF_FRFMSB_910_MHZ 0xE3 00850 #define RF_FRFMID_910_MHZ 0x80 00851 #define RF_FRFLSB_910_MHZ 0x00 00852 #define RF_FRFMSB_911_MHZ 0xE3 00853 #define RF_FRFMID_911_MHZ 0xC0 00854 #define RF_FRFLSB_911_MHZ 0x00 00855 #define RF_FRFMSB_912_MHZ 0xE4 00856 #define RF_FRFMID_912_MHZ 0x00 00857 #define RF_FRFLSB_912_MHZ 0x00 00858 #define RF_FRFMSB_913_MHZ 0xE4 00859 #define RF_FRFMID_913_MHZ 0x40 00860 #define RF_FRFLSB_913_MHZ 0x00 00861 #define RF_FRFMSB_914_MHZ 0xE4 00862 #define RF_FRFMID_914_MHZ 0x80 00863 #define RF_FRFLSB_914_MHZ 0x00 00864 #define RF_FRFMSB_915_MHZ 0xE4 // Default 00865 #define RF_FRFMID_915_MHZ 0xC0 // Default 00866 #define RF_FRFLSB_915_MHZ 0x00 // Default 00867 #define RF_FRFMSB_916_MHZ 0xE5 00868 #define RF_FRFMID_916_MHZ 0x00 00869 #define RF_FRFLSB_916_MHZ 0x00 00870 #define RF_FRFMSB_917_MHZ 0xE5 00871 #define RF_FRFMID_917_MHZ 0x40 00872 #define RF_FRFLSB_917_MHZ 0x00 00873 #define RF_FRFMSB_918_MHZ 0xE5 00874 #define RF_FRFMID_918_MHZ 0x80 00875 #define RF_FRFLSB_918_MHZ 0x00 00876 #define RF_FRFMSB_919_MHZ 0xE5 00877 #define RF_FRFMID_919_MHZ 0xC0 00878 #define RF_FRFLSB_919_MHZ 0x00 00879 #define RF_FRFMSB_920_MHZ 0xE6 00880 #define RF_FRFMID_920_MHZ 0x00 00881 #define RF_FRFLSB_920_MHZ 0x00 00882 #define RF_FRFMSB_921_MHZ 0xE6 00883 #define RF_FRFMID_921_MHZ 0x40 00884 #define RF_FRFLSB_921_MHZ 0x00 00885 #define RF_FRFMSB_922_MHZ 0xE6 00886 #define RF_FRFMID_922_MHZ 0x80 00887 #define RF_FRFLSB_922_MHZ 0x00 00888 #define RF_FRFMSB_923_MHZ 0xE6 00889 #define RF_FRFMID_923_MHZ 0xC0 00890 #define RF_FRFLSB_923_MHZ 0x00 00891 #define RF_FRFMSB_924_MHZ 0xE7 00892 #define RF_FRFMID_924_MHZ 0x00 00893 #define RF_FRFLSB_924_MHZ 0x00 00894 #define RF_FRFMSB_925_MHZ 0xE7 00895 #define RF_FRFMID_925_MHZ 0x40 00896 #define RF_FRFLSB_925_MHZ 0x00 00897 #define RF_FRFMSB_926_MHZ 0xE7 00898 #define RF_FRFMID_926_MHZ 0x80 00899 #define RF_FRFLSB_926_MHZ 0x00 00900 #define RF_FRFMSB_927_MHZ 0xE7 00901 #define RF_FRFMID_927_MHZ 0xC0 00902 #define RF_FRFLSB_927_MHZ 0x00 00903 #define RF_FRFMSB_928_MHZ 0xE8 00904 #define RF_FRFMID_928_MHZ 0x00 00905 #define RF_FRFLSB_928_MHZ 0x00 00906 00907 /*! 00908 * RegPaConfig 00909 */ 00910 #define RF_PACONFIG_PASELECT_MASK 0x7F 00911 #define RF_PACONFIG_PASELECT_PABOOST 0x80 00912 #define RF_PACONFIG_PASELECT_RFO 0x00 // Default 00913 00914 #define RF_PACONFIG_MAX_POWER_MASK 0x8F 00915 00916 #define RF_PACONFIG_OUTPUTPOWER_MASK 0xF0 00917 00918 /*! 00919 * RegPaRamp 00920 */ 00921 #define RF_PARAMP_MODULATIONSHAPING_MASK 0x9F 00922 #define RF_PARAMP_MODULATIONSHAPING_00 0x00 // Default 00923 #define RF_PARAMP_MODULATIONSHAPING_01 0x20 00924 #define RF_PARAMP_MODULATIONSHAPING_10 0x40 00925 #define RF_PARAMP_MODULATIONSHAPING_11 0x60 00926 00927 #define RF_PARAMP_LOWPNTXPLL_MASK 0xEF 00928 #define RF_PARAMP_LOWPNTXPLL_OFF 0x10 00929 #define RF_PARAMP_LOWPNTXPLL_ON 0x00 // Default 00930 00931 #define RF_PARAMP_MASK 0xF0 00932 #define RF_PARAMP_3400_US 0x00 00933 #define RF_PARAMP_2000_US 0x01 00934 #define RF_PARAMP_1000_US 0x02 00935 #define RF_PARAMP_0500_US 0x03 00936 #define RF_PARAMP_0250_US 0x04 00937 #define RF_PARAMP_0125_US 0x05 00938 #define RF_PARAMP_0100_US 0x06 00939 #define RF_PARAMP_0062_US 0x07 00940 #define RF_PARAMP_0050_US 0x08 00941 #define RF_PARAMP_0040_US 0x09 // Default 00942 #define RF_PARAMP_0031_US 0x0A 00943 #define RF_PARAMP_0025_US 0x0B 00944 #define RF_PARAMP_0020_US 0x0C 00945 #define RF_PARAMP_0015_US 0x0D 00946 #define RF_PARAMP_0012_US 0x0E 00947 #define RF_PARAMP_0010_US 0x0F 00948 00949 /*! 00950 * RegOcp 00951 */ 00952 #define RF_OCP_MASK 0xDF 00953 #define RF_OCP_ON 0x20 // Default 00954 #define RF_OCP_OFF 0x00 00955 00956 #define RF_OCP_TRIM_MASK 0xE0 00957 #define RF_OCP_TRIM_045_MA 0x00 00958 #define RF_OCP_TRIM_050_MA 0x01 00959 #define RF_OCP_TRIM_055_MA 0x02 00960 #define RF_OCP_TRIM_060_MA 0x03 00961 #define RF_OCP_TRIM_065_MA 0x04 00962 #define RF_OCP_TRIM_070_MA 0x05 00963 #define RF_OCP_TRIM_075_MA 0x06 00964 #define RF_OCP_TRIM_080_MA 0x07 00965 #define RF_OCP_TRIM_085_MA 0x08 00966 #define RF_OCP_TRIM_090_MA 0x09 00967 #define RF_OCP_TRIM_095_MA 0x0A 00968 #define RF_OCP_TRIM_100_MA 0x0B // Default 00969 #define RF_OCP_TRIM_105_MA 0x0C 00970 #define RF_OCP_TRIM_110_MA 0x0D 00971 #define RF_OCP_TRIM_115_MA 0x0E 00972 #define RF_OCP_TRIM_120_MA 0x0F 00973 #define RF_OCP_TRIM_130_MA 0x10 00974 #define RF_OCP_TRIM_140_MA 0x11 00975 #define RF_OCP_TRIM_150_MA 0x12 00976 #define RF_OCP_TRIM_160_MA 0x13 00977 #define RF_OCP_TRIM_170_MA 0x14 00978 #define RF_OCP_TRIM_180_MA 0x15 00979 #define RF_OCP_TRIM_190_MA 0x16 00980 #define RF_OCP_TRIM_200_MA 0x17 00981 #define RF_OCP_TRIM_210_MA 0x18 00982 #define RF_OCP_TRIM_220_MA 0x19 00983 #define RF_OCP_TRIM_230_MA 0x1A 00984 #define RF_OCP_TRIM_240_MA 0x1B 00985 00986 /*! 00987 * RegLna 00988 */ 00989 #define RF_LNA_GAIN_MASK 0x1F 00990 #define RF_LNA_GAIN_G1 0x20 // Default 00991 #define RF_LNA_GAIN_G2 0x40 00992 #define RF_LNA_GAIN_G3 0x60 00993 #define RF_LNA_GAIN_G4 0x80 00994 #define RF_LNA_GAIN_G5 0xA0 00995 #define RF_LNA_GAIN_G6 0xC0 00996 00997 #define RF_LNA_BOOST_MASK 0xFC 00998 #define RF_LNA_BOOST_OFF 0x00 // Default 00999 #define RF_LNA_BOOST_ON 0x03 01000 01001 /*! 01002 * RegRxConfig 01003 */ 01004 #define RF_RXCONFIG_RESTARTRXONCOLLISION_MASK 0x7F 01005 #define RF_RXCONFIG_RESTARTRXONCOLLISION_ON 0x80 01006 #define RF_RXCONFIG_RESTARTRXONCOLLISION_OFF 0x00 // Default 01007 01008 #define RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK 0x40 // Write only 01009 01010 #define RF_RXCONFIG_RESTARTRXWITHPLLLOCK 0x20 // Write only 01011 01012 #define RF_RXCONFIG_AFCAUTO_MASK 0xEF 01013 #define RF_RXCONFIG_AFCAUTO_ON 0x10 01014 #define RF_RXCONFIG_AFCAUTO_OFF 0x00 // Default 01015 01016 #define RF_RXCONFIG_AGCAUTO_MASK 0xF7 01017 #define RF_RXCONFIG_AGCAUTO_ON 0x08 // Default 01018 #define RF_RXCONFIG_AGCAUTO_OFF 0x00 01019 01020 #define RF_RXCONFIG_RXTRIGER_MASK 0xF8 01021 #define RF_RXCONFIG_RXTRIGER_OFF 0x00 01022 #define RF_RXCONFIG_RXTRIGER_RSSI 0x01 01023 #define RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT 0x06 // Default 01024 #define RF_RXCONFIG_RXTRIGER_RSSI_PREAMBLEDETECT 0x07 01025 01026 /*! 01027 * RegRssiConfig 01028 */ 01029 #define RF_RSSICONFIG_OFFSET_MASK 0x07 01030 #define RF_RSSICONFIG_OFFSET_P_00_DB 0x00 // Default 01031 #define RF_RSSICONFIG_OFFSET_P_01_DB 0x08 01032 #define RF_RSSICONFIG_OFFSET_P_02_DB 0x10 01033 #define RF_RSSICONFIG_OFFSET_P_03_DB 0x18 01034 #define RF_RSSICONFIG_OFFSET_P_04_DB 0x20 01035 #define RF_RSSICONFIG_OFFSET_P_05_DB 0x28 01036 #define RF_RSSICONFIG_OFFSET_P_06_DB 0x30 01037 #define RF_RSSICONFIG_OFFSET_P_07_DB 0x38 01038 #define RF_RSSICONFIG_OFFSET_P_08_DB 0x40 01039 #define RF_RSSICONFIG_OFFSET_P_09_DB 0x48 01040 #define RF_RSSICONFIG_OFFSET_P_10_DB 0x50 01041 #define RF_RSSICONFIG_OFFSET_P_11_DB 0x58 01042 #define RF_RSSICONFIG_OFFSET_P_12_DB 0x60 01043 #define RF_RSSICONFIG_OFFSET_P_13_DB 0x68 01044 #define RF_RSSICONFIG_OFFSET_P_14_DB 0x70 01045 #define RF_RSSICONFIG_OFFSET_P_15_DB 0x78 01046 #define RF_RSSICONFIG_OFFSET_M_16_DB 0x80 01047 #define RF_RSSICONFIG_OFFSET_M_15_DB 0x88 01048 #define RF_RSSICONFIG_OFFSET_M_14_DB 0x90 01049 #define RF_RSSICONFIG_OFFSET_M_13_DB 0x98 01050 #define RF_RSSICONFIG_OFFSET_M_12_DB 0xA0 01051 #define RF_RSSICONFIG_OFFSET_M_11_DB 0xA8 01052 #define RF_RSSICONFIG_OFFSET_M_10_DB 0xB0 01053 #define RF_RSSICONFIG_OFFSET_M_09_DB 0xB8 01054 #define RF_RSSICONFIG_OFFSET_M_08_DB 0xC0 01055 #define RF_RSSICONFIG_OFFSET_M_07_DB 0xC8 01056 #define RF_RSSICONFIG_OFFSET_M_06_DB 0xD0 01057 #define RF_RSSICONFIG_OFFSET_M_05_DB 0xD8 01058 #define RF_RSSICONFIG_OFFSET_M_04_DB 0xE0 01059 #define RF_RSSICONFIG_OFFSET_M_03_DB 0xE8 01060 #define RF_RSSICONFIG_OFFSET_M_02_DB 0xF0 01061 #define RF_RSSICONFIG_OFFSET_M_01_DB 0xF8 01062 01063 #define RF_RSSICONFIG_SMOOTHING_MASK 0xF8 01064 #define RF_RSSICONFIG_SMOOTHING_2 0x00 01065 #define RF_RSSICONFIG_SMOOTHING_4 0x01 01066 #define RF_RSSICONFIG_SMOOTHING_8 0x02 // Default 01067 #define RF_RSSICONFIG_SMOOTHING_16 0x03 01068 #define RF_RSSICONFIG_SMOOTHING_32 0x04 01069 #define RF_RSSICONFIG_SMOOTHING_64 0x05 01070 #define RF_RSSICONFIG_SMOOTHING_128 0x06 01071 #define RF_RSSICONFIG_SMOOTHING_256 0x07 01072 01073 /*! 01074 * RegRssiCollision 01075 */ 01076 #define RF_RSSICOLISION_THRESHOLD 0x0A // Default 01077 01078 /*! 01079 * RegRssiThresh 01080 */ 01081 #define RF_RSSITHRESH_THRESHOLD 0xFF // Default 01082 01083 /*! 01084 * RegRssiValue (Read Only) 01085 */ 01086 01087 /*! 01088 * RegRxBw 01089 */ 01090 #define RF_RXBW_MANT_MASK 0xE7 01091 #define RF_RXBW_MANT_16 0x00 01092 #define RF_RXBW_MANT_20 0x08 01093 #define RF_RXBW_MANT_24 0x10 // Default 01094 01095 #define RF_RXBW_EXP_MASK 0xF8 01096 #define RF_RXBW_EXP_0 0x00 01097 #define RF_RXBW_EXP_1 0x01 01098 #define RF_RXBW_EXP_2 0x02 01099 #define RF_RXBW_EXP_3 0x03 01100 #define RF_RXBW_EXP_4 0x04 01101 #define RF_RXBW_EXP_5 0x05 // Default 01102 #define RF_RXBW_EXP_6 0x06 01103 #define RF_RXBW_EXP_7 0x07 01104 01105 /*! 01106 * RegAfcBw 01107 */ 01108 #define RF_AFCBW_MANTAFC_MASK 0xE7 01109 #define RF_AFCBW_MANTAFC_16 0x00 01110 #define RF_AFCBW_MANTAFC_20 0x08 // Default 01111 #define RF_AFCBW_MANTAFC_24 0x10 01112 01113 #define RF_AFCBW_EXPAFC_MASK 0xF8 01114 #define RF_AFCBW_EXPAFC_0 0x00 01115 #define RF_AFCBW_EXPAFC_1 0x01 01116 #define RF_AFCBW_EXPAFC_2 0x02 01117 #define RF_AFCBW_EXPAFC_3 0x03 // Default 01118 #define RF_AFCBW_EXPAFC_4 0x04 01119 #define RF_AFCBW_EXPAFC_5 0x05 01120 #define RF_AFCBW_EXPAFC_6 0x06 01121 #define RF_AFCBW_EXPAFC_7 0x07 01122 01123 /*! 01124 * RegOokPeak 01125 */ 01126 #define RF_OOKPEAK_BITSYNC_MASK 0xDF // Default 01127 #define RF_OOKPEAK_BITSYNC_ON 0x20 // Default 01128 #define RF_OOKPEAK_BITSYNC_OFF 0x00 01129 01130 #define RF_OOKPEAK_OOKTHRESHTYPE_MASK 0xE7 01131 #define RF_OOKPEAK_OOKTHRESHTYPE_FIXED 0x00 01132 #define RF_OOKPEAK_OOKTHRESHTYPE_PEAK 0x08 // Default 01133 #define RF_OOKPEAK_OOKTHRESHTYPE_AVERAGE 0x10 01134 01135 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_MASK 0xF8 01136 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_0_5_DB 0x00 // Default 01137 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_0_DB 0x01 01138 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_1_5_DB 0x02 01139 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_2_0_DB 0x03 01140 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_3_0_DB 0x04 01141 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_4_0_DB 0x05 01142 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_5_0_DB 0x06 01143 #define RF_OOKPEAK_OOKPEAKTHRESHSTEP_6_0_DB 0x07 01144 01145 /*! 01146 * RegOokFix 01147 */ 01148 #define RF_OOKFIX_OOKFIXEDTHRESHOLD 0x0C // Default 01149 01150 /*! 01151 * RegOokAvg 01152 */ 01153 #define RF_OOKAVG_OOKPEAKTHRESHDEC_MASK 0x1F 01154 #define RF_OOKAVG_OOKPEAKTHRESHDEC_000 0x00 // Default 01155 #define RF_OOKAVG_OOKPEAKTHRESHDEC_001 0x20 01156 #define RF_OOKAVG_OOKPEAKTHRESHDEC_010 0x40 01157 #define RF_OOKAVG_OOKPEAKTHRESHDEC_011 0x60 01158 #define RF_OOKAVG_OOKPEAKTHRESHDEC_100 0x80 01159 #define RF_OOKAVG_OOKPEAKTHRESHDEC_101 0xA0 01160 #define RF_OOKAVG_OOKPEAKTHRESHDEC_110 0xC0 01161 #define RF_OOKAVG_OOKPEAKTHRESHDEC_111 0xE0 01162 01163 #define RF_OOKAVG_AVERAGEOFFSET_MASK 0xF3 01164 #define RF_OOKAVG_AVERAGEOFFSET_0_DB 0x00 // Default 01165 #define RF_OOKAVG_AVERAGEOFFSET_2_DB 0x04 01166 #define RF_OOKAVG_AVERAGEOFFSET_4_DB 0x08 01167 #define RF_OOKAVG_AVERAGEOFFSET_6_DB 0x0C 01168 01169 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_MASK 0xFC 01170 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_00 0x00 01171 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_01 0x01 01172 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_10 0x02 // Default 01173 #define RF_OOKAVG_OOKAVERAGETHRESHFILT_11 0x03 01174 01175 /*! 01176 * RegAfcFei 01177 */ 01178 #define RF_AFCFEI_AGCSTART 0x10 01179 01180 #define RF_AFCFEI_AFCCLEAR 0x02 01181 01182 #define RF_AFCFEI_AFCAUTOCLEAR_MASK 0xFE 01183 #define RF_AFCFEI_AFCAUTOCLEAR_ON 0x01 01184 #define RF_AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 01185 01186 /*! 01187 * RegAfcMsb (Read Only) 01188 */ 01189 01190 /*! 01191 * RegAfcLsb (Read Only) 01192 */ 01193 01194 /*! 01195 * RegFeiMsb (Read Only) 01196 */ 01197 01198 /*! 01199 * RegFeiLsb (Read Only) 01200 */ 01201 01202 /*! 01203 * RegPreambleDetect 01204 */ 01205 #define RF_PREAMBLEDETECT_DETECTOR_MASK 0x7F 01206 #define RF_PREAMBLEDETECT_DETECTOR_ON 0x80 // Default 01207 #define RF_PREAMBLEDETECT_DETECTOR_OFF 0x00 01208 01209 #define RF_PREAMBLEDETECT_DETECTORSIZE_MASK 0x9F 01210 #define RF_PREAMBLEDETECT_DETECTORSIZE_1 0x00 01211 #define RF_PREAMBLEDETECT_DETECTORSIZE_2 0x20 // Default 01212 #define RF_PREAMBLEDETECT_DETECTORSIZE_3 0x40 01213 #define RF_PREAMBLEDETECT_DETECTORSIZE_4 0x60 01214 01215 #define RF_PREAMBLEDETECT_DETECTORTOL_MASK 0xE0 01216 #define RF_PREAMBLEDETECT_DETECTORTOL_0 0x00 01217 #define RF_PREAMBLEDETECT_DETECTORTOL_1 0x01 01218 #define RF_PREAMBLEDETECT_DETECTORTOL_2 0x02 01219 #define RF_PREAMBLEDETECT_DETECTORTOL_3 0x03 01220 #define RF_PREAMBLEDETECT_DETECTORTOL_4 0x04 01221 #define RF_PREAMBLEDETECT_DETECTORTOL_5 0x05 01222 #define RF_PREAMBLEDETECT_DETECTORTOL_6 0x06 01223 #define RF_PREAMBLEDETECT_DETECTORTOL_7 0x07 01224 #define RF_PREAMBLEDETECT_DETECTORTOL_8 0x08 01225 #define RF_PREAMBLEDETECT_DETECTORTOL_9 0x09 01226 #define RF_PREAMBLEDETECT_DETECTORTOL_10 0x0A // Default 01227 #define RF_PREAMBLEDETECT_DETECTORTOL_11 0x0B 01228 #define RF_PREAMBLEDETECT_DETECTORTOL_12 0x0C 01229 #define RF_PREAMBLEDETECT_DETECTORTOL_13 0x0D 01230 #define RF_PREAMBLEDETECT_DETECTORTOL_14 0x0E 01231 #define RF_PREAMBLEDETECT_DETECTORTOL_15 0x0F 01232 #define RF_PREAMBLEDETECT_DETECTORTOL_16 0x10 01233 #define RF_PREAMBLEDETECT_DETECTORTOL_17 0x11 01234 #define RF_PREAMBLEDETECT_DETECTORTOL_18 0x12 01235 #define RF_PREAMBLEDETECT_DETECTORTOL_19 0x13 01236 #define RF_PREAMBLEDETECT_DETECTORTOL_20 0x14 01237 #define RF_PREAMBLEDETECT_DETECTORTOL_21 0x15 01238 #define RF_PREAMBLEDETECT_DETECTORTOL_22 0x16 01239 #define RF_PREAMBLEDETECT_DETECTORTOL_23 0x17 01240 #define RF_PREAMBLEDETECT_DETECTORTOL_24 0x18 01241 #define RF_PREAMBLEDETECT_DETECTORTOL_25 0x19 01242 #define RF_PREAMBLEDETECT_DETECTORTOL_26 0x1A 01243 #define RF_PREAMBLEDETECT_DETECTORTOL_27 0x1B 01244 #define RF_PREAMBLEDETECT_DETECTORTOL_28 0x1C 01245 #define RF_PREAMBLEDETECT_DETECTORTOL_29 0x1D 01246 #define RF_PREAMBLEDETECT_DETECTORTOL_30 0x1E 01247 #define RF_PREAMBLEDETECT_DETECTORTOL_31 0x1F 01248 01249 /*! 01250 * RegRxTimeout1 01251 */ 01252 #define RF_RXTIMEOUT1_TIMEOUTRXRSSI 0x00 // Default 01253 01254 /*! 01255 * RegRxTimeout2 01256 */ 01257 #define RF_RXTIMEOUT2_TIMEOUTRXPREAMBLE 0x00 // Default 01258 01259 /*! 01260 * RegRxTimeout3 01261 */ 01262 #define RF_RXTIMEOUT3_TIMEOUTSIGNALSYNC 0x00 // Default 01263 01264 /*! 01265 * RegRxDelay 01266 */ 01267 #define RF_RXDELAY_INTERPACKETRXDELAY 0x00 // Default 01268 01269 /*! 01270 * RegOsc 01271 */ 01272 #define RF_OSC_RCCALSTART 0x08 01273 01274 #define RF_OSC_CLKOUT_MASK 0xF8 01275 #define RF_OSC_CLKOUT_32_MHZ 0x00 01276 #define RF_OSC_CLKOUT_16_MHZ 0x01 01277 #define RF_OSC_CLKOUT_8_MHZ 0x02 01278 #define RF_OSC_CLKOUT_4_MHZ 0x03 01279 #define RF_OSC_CLKOUT_2_MHZ 0x04 01280 #define RF_OSC_CLKOUT_1_MHZ 0x05 // Default 01281 #define RF_OSC_CLKOUT_RC 0x06 01282 #define RF_OSC_CLKOUT_OFF 0x07 01283 01284 /*! 01285 * RegPreambleMsb/RegPreambleLsb 01286 */ 01287 #define RF_PREAMBLEMSB_SIZE 0x00 // Default 01288 #define RF_PREAMBLELSB_SIZE 0x03 // Default 01289 01290 /*! 01291 * RegSyncConfig 01292 */ 01293 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_MASK 0x3F 01294 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_ON 0x80 // Default 01295 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_WAITPLL_OFF 0x40 01296 #define RF_SYNCCONFIG_AUTORESTARTRXMODE_OFF 0x00 01297 01298 01299 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_MASK 0xDF 01300 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_55 0x20 01301 #define RF_SYNCCONFIG_PREAMBLEPOLARITY_AA 0x00 // Default 01302 01303 #define RF_SYNCCONFIG_SYNC_MASK 0xEF 01304 #define RF_SYNCCONFIG_SYNC_ON 0x10 // Default 01305 #define RF_SYNCCONFIG_SYNC_OFF 0x00 01306 01307 01308 #define RF_SYNCCONFIG_SYNCSIZE_MASK 0xF8 01309 #define RF_SYNCCONFIG_SYNCSIZE_1 0x00 01310 #define RF_SYNCCONFIG_SYNCSIZE_2 0x01 01311 #define RF_SYNCCONFIG_SYNCSIZE_3 0x02 01312 #define RF_SYNCCONFIG_SYNCSIZE_4 0x03 // Default 01313 #define RF_SYNCCONFIG_SYNCSIZE_5 0x04 01314 #define RF_SYNCCONFIG_SYNCSIZE_6 0x05 01315 #define RF_SYNCCONFIG_SYNCSIZE_7 0x06 01316 #define RF_SYNCCONFIG_SYNCSIZE_8 0x07 01317 01318 /*! 01319 * RegSyncValue1-8 01320 */ 01321 #define RF_SYNCVALUE1_SYNCVALUE 0x01 // Default 01322 #define RF_SYNCVALUE2_SYNCVALUE 0x01 // Default 01323 #define RF_SYNCVALUE3_SYNCVALUE 0x01 // Default 01324 #define RF_SYNCVALUE4_SYNCVALUE 0x01 // Default 01325 #define RF_SYNCVALUE5_SYNCVALUE 0x01 // Default 01326 #define RF_SYNCVALUE6_SYNCVALUE 0x01 // Default 01327 #define RF_SYNCVALUE7_SYNCVALUE 0x01 // Default 01328 #define RF_SYNCVALUE8_SYNCVALUE 0x01 // Default 01329 01330 /*! 01331 * RegPacketConfig1 01332 */ 01333 #define RF_PACKETCONFIG1_PACKETFORMAT_MASK 0x7F 01334 #define RF_PACKETCONFIG1_PACKETFORMAT_FIXED 0x00 01335 #define RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE 0x80 // Default 01336 01337 #define RF_PACKETCONFIG1_DCFREE_MASK 0x9F 01338 #define RF_PACKETCONFIG1_DCFREE_OFF 0x00 // Default 01339 #define RF_PACKETCONFIG1_DCFREE_MANCHESTER 0x20 01340 #define RF_PACKETCONFIG1_DCFREE_WHITENING 0x40 01341 01342 #define RF_PACKETCONFIG1_CRC_MASK 0xEF 01343 #define RF_PACKETCONFIG1_CRC_ON 0x10 // Default 01344 #define RF_PACKETCONFIG1_CRC_OFF 0x00 01345 01346 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_MASK 0xF7 01347 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_ON 0x00 // Default 01348 #define RF_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 01349 01350 #define RF_PACKETCONFIG1_ADDRSFILTERING_MASK 0xF9 01351 #define RF_PACKETCONFIG1_ADDRSFILTERING_OFF 0x00 // Default 01352 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODE 0x02 01353 #define RF_PACKETCONFIG1_ADDRSFILTERING_NODEBROADCAST 0x04 01354 01355 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_MASK 0xFE 01356 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_CCITT 0x00 // Default 01357 #define RF_PACKETCONFIG1_CRCWHITENINGTYPE_IBM 0x01 01358 01359 /*! 01360 * RegPacketConfig2 01361 */ 01362 01363 #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE_MASK 0x7F 01364 #define RF_PACKETCONFIG2_WMBUS_CRC_ENABLE 0x80 01365 #define RF_PACKETCONFIG2_WMBUS_CRC_DISABLE 0x00 // Default 01366 01367 #define RF_PACKETCONFIG2_DATAMODE_MASK 0xBF 01368 #define RF_PACKETCONFIG2_DATAMODE_CONTINUOUS 0x00 01369 #define RF_PACKETCONFIG2_DATAMODE_PACKET 0x40 // Default 01370 01371 #define RF_PACKETCONFIG2_IOHOME_MASK 0xDF 01372 #define RF_PACKETCONFIG2_IOHOME_ON 0x20 01373 #define RF_PACKETCONFIG2_IOHOME_OFF 0x00 // Default 01374 01375 #define RF_PACKETCONFIG2_BEACON_MASK 0xF7 01376 #define RF_PACKETCONFIG2_BEACON_ON 0x08 01377 #define RF_PACKETCONFIG2_BEACON_OFF 0x00 // Default 01378 01379 #define RF_PACKETCONFIG2_PAYLOADLENGTH_MSB_MASK 0xF8 01380 01381 /*! 01382 * RegPayloadLength 01383 */ 01384 #define RF_PAYLOADLENGTH_LENGTH 0x40 // Default 01385 01386 /*! 01387 * RegNodeAdrs 01388 */ 01389 #define RF_NODEADDRESS_ADDRESS 0x00 01390 01391 /*! 01392 * RegBroadcastAdrs 01393 */ 01394 #define RF_BROADCASTADDRESS_ADDRESS 0x00 01395 01396 /*! 01397 * RegFifoThresh 01398 */ 01399 #define RF_FIFOTHRESH_TXSTARTCONDITION_MASK 0x7F 01400 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFOTHRESH 0x00 // Default 01401 #define RF_FIFOTHRESH_TXSTARTCONDITION_FIFONOTEMPTY 0x80 01402 01403 #define RF_FIFOTHRESH_FIFOTHRESHOLD_MASK 0xC0 01404 #define RF_FIFOTHRESH_FIFOTHRESHOLD_THRESHOLD 0x0F // Default 01405 01406 /*! 01407 * RegSeqConfig1 01408 */ 01409 #define RF_SEQCONFIG1_SEQUENCER_START 0x80 01410 01411 #define RF_SEQCONFIG1_SEQUENCER_STOP 0x40 01412 01413 #define RF_SEQCONFIG1_IDLEMODE_MASK 0xDF 01414 #define RF_SEQCONFIG1_IDLEMODE_SLEEP 0x20 01415 #define RF_SEQCONFIG1_IDLEMODE_STANDBY 0x00 // Default 01416 01417 #define RF_SEQCONFIG1_FROMSTART_MASK 0xE7 01418 #define RF_SEQCONFIG1_FROMSTART_TOLPS 0x00 // Default 01419 #define RF_SEQCONFIG1_FROMSTART_TORX 0x08 01420 #define RF_SEQCONFIG1_FROMSTART_TOTX 0x10 01421 #define RF_SEQCONFIG1_FROMSTART_TOTX_ONFIFOLEVEL 0x18 01422 01423 #define RF_SEQCONFIG1_LPS_MASK 0xFB 01424 #define RF_SEQCONFIG1_LPS_SEQUENCER_OFF 0x00 // Default 01425 #define RF_SEQCONFIG1_LPS_IDLE 0x04 01426 01427 #define RF_SEQCONFIG1_FROMIDLE_MASK 0xFD 01428 #define RF_SEQCONFIG1_FROMIDLE_TOTX 0x00 // Default 01429 #define RF_SEQCONFIG1_FROMIDLE_TORX 0x02 01430 01431 #define RF_SEQCONFIG1_FROMTX_MASK 0xFE 01432 #define RF_SEQCONFIG1_FROMTX_TOLPS 0x00 // Default 01433 #define RF_SEQCONFIG1_FROMTX_TORX 0x01 01434 01435 /*! 01436 * RegSeqConfig2 01437 */ 01438 #define RF_SEQCONFIG2_FROMRX_MASK 0x1F 01439 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_000 0x00 // Default 01440 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONPLDRDY 0x20 01441 #define RF_SEQCONFIG2_FROMRX_TOLPS_ONPLDRDY 0x40 01442 #define RF_SEQCONFIG2_FROMRX_TORXPKT_ONCRCOK 0x60 01443 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONRSSI 0x80 01444 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONSYNC 0xA0 01445 #define RF_SEQCONFIG2_FROMRX_TOSEQUENCEROFF_ONPREAMBLE 0xC0 01446 #define RF_SEQCONFIG2_FROMRX_TOUNUSED_111 0xE0 01447 01448 #define RF_SEQCONFIG2_FROMRXTIMEOUT_MASK 0xE7 01449 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TORXRESTART 0x00 // Default 01450 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOTX 0x08 01451 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOLPS 0x10 01452 #define RF_SEQCONFIG2_FROMRXTIMEOUT_TOSEQUENCEROFF 0x18 01453 01454 #define RF_SEQCONFIG2_FROMRXPKT_MASK 0xF8 01455 #define RF_SEQCONFIG2_FROMRXPKT_TOSEQUENCEROFF 0x00 // Default 01456 #define RF_SEQCONFIG2_FROMRXPKT_TOTX_ONFIFOEMPTY 0x01 01457 #define RF_SEQCONFIG2_FROMRXPKT_TOLPS 0x02 01458 #define RF_SEQCONFIG2_FROMRXPKT_TOSYNTHESIZERRX 0x03 01459 #define RF_SEQCONFIG2_FROMRXPKT_TORX 0x04 01460 01461 /*! 01462 * RegTimerResol 01463 */ 01464 #define RF_TIMERRESOL_TIMER1RESOL_MASK 0xF3 01465 #define RF_TIMERRESOL_TIMER1RESOL_OFF 0x00 // Default 01466 #define RF_TIMERRESOL_TIMER1RESOL_000064_US 0x04 01467 #define RF_TIMERRESOL_TIMER1RESOL_004100_US 0x08 01468 #define RF_TIMERRESOL_TIMER1RESOL_262000_US 0x0C 01469 01470 #define RF_TIMERRESOL_TIMER2RESOL_MASK 0xFC 01471 #define RF_TIMERRESOL_TIMER2RESOL_OFF 0x00 // Default 01472 #define RF_TIMERRESOL_TIMER2RESOL_000064_US 0x01 01473 #define RF_TIMERRESOL_TIMER2RESOL_004100_US 0x02 01474 #define RF_TIMERRESOL_TIMER2RESOL_262000_US 0x03 01475 01476 /*! 01477 * RegTimer1Coef 01478 */ 01479 #define RF_TIMER1COEF_TIMER1COEFFICIENT 0xF5 // Default 01480 01481 /*! 01482 * RegTimer2Coef 01483 */ 01484 #define RF_TIMER2COEF_TIMER2COEFFICIENT 0x20 // Default 01485 01486 /*! 01487 * RegImageCal 01488 */ 01489 #define RF_IMAGECAL_AUTOIMAGECAL_MASK 0x7F 01490 #define RF_IMAGECAL_AUTOIMAGECAL_ON 0x80 01491 #define RF_IMAGECAL_AUTOIMAGECAL_OFF 0x00 // Default 01492 01493 #define RF_IMAGECAL_IMAGECAL_MASK 0xBF 01494 #define RF_IMAGECAL_IMAGECAL_START 0x40 01495 01496 #define RF_IMAGECAL_IMAGECAL_RUNNING 0x20 01497 #define RF_IMAGECAL_IMAGECAL_DONE 0x00 // Default 01498 01499 #define RF_IMAGECAL_TEMPCHANGE_HIGHER 0x08 01500 #define RF_IMAGECAL_TEMPCHANGE_LOWER 0x00 01501 01502 #define RF_IMAGECAL_TEMPTHRESHOLD_MASK 0xF9 01503 #define RF_IMAGECAL_TEMPTHRESHOLD_05 0x00 01504 #define RF_IMAGECAL_TEMPTHRESHOLD_10 0x02 // Default 01505 #define RF_IMAGECAL_TEMPTHRESHOLD_15 0x04 01506 #define RF_IMAGECAL_TEMPTHRESHOLD_20 0x06 01507 01508 #define RF_IMAGECAL_TEMPMONITOR_MASK 0xFE 01509 #define RF_IMAGECAL_TEMPMONITOR_ON 0x00 // Default 01510 #define RF_IMAGECAL_TEMPMONITOR_OFF 0x01 01511 01512 /*! 01513 * RegTemp (Read Only) 01514 */ 01515 01516 /*! 01517 * RegLowBat 01518 */ 01519 #define RF_LOWBAT_MASK 0xF7 01520 #define RF_LOWBAT_ON 0x08 01521 #define RF_LOWBAT_OFF 0x00 // Default 01522 01523 #define RF_LOWBAT_TRIM_MASK 0xF8 01524 #define RF_LOWBAT_TRIM_1695 0x00 01525 #define RF_LOWBAT_TRIM_1764 0x01 01526 #define RF_LOWBAT_TRIM_1835 0x02 // Default 01527 #define RF_LOWBAT_TRIM_1905 0x03 01528 #define RF_LOWBAT_TRIM_1976 0x04 01529 #define RF_LOWBAT_TRIM_2045 0x05 01530 #define RF_LOWBAT_TRIM_2116 0x06 01531 #define RF_LOWBAT_TRIM_2185 0x07 01532 01533 /*! 01534 * RegIrqFlags1 01535 */ 01536 #define RF_IRQFLAGS1_MODEREADY 0x80 01537 01538 #define RF_IRQFLAGS1_RXREADY 0x40 01539 01540 #define RF_IRQFLAGS1_TXREADY 0x20 01541 01542 #define RF_IRQFLAGS1_PLLLOCK 0x10 01543 01544 #define RF_IRQFLAGS1_RSSI 0x08 01545 01546 #define RF_IRQFLAGS1_TIMEOUT 0x04 01547 01548 #define RF_IRQFLAGS1_PREAMBLEDETECT 0x02 01549 01550 #define RF_IRQFLAGS1_SYNCADDRESSMATCH 0x01 01551 01552 /*! 01553 * RegIrqFlags2 01554 */ 01555 #define RF_IRQFLAGS2_FIFOFULL 0x80 01556 01557 #define RF_IRQFLAGS2_FIFOEMPTY 0x40 01558 01559 #define RF_IRQFLAGS2_FIFOLEVEL 0x20 01560 01561 #define RF_IRQFLAGS2_FIFOOVERRUN 0x10 01562 01563 #define RF_IRQFLAGS2_PACKETSENT 0x08 01564 01565 #define RF_IRQFLAGS2_PAYLOADREADY 0x04 01566 01567 #define RF_IRQFLAGS2_CRCOK 0x02 01568 01569 #define RF_IRQFLAGS2_LOWBAT 0x01 01570 01571 /*! 01572 * RegDioMapping1 01573 */ 01574 #define RF_DIOMAPPING1_DIO0_MASK 0x3F 01575 #define RF_DIOMAPPING1_DIO0_00 0x00 // Default 01576 #define RF_DIOMAPPING1_DIO0_01 0x40 01577 #define RF_DIOMAPPING1_DIO0_10 0x80 01578 #define RF_DIOMAPPING1_DIO0_11 0xC0 01579 01580 #define RF_DIOMAPPING1_DIO1_MASK 0xCF 01581 #define RF_DIOMAPPING1_DIO1_00 0x00 // Default 01582 #define RF_DIOMAPPING1_DIO1_01 0x10 01583 #define RF_DIOMAPPING1_DIO1_10 0x20 01584 #define RF_DIOMAPPING1_DIO1_11 0x30 01585 01586 #define RF_DIOMAPPING1_DIO2_MASK 0xF3 01587 #define RF_DIOMAPPING1_DIO2_00 0x00 // Default 01588 #define RF_DIOMAPPING1_DIO2_01 0x04 01589 #define RF_DIOMAPPING1_DIO2_10 0x08 01590 #define RF_DIOMAPPING1_DIO2_11 0x0C 01591 01592 #define RF_DIOMAPPING1_DIO3_MASK 0xFC 01593 #define RF_DIOMAPPING1_DIO3_00 0x00 // Default 01594 #define RF_DIOMAPPING1_DIO3_01 0x01 01595 #define RF_DIOMAPPING1_DIO3_10 0x02 01596 #define RF_DIOMAPPING1_DIO3_11 0x03 01597 01598 /*! 01599 * RegDioMapping2 01600 */ 01601 #define RF_DIOMAPPING2_DIO4_MASK 0x3F 01602 #define RF_DIOMAPPING2_DIO4_00 0x00 // Default 01603 #define RF_DIOMAPPING2_DIO4_01 0x40 01604 #define RF_DIOMAPPING2_DIO4_10 0x80 01605 #define RF_DIOMAPPING2_DIO4_11 0xC0 01606 01607 #define RF_DIOMAPPING2_DIO5_MASK 0xCF 01608 #define RF_DIOMAPPING2_DIO5_00 0x00 // Default 01609 #define RF_DIOMAPPING2_DIO5_01 0x10 01610 #define RF_DIOMAPPING2_DIO5_10 0x20 01611 #define RF_DIOMAPPING2_DIO5_11 0x30 01612 01613 #define RF_DIOMAPPING2_MAP_MASK 0xFE 01614 #define RF_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 01615 #define RF_DIOMAPPING2_MAP_RSSI 0x00 // Default 01616 01617 /*! 01618 * RegVersion (Read Only) 01619 */ 01620 01621 /*! 01622 * RegPllHop 01623 */ 01624 #define RF_PLLHOP_FASTHOP_MASK 0x7F 01625 #define RF_PLLHOP_FASTHOP_ON 0x80 01626 #define RF_PLLHOP_FASTHOP_OFF 0x00 // Default 01627 01628 /*! 01629 * RegTcxo 01630 */ 01631 #define RF_TCXO_TCXOINPUT_MASK 0xEF 01632 #define RF_TCXO_TCXOINPUT_ON 0x10 01633 #define RF_TCXO_TCXOINPUT_OFF 0x00 // Default 01634 01635 /*! 01636 * RegPaDac 01637 */ 01638 #define RF_PADAC_20DBM_MASK 0xF8 01639 #define RF_PADAC_20DBM_ON 0x07 01640 #define RF_PADAC_20DBM_OFF 0x04 // Default 01641 01642 /*! 01643 * RegFormerTemp 01644 */ 01645 01646 /*! 01647 * RegBitrateFrac 01648 */ 01649 #define RF_BITRATEFRAC_MASK 0xF0 01650 01651 /*! 01652 * RegAgcRef 01653 */ 01654 01655 /*! 01656 * RegAgcThresh1 01657 */ 01658 01659 /*! 01660 * RegAgcThresh2 01661 */ 01662 01663 /*! 01664 * RegAgcThresh3 01665 */ 01666 01667 /*! 01668 * RegPll 01669 */ 01670 #define RF_PLL_BANDWIDTH_MASK 0x3F 01671 #define RF_PLL_BANDWIDTH_75 0x00 01672 #define RF_PLL_BANDWIDTH_150 0x40 01673 #define RF_PLL_BANDWIDTH_225 0x80 01674 #define RF_PLL_BANDWIDTH_300 0xC0 // Default 01675 01676 01677 01678 01679 01680 01681 01682 01683 01684 01685 01686 #endif // __REGISTERS_H__
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