Zoltan Hudak / MODDMA

Fork of Andy Kirkham's MODDMA GPDMA Controller for Mbed OS 6

Read MODDMA for more info.

iomacros.h@20:01d0a680e45a, 16 months ago (annotated)

Committer:
hudakz
Date:
Mon Dec 12 15:08:37 2022 +0000
Revision:
20:01d0a680e45a
Parent:
12:1dfee7208043 
Fork of Andy Kirkham's MODDMA GPDMA Controller for Mbed OS 6.; The examples are updated in order to compile with Mbed OS 6.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AjK 8:cb4d323ce6fd 1 /*
AjK 8:cb4d323ce6fd 2 Copyright (c) 2011 Andy Kirkham
AjK 8:cb4d323ce6fd 3
AjK 8:cb4d323ce6fd 4 Permission is hereby granted, free of charge, to any person obtaining a copy
AjK 8:cb4d323ce6fd 5 of this software and associated documentation files (the "Software"), to deal
AjK 8:cb4d323ce6fd 6 in the Software without restriction, including without limitation the rights
AjK 8:cb4d323ce6fd 7 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
AjK 8:cb4d323ce6fd 8 copies of the Software, and to permit persons to whom the Software is
AjK 8:cb4d323ce6fd 9 furnished to do so, subject to the following conditions:
AjK 8:cb4d323ce6fd 10
AjK 8:cb4d323ce6fd 11 The above copyright notice and this permission notice shall be included in
AjK 8:cb4d323ce6fd 12 all copies or substantial portions of the Software.
AjK 8:cb4d323ce6fd 13
AjK 8:cb4d323ce6fd 14 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
AjK 8:cb4d323ce6fd 15 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
AjK 8:cb4d323ce6fd 16 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AjK 8:cb4d323ce6fd 17 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
AjK 8:cb4d323ce6fd 18 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
AjK 8:cb4d323ce6fd 19 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
AjK 8:cb4d323ce6fd 20 THE SOFTWARE.
AjK 8:cb4d323ce6fd 21 */
AjK 8:cb4d323ce6fd 22
AjK 8:cb4d323ce6fd 23 #ifndef IOMACROS_H
AjK 8:cb4d323ce6fd 24 #define IOMACROS_H
AjK 8:cb4d323ce6fd 25
AjK 8:cb4d323ce6fd 26 #ifndef __LPC17xx_H__
AjK 8:cb4d323ce6fd 27 #include "LPC17xx.h"
AjK 8:cb4d323ce6fd 28 #endif
AjK 8:cb4d323ce6fd 29
AjK 8:cb4d323ce6fd 30 #define PIN_PULLUP 0UL
AjK 8:cb4d323ce6fd 31 #define PIN_REPEAT 1UL
AjK 8:cb4d323ce6fd 32 #define PIN_NONE 2UL
AjK 8:cb4d323ce6fd 33 #define PIN_PULLDOWN 3UL
AjK 8:cb4d323ce6fd 34
AjK 8:cb4d323ce6fd 35 /* p5 is P0.9 */
AjK 8:cb4d323ce6fd 36 #define p5_SEL_MASK ~(3UL << 18)
AjK 8:cb4d323ce6fd 37 #define p5_SET_MASK (1UL << 9)
AjK 8:cb4d323ce6fd 38 #define p5_CLR_MASK ~(p5_SET_MASK)
AjK 8:cb4d323ce6fd 39 #define p5_AS_OUTPUT LPC_PINCON->PINSEL0&=p5_SEL_MASK;LPC_GPIO0->FIODIR|=p5_SET_MASK
AjK 8:cb4d323ce6fd 40 #define p5_AS_INPUT LPC_GPIO0->FIOMASK &= p5_CLR_MASK;
AjK 8:cb4d323ce6fd 41 #define p5_SET LPC_GPIO0->FIOSET = p5_SET_MASK
AjK 8:cb4d323ce6fd 42 #define p5_CLR LPC_GPIO0->FIOCLR = p5_SET_MASK
AjK 8:cb4d323ce6fd 43 #define p5_IS_SET (bool)(LPC_GPIO0->FIOPIN & p5_SET_MASK)
AjK 8:cb4d323ce6fd 44 #define p5_IS_CLR !(p5_IS_SET)
AjK 8:cb4d323ce6fd 45 #define p5_MODE(x) LPC_PINCON->PINMODE0&=p5_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<18)
AjK 8:cb4d323ce6fd 46
AjK 8:cb4d323ce6fd 47 /* p6 is P0.8 */
AjK 8:cb4d323ce6fd 48 #define p6_SEL_MASK ~(3UL << 16)
AjK 8:cb4d323ce6fd 49 #define p6_SET_MASK (1UL << 8)
AjK 8:cb4d323ce6fd 50 #define p6_CLR_MASK ~(p6_SET_MASK)
AjK 8:cb4d323ce6fd 51 #define p6_AS_OUTPUT LPC_PINCON->PINSEL0&=p6_SEL_MASK;LPC_GPIO0->FIODIR|=p6-SET_MASK
AjK 8:cb4d323ce6fd 52 #define p6_AS_INPUT LPC_GPIO0->FIOMASK &= p6_CLR_MASK;
AjK 8:cb4d323ce6fd 53 #define p6_SET LPC_GPIO0->FIOSET = p6_SET_MASK
AjK 8:cb4d323ce6fd 54 #define p6_CLR LPC_GPIO0->FIOCLR = p6_SET_MASK
AjK 8:cb4d323ce6fd 55 #define p6_IS_SET (bool)(LPC_GPIO0->FIOPIN & p6_SET_MASK)
AjK 8:cb4d323ce6fd 56 #define p6_IS_CLR !(p6_IS_SET)
AjK 8:cb4d323ce6fd 57 #define p6_MODE(x) LPC_PINCON->PINMODE0&=p6_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<16)
AjK 8:cb4d323ce6fd 58
AjK 8:cb4d323ce6fd 59 /* p7 is P0.7 */
AjK 8:cb4d323ce6fd 60 #define p7_SEL_MASK ~(3UL << 14)
AjK 8:cb4d323ce6fd 61 #define p7_SET_MASK (1UL << 7)
AjK 8:cb4d323ce6fd 62 #define p7_CLR_MASK ~(p7_SET_MASK)
AjK 8:cb4d323ce6fd 63 #define p7_AS_OUTPUT LPC_PINCON->PINSEL0&=p7_SEL_MASK;LPC_GPIO0->FIODIR|=p7_SET_MASK
AjK 8:cb4d323ce6fd 64 #define p7_AS_INPUT LPC_GPIO0->FIOMASK &= p7_CLR_MASK;
AjK 8:cb4d323ce6fd 65 #define p7_SET LPC_GPIO0->FIOSET = p7_SET_MASK
AjK 8:cb4d323ce6fd 66 #define p7_CLR LPC_GPIO0->FIOCLR = p7_SET_MASK
AjK 8:cb4d323ce6fd 67 #define p7_IS_SET (bool)(LPC_GPIO0->FIOPIN & p7_SET_MASK)
AjK 8:cb4d323ce6fd 68 #define p7_IS_CLR !(p7_IS_SET)
AjK 8:cb4d323ce6fd 69 #define p7_MODE(x) LPC_PINCON->PINMODE0&=p7_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<14)
AjK 8:cb4d323ce6fd 70
AjK 8:cb4d323ce6fd 71 /* p8 is P0.6 */
AjK 8:cb4d323ce6fd 72 #define p8_SEL_MASK ~(3UL << 12)
AjK 8:cb4d323ce6fd 73 #define p8_SET_MASK (1UL << 6)
AjK 12:1dfee7208043 74 #define p8_CLR_MASK ~(p8_SET_MASK)
AjK 8:cb4d323ce6fd 75 #define p8_AS_OUTPUT LPC_PINCON->PINSEL0&=p8_SEL_MASK;LPC_GPIO0->FIODIR|=p8_SET_MASK
AjK 8:cb4d323ce6fd 76 #define p8_AS_INPUT LPC_GPIO0->FIOMASK &= p8_CLR_MASK;
AjK 8:cb4d323ce6fd 77 #define p8_SET LPC_GPIO0->FIOSET = p8_SET_MASK
AjK 8:cb4d323ce6fd 78 #define p8_CLR LPC_GPIO0->FIOCLR = p8_SET_MASK
AjK 8:cb4d323ce6fd 79 #define p8_IS_SET (bool)(LPC_GPIO0->FIOPIN & p8_SET_MASK)
AjK 8:cb4d323ce6fd 80 #define p8_IS_CLR !(p8_IS_SET)
AjK 8:cb4d323ce6fd 81 #define p8_MODE(x) LPC_PINCON->PINMODE0&=p8_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<12)
AjK 8:cb4d323ce6fd 82
AjK 8:cb4d323ce6fd 83 /* p9 is P0.0 */
AjK 8:cb4d323ce6fd 84 #define p9_SEL_MASK ~(3UL << 0)
AjK 8:cb4d323ce6fd 85 #define p9_SET_MASK (1UL << 0)
AjK 8:cb4d323ce6fd 86 #define p9_CLR_MASK ~(p9_SET_MASK)
AjK 8:cb4d323ce6fd 87 #define p9_AS_OUTPUT LPC_PINCON->PINSEL0&=p9_SEL_MASK;LPC_GPIO0->FIODIR|=p9_SET_MASK
AjK 8:cb4d323ce6fd 88 #define p9_AS_INPUT LPC_GPIO0->FIOMASK &= p9_CLR_MASK;
AjK 8:cb4d323ce6fd 89 #define p9_SET LPC_GPIO0->FIOSET = p9_SET_MASK
AjK 8:cb4d323ce6fd 90 #define p9_CLR LPC_GPIO0->FIOCLR = p9_SET_MASK
AjK 8:cb4d323ce6fd 91 #define p9_IS_SET (bool)(LPC_GPIO0->FIOPIN & p9_SET_MASK)
AjK 8:cb4d323ce6fd 92 #define p9_IS_CLR !(p9_IS_SET)
AjK 8:cb4d323ce6fd 93 #define p9_MODE(x) LPC_PINCON->PINMODE0&=p9_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<0)
AjK 8:cb4d323ce6fd 94
AjK 8:cb4d323ce6fd 95 /* p10 is P0.1 */
AjK 8:cb4d323ce6fd 96 #define p10_SEL_MASK ~(3UL << 2)
AjK 8:cb4d323ce6fd 97 #define p10_SET_MASK (1UL << 1)
AjK 8:cb4d323ce6fd 98 #define p10_CLR_MASK ~(p10_SET_MASK)
AjK 8:cb4d323ce6fd 99 #define p10_AS_OUTPUT LPC_PINCON->PINSEL0&=p10_SEL_MASK;LPC_GPIO0->FIODIR|=p10_SET_MASK
AjK 8:cb4d323ce6fd 100 #define p10_AS_INPUT LPC_GPIO0->FIOMASK &= p10_CLR_MASK;
AjK 8:cb4d323ce6fd 101 #define p10_SET LPC_GPIO0->FIOSET = p10_SET_MASK
AjK 8:cb4d323ce6fd 102 #define p10_CLR LPC_GPIO0->FIOCLR = p10_SET_MASK
AjK 8:cb4d323ce6fd 103 #define p10_IS_SET (bool)(LPC_GPIO0->FIOPIN & p10_SET_MASK)
AjK 8:cb4d323ce6fd 104 #define p10_IS_CLR !(p10_IS_SET)
AjK 8:cb4d323ce6fd 105 #define p10_MODE(x) LPC_PINCON->PINMODE0&=p10_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<2)
AjK 8:cb4d323ce6fd 106
AjK 8:cb4d323ce6fd 107 /* p11 is P0.18 */
AjK 8:cb4d323ce6fd 108 #define p11_SEL_MASK ~(3UL << 4)
AjK 8:cb4d323ce6fd 109 #define p11_SET_MASK (1UL << 18)
AjK 8:cb4d323ce6fd 110 #define p11_CLR_MASK ~(p11_SET_MASK)
AjK 8:cb4d323ce6fd 111 #define p11_AS_OUTPUT LPC_PINCON->PINSEL1&=p11_SEL_MASK;LPC_GPIO0->FIODIR|=p11_SET_MASK
AjK 8:cb4d323ce6fd 112 #define p11_AS_INPUT LPC_GPIO0->FIOMASK &= p11_CLR_MASK;
AjK 8:cb4d323ce6fd 113 #define p11_SET LPC_GPIO0->FIOSET = p11_SET_MASK
AjK 8:cb4d323ce6fd 114 #define p11_CLR LPC_GPIO0->FIOCLR = p11_SET_MASK
AjK 8:cb4d323ce6fd 115 #define p11_IS_SET (bool)(LPC_GPIO0->FIOPIN & p11_SET_MASK)
AjK 8:cb4d323ce6fd 116 #define p11_IS_CLR !(p11_IS_SET)
AjK 8:cb4d323ce6fd 117 #define p11_MODE(x) LPC_PINCON->PINMODE1&=p11_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<4)
AjK 8:cb4d323ce6fd 118
AjK 8:cb4d323ce6fd 119 /* p12 is P0.17 */
AjK 8:cb4d323ce6fd 120 #define p12_SEL_MASK ~(3UL << 2)
AjK 8:cb4d323ce6fd 121 #define p12_SET_MASK (1UL << 17)
AjK 8:cb4d323ce6fd 122 #define p12_CLR_MASK ~(p12_SET_MASK)
AjK 8:cb4d323ce6fd 123 #define p12_AS_OUTPUT LPC_PINCON->PINSEL1&=p12_SEL_MASK;LPC_GPIO0->FIODIR|=p12_SET_MASK
AjK 8:cb4d323ce6fd 124 #define p12_AS_INPUT LPC_GPIO0->FIOMASK &= p12_CLR_MASK;
AjK 8:cb4d323ce6fd 125 #define p12_SET LPC_GPIO0->FIOSET = p12_SET_MASK
AjK 8:cb4d323ce6fd 126 #define p12_CLR LPC_GPIO0->FIOCLR = p12_SET_MASK
AjK 8:cb4d323ce6fd 127 #define p12_IS_SET (bool)(LPC_GPIO0->FIOPIN & p12_SET_MASK)
AjK 8:cb4d323ce6fd 128 #define p12_IS_CLR !(p12_IS_SET)
AjK 8:cb4d323ce6fd 129 #define p12_MODE(x) LPC_PINCON->PINMODE1&=p12_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<2)
AjK 8:cb4d323ce6fd 130
AjK 8:cb4d323ce6fd 131 /* p13 is P0.15 */
AjK 8:cb4d323ce6fd 132 #define p13_SEL_MASK ~(3UL << 30)
AjK 8:cb4d323ce6fd 133 #define p13_SET_MASK (1UL << 15)
AjK 8:cb4d323ce6fd 134 #define p13_CLR_MASK ~(p13_SET_MASK)
AjK 8:cb4d323ce6fd 135 #define p13_AS_OUTPUT LPC_PINCON->PINSEL0&=p13_SEL_MASK;LPC_GPIO0->FIODIR|=p13_SET_MASK
AjK 8:cb4d323ce6fd 136 #define p13_AS_INPUT LPC_GPIO0->FIOMASK &= p13_CLR_MASK;
AjK 8:cb4d323ce6fd 137 #define p13_SET LPC_GPIO0->FIOSET = p13_SET_MASK
AjK 8:cb4d323ce6fd 138 #define p13_CLR LPC_GPIO0->FIOCLR = p13_SET_MASK
AjK 8:cb4d323ce6fd 139 #define p13_IS_SET (bool)(LPC_GPIO0->FIOPIN & p13_SET_MASK)
AjK 8:cb4d323ce6fd 140 #define p13_IS_CLR !(p13_IS_SET)
AjK 8:cb4d323ce6fd 141 #define p13_MODE(x) LPC_PINCON->PINMODE0&=p13_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<30)
AjK 8:cb4d323ce6fd 142
AjK 8:cb4d323ce6fd 143 /* p14 is P0.16 */
AjK 8:cb4d323ce6fd 144 #define p14_SEL_MASK ~(3UL << 0)
AjK 8:cb4d323ce6fd 145 #define p14_SET_MASK (1UL << 16)
AjK 8:cb4d323ce6fd 146 #define p14_CLR_MASK ~(p14_SET_MASK)
AjK 8:cb4d323ce6fd 147 #define p14_AS_OUTPUT LPC_PINCON->PINSEL1&=p14_SEL_MASK;LPC_GPIO0->FIODIR|=p14_SET_MASK
AjK 8:cb4d323ce6fd 148 #define p14_AS_INPUT LPC_GPIO0->FIOMASK &= p14_CLR_MASK;
AjK 8:cb4d323ce6fd 149 #define p14_SET LPC_GPIO0->FIOSET = p14_SET_MASK
AjK 8:cb4d323ce6fd 150 #define p14_CLR LPC_GPIO0->FIOCLR = p14_SET_MASK
AjK 8:cb4d323ce6fd 151 #define p14_IS_SET (bool)(LPC_GPIO0->FIOPIN & p14_SET_MASK)
AjK 8:cb4d323ce6fd 152 #define p14_IS_CLR !(p14_IS_SET)
AjK 8:cb4d323ce6fd 153 #define p14_MODE(x) LPC_PINCON->PINMODE1&=p14_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<0)
AjK 8:cb4d323ce6fd 154
AjK 8:cb4d323ce6fd 155 /* p15 is P0.23 */
AjK 8:cb4d323ce6fd 156 #define p15_SEL_MASK ~(3UL << 14)
AjK 8:cb4d323ce6fd 157 #define p15_SET_MASK (1UL << 23)
AjK 8:cb4d323ce6fd 158 #define p15_CLR_MASK ~(p15_SET_MASK)
AjK 8:cb4d323ce6fd 159 #define p15_AS_OUTPUT LPC_PINCON->PINSEL1&=p15_SEL_MASK;LPC_GPIO0->FIODIR|=p15_SET_MASK
AjK 8:cb4d323ce6fd 160 #define p15_AS_INPUT LPC_GPIO0->FIOMASK &= p15_CLR_MASK;
AjK 8:cb4d323ce6fd 161 #define p15_SET LPC_GPIO0->FIOSET = p15_SET_MASK
AjK 8:cb4d323ce6fd 162 #define p15_CLR LPC_GPIO0->FIOCLR = p15_SET_MASK
AjK 8:cb4d323ce6fd 163 #define p15_IS_SET (bool)(LPC_GPIO0->FIOPIN & p15_SET_MASK)
AjK 8:cb4d323ce6fd 164 #define p15_IS_CLR !(p15_IS_SET)
AjK 8:cb4d323ce6fd 165 #define p15_MODE(x) LPC_PINCON->PINMODE1&=p15_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<14)
AjK 8:cb4d323ce6fd 166
AjK 8:cb4d323ce6fd 167 /* p16 is P0.24 */
AjK 8:cb4d323ce6fd 168 #define p16_SEL_MASK ~(3UL << 16)
AjK 8:cb4d323ce6fd 169 #define p16_SET_MASK (1UL << 24)
AjK 8:cb4d323ce6fd 170 #define p16_CLR_MASK ~(p16_SET_MASK)
AjK 8:cb4d323ce6fd 171 #define p16_AS_OUTPUT LPC_PINCON->PINSEL1&=p16_SEL_MASK;LPC_GPIO0->FIODIR|=p16_SET_MASK
AjK 8:cb4d323ce6fd 172 #define p16_AS_INPUT LPC_GPIO0->FIOMASK &= p16_CLR_MASK;
AjK 8:cb4d323ce6fd 173 #define p16_SET LPC_GPIO0->FIOSET = p16_SET_MASK
AjK 8:cb4d323ce6fd 174 #define p16_CLR LPC_GPIO0->FIOCLR = p16_SET_MASK
AjK 8:cb4d323ce6fd 175 #define p16_IS_SET (bool)(LPC_GPIO0->FIOPIN & p16_SET_MASK)
AjK 8:cb4d323ce6fd 176 #define p16_IS_CLR !(p16_IS_SET)
AjK 8:cb4d323ce6fd 177 #define p16_MODE(x) LPC_PINCON->PINMODE1&=p16_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<16)
AjK 8:cb4d323ce6fd 178
AjK 8:cb4d323ce6fd 179 /* p17 is P0.25 */
AjK 8:cb4d323ce6fd 180 #define p17_SEL_MASK ~(3UL << 18)
AjK 8:cb4d323ce6fd 181 #define p17_SET_MASK (1UL << 25)
AjK 8:cb4d323ce6fd 182 #define p17_CLR_MASK ~(p17_SET_MASK)
AjK 8:cb4d323ce6fd 183 #define p17_AS_OUTPUT LPC_PINCON->PINSEL1&=p17_SEL_MASK;LPC_GPIO0->FIODIR|=p17_SET_MASK
AjK 8:cb4d323ce6fd 184 #define p17_AS_INPUT LPC_GPIO0->FIOMASK &= p17_CLR_MASK;
AjK 8:cb4d323ce6fd 185 #define p17_SET LPC_GPIO0->FIOSET = p17_SET_MASK
AjK 8:cb4d323ce6fd 186 #define p17_CLR LPC_GPIO0->FIOCLR = p17_SET_MASK
AjK 8:cb4d323ce6fd 187 #define p17_IS_SET (bool)(LPC_GPIO0->FIOPIN & p17_SET_MASK)
AjK 8:cb4d323ce6fd 188 #define p17_IS_CLR !(p17_IS_SET)
AjK 8:cb4d323ce6fd 189 #define p17_MODE(x) LPC_PINCON->PINMODE1&=p17_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<18)
AjK 8:cb4d323ce6fd 190
AjK 8:cb4d323ce6fd 191 /* p18 is P0.26 */
AjK 8:cb4d323ce6fd 192 #define p18_SEL_MASK ~(3UL << 20)
AjK 8:cb4d323ce6fd 193 #define p18_SET_MASK (1UL << 26)
AjK 8:cb4d323ce6fd 194 #define p18_CLR_MASK ~(p18_SET_MASK)
AjK 8:cb4d323ce6fd 195 #define p18_AS_OUTPUT LPC_PINCON->PINSEL1&=p18_SEL_MASK;LPC_GPIO0->FIODIR|=p18_SET_MASK
AjK 8:cb4d323ce6fd 196 #define p18_AS_INPUT LPC_GPIO0->FIOMASK &= p18_CLR_MASK;
AjK 8:cb4d323ce6fd 197 #define p18_SET LPC_GPIO0->FIOSET = p18_SET_MASK
AjK 8:cb4d323ce6fd 198 #define p18_CLR LPC_GPIO0->FIOCLR = p18_SET_MASK
AjK 8:cb4d323ce6fd 199 #define p18_IS_SET (bool)(LPC_GPIO0->FIOPIN & p18_SET_MASK)
AjK 8:cb4d323ce6fd 200 #define p18_IS_CLR !(p18_IS_SET)
AjK 8:cb4d323ce6fd 201 #define p18_MODE(x) LPC_PINCON->PINMODE1&=p18_SEL_MASK;LPC_PINCON->PINMODE1|=((x&0x3)<<20)
AjK 8:cb4d323ce6fd 202
AjK 8:cb4d323ce6fd 203 /* p19 is P1.30 */
AjK 8:cb4d323ce6fd 204 #define p19_SEL_MASK ~(3UL << 28)
AjK 8:cb4d323ce6fd 205 #define p19_SET_MASK (1UL << 30)
AjK 8:cb4d323ce6fd 206 #define p19_AS_OUTPUT LPC_PINCON->PINSEL3&=p19_SEL_MASK;LPC_GPIO1->FIODIR|=p19_SET_MASK
AjK 8:cb4d323ce6fd 207 #define p19_AS_INPUT LPC_GPIO1->FIOMASK &= p19_CLR_MASK;
AjK 8:cb4d323ce6fd 208 #define p19_SET LPC_GPIO1->FIOSET = p19_SET_MASK
AjK 8:cb4d323ce6fd 209 #define p19_CLR LPC_GPIO1->FIOCLR = p19_SET_MASK
AjK 8:cb4d323ce6fd 210 #define p19_IS_SET (bool)(LPC_GPIO1->FIOPIN & p19_SET_MASK)
AjK 8:cb4d323ce6fd 211 #define p19_IS_CLR !(p19_IS_SET)
AjK 8:cb4d323ce6fd 212 #define p19_MODE(x) LPC_PINCON->PINMODE3&=p19_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<28)
AjK 8:cb4d323ce6fd 213
AjK 8:cb4d323ce6fd 214 /* p20 is P1.31 */
AjK 8:cb4d323ce6fd 215 #define p20_SEL_MASK ~(3UL << 30)
AjK 8:cb4d323ce6fd 216 #define p20_SET_MASK (1UL << 31)
AjK 8:cb4d323ce6fd 217 #define p20_CLR_MASK ~(p20_SET_MASK)
AjK 8:cb4d323ce6fd 218 #define p20_AS_OUTPUT LPC_PINCON->PINSEL3&=p20_SEL_MASK;LPC_GPIO1->FIODIR|=p20_SET_MASK
AjK 8:cb4d323ce6fd 219 #define p20_AS_INPUT LPC_GPIO1->FIOMASK &= p20_CLR_MASK;
AjK 8:cb4d323ce6fd 220 #define p20_SET LPC_GPIO1->FIOSET = p20_SET_MASK
AjK 8:cb4d323ce6fd 221 #define p20_CLR LPC_GPIO1->FIOCLR = p20_SET_MASK
AjK 8:cb4d323ce6fd 222 #define p20_IS_SET (bool)(LPC_GPIO1->FIOPIN & p20_SET_MASK)
AjK 8:cb4d323ce6fd 223 #define p20_IS_CLR !(p20_IS_SET)
AjK 8:cb4d323ce6fd 224 #define p20_MODE(x) LPC_PINCON->PINMODE3&=p20_SEL_MASK;LPC_PINCON->PINMODE3|=((x&0x3)<<30)
AjK 8:cb4d323ce6fd 225
AjK 8:cb4d323ce6fd 226 /* p21 is P2.5 */
AjK 8:cb4d323ce6fd 227 #define p21_SEL_MASK ~(3UL << 10)
AjK 8:cb4d323ce6fd 228 #define p21_SET_MASK (1UL << 5)
AjK 8:cb4d323ce6fd 229 #define p21_CLR_MASK ~(p21_SET_MASK)
AjK 8:cb4d323ce6fd 230 #define p21_AS_OUTPUT LPC_PINCON->PINSEL4&=p21_SEL_MASK;LPC_GPIO2->FIODIR|=p21_SET_MASK
AjK 8:cb4d323ce6fd 231 #define p21_AS_INPUT LPC_GPIO2->FIOMASK &= p21_CLR_MASK;
AjK 8:cb4d323ce6fd 232 #define p21_SET LPC_GPIO2->FIOSET = p21_SET_MASK
AjK 8:cb4d323ce6fd 233 #define p21_CLR LPC_GPIO2->FIOCLR = p21_SET_MASK
AjK 8:cb4d323ce6fd 234 #define p21_IS_SET (bool)(LPC_GPIO2->FIOPIN & p21_SET_MASK)
AjK 8:cb4d323ce6fd 235 #define p21_IS_CLR !(p21_IS_SET)
AjK 8:cb4d323ce6fd 236 #define p21_TOGGLE p21_IS_SET?p21_CLR:p21_SET
AjK 8:cb4d323ce6fd 237 #define p21_MODE(x) LPC_PINCON->PINMODE4&=p21_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<10)
AjK 8:cb4d323ce6fd 238
AjK 8:cb4d323ce6fd 239 /* p22 is P2.4 */
AjK 8:cb4d323ce6fd 240 #define p22_SEL_MASK ~(3UL << 8)
AjK 8:cb4d323ce6fd 241 #define p22_SET_MASK (1UL << 4)
AjK 8:cb4d323ce6fd 242 #define p22_CLR_MASK ~(p22_SET_MASK)
AjK 8:cb4d323ce6fd 243 #define p22_AS_OUTPUT LPC_PINCON->PINSEL4&=p22_SEL_MASK;LPC_GPIO2->FIODIR|=p22_SET_MASK
AjK 8:cb4d323ce6fd 244 #define p22_AS_INPUT LPC_GPIO2->FIOMASK &= p22_CLR_MASK;
AjK 8:cb4d323ce6fd 245 #define p22_SET LPC_GPIO2->FIOSET = p22_SET_MASK
AjK 8:cb4d323ce6fd 246 #define p22_CLR LPC_GPIO2->FIOCLR = p22_SET_MASK
AjK 8:cb4d323ce6fd 247 #define p22_IS_SET (bool)(LPC_GPIO2->FIOPIN & p22_SET_MASK)
AjK 8:cb4d323ce6fd 248 #define p22_IS_CLR !(p22_IS_SET)
AjK 8:cb4d323ce6fd 249 #define p22_TOGGLE p22_IS_SET?p22_CLR:p22_SET
AjK 8:cb4d323ce6fd 250 #define p22_MODE(x) LPC_PINCON->PINMODE4&=p22_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<8)
AjK 8:cb4d323ce6fd 251
AjK 8:cb4d323ce6fd 252 /* p23 is P2.3 */
AjK 8:cb4d323ce6fd 253 #define p23_SEL_MASK ~(3UL << 6)
AjK 8:cb4d323ce6fd 254 #define p23_SET_MASK (1UL << 3)
AjK 8:cb4d323ce6fd 255 #define p23_CLR_MASK ~(p23_SET_MASK)
AjK 8:cb4d323ce6fd 256 #define p23_AS_OUTPUT LPC_PINCON->PINSEL4&=p23_SEL_MASK;LPC_GPIO2->FIODIR|=p23_SET_MASK
AjK 8:cb4d323ce6fd 257 #define p23_AS_INPUT LPC_GPIO2->FIOMASK &= p23_CLR_MASK;
AjK 8:cb4d323ce6fd 258 #define p23_SET LPC_GPIO2->FIOSET = p23_SET_MASK
AjK 8:cb4d323ce6fd 259 #define p23_CLR LPC_GPIO2->FIOCLR = p23_SET_MASK
AjK 8:cb4d323ce6fd 260 #define p23_IS_SET (bool)(LPC_GPIO2->FIOPIN & p23_SET_MASK)
AjK 8:cb4d323ce6fd 261 #define p23_IS_CLR !(p23_IS_SET)
AjK 8:cb4d323ce6fd 262 #define p23_TOGGLE p23_IS_SET?p23_CLR:p23_SET
AjK 8:cb4d323ce6fd 263 #define p23_MODE(x) LPC_PINCON->PINMODE4&=p23_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<6)
AjK 8:cb4d323ce6fd 264
AjK 8:cb4d323ce6fd 265 /* p24 is P2.2 */
AjK 8:cb4d323ce6fd 266 #define p24_SEL_MASK ~(3UL << 4)
AjK 8:cb4d323ce6fd 267 #define p24_SET_MASK (1UL << 2)
AjK 8:cb4d323ce6fd 268 #define p24_CLR_MASK ~(p24_SET_MASK)
AjK 8:cb4d323ce6fd 269 #define p24_AS_OUTPUT LPC_PINCON->PINSEL4&=p24_SEL_MASK;LPC_GPIO2->FIODIR|=p24_SET_MASK
AjK 8:cb4d323ce6fd 270 #define p24_AS_INPUT LPC_GPIO2->FIOMASK &= p24_CLR_MASK;
AjK 8:cb4d323ce6fd 271 #define p24_SET LPC_GPIO2->FIOSET = p24_SET_MASK
AjK 8:cb4d323ce6fd 272 #define p24_CLR LPC_GPIO2->FIOCLR = p24_SET_MASK
AjK 8:cb4d323ce6fd 273 #define p24_IS_SET (bool)(LPC_GPIO2->FIOPIN & p24_SET_MASK)
AjK 8:cb4d323ce6fd 274 #define p24_IS_CLR !(p24_IS_SET)
AjK 8:cb4d323ce6fd 275 #define p24_TOGGLE p24_IS_SET?p24_CLR:p24_SET
AjK 8:cb4d323ce6fd 276 #define p24_MODE(x) LPC_PINCON->PINMODE4&=p24_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<4)
AjK 8:cb4d323ce6fd 277
AjK 8:cb4d323ce6fd 278 /* p25 is P2.1 */
AjK 8:cb4d323ce6fd 279 #define p25_SEL_MASK ~(3UL << 2)
AjK 8:cb4d323ce6fd 280 #define p25_SET_MASK (1UL << 1)
AjK 8:cb4d323ce6fd 281 #define p25_CLR_MASK ~(p25_SET_MASK)
AjK 8:cb4d323ce6fd 282 #define p25_AS_OUTPUT LPC_PINCON->PINSEL4&=p25_SEL_MASK;LPC_GPIO2->FIODIR|=p25_SET_MASK
AjK 8:cb4d323ce6fd 283 #define p25_AS_INPUT LPC_GPIO2->FIOMASK &= p25_CLR_MASK;
AjK 8:cb4d323ce6fd 284 #define p25_SET LPC_GPIO2->FIOSET = p25_SET_MASK
AjK 8:cb4d323ce6fd 285 #define p25_CLR LPC_GPIO2->FIOCLR = p25_SET_MASK
AjK 8:cb4d323ce6fd 286 #define p25_IS_SET (bool)(LPC_GPIO2->FIOPIN & p25_SET_MASK)
AjK 8:cb4d323ce6fd 287 #define p25_IS_CLR !(p25_IS_SET)
AjK 8:cb4d323ce6fd 288 #define p25_MODE(x) LPC_PINCON->PINMODE4&=p25_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<2)
AjK 8:cb4d323ce6fd 289
AjK 8:cb4d323ce6fd 290 /* p26 is P2.0 */
AjK 8:cb4d323ce6fd 291 #define p26_SEL_MASK ~(3UL << 0)
AjK 8:cb4d323ce6fd 292 #define p26_SET_MASK (1UL << 0)
AjK 8:cb4d323ce6fd 293 #define p26_CLR_MASK ~(p26_SET_MASK)
AjK 8:cb4d323ce6fd 294 #define p26_AS_OUTPUT LPC_PINCON->PINSEL4&=p26_SEL_MASK;LPC_GPIO2->FIODIR|=p26_SET_MASK
AjK 8:cb4d323ce6fd 295 #define p26_AS_INPUT LPC_GPIO2->FIOMASK &= p26_CLR_MASK;
AjK 8:cb4d323ce6fd 296 #define p26_SET LPC_GPIO2->FIOSET = p26_SET_MASK
AjK 8:cb4d323ce6fd 297 #define p26_CLR LPC_GPIO2->FIOCLR = p26_SET_MASK
AjK 8:cb4d323ce6fd 298 #define p26_IS_SET (bool)(LPC_GPIO2->FIOPIN & p26_SET_MASK)
AjK 8:cb4d323ce6fd 299 #define p26_IS_CLR !(p26_IS_SET)
AjK 8:cb4d323ce6fd 300 #define p26_MODE(x) LPC_PINCON->PINMODE4&=p26_SEL_MASK;LPC_PINCON->PINMODE4|=((x&0x3)<<0)
AjK 8:cb4d323ce6fd 301
AjK 8:cb4d323ce6fd 302 /* p27 is P0.11 */
AjK 8:cb4d323ce6fd 303 #define p27_SEL_MASK ~(3UL << 22)
AjK 8:cb4d323ce6fd 304 #define p27_SET_MASK (1UL << 11)
AjK 8:cb4d323ce6fd 305 #define p27_CLR_MASK ~(p27_SET_MASK)
AjK 8:cb4d323ce6fd 306 #define p27_AS_OUTPUT LPC_PINCON->PINSEL0&=p27_SEL_MASK;LPC_GPIO0->FIODIR|=p27_SET_MASK
AjK 8:cb4d323ce6fd 307 #define p27_AS_INPUT LPC_GPIO0->FIOMASK &= p27_CLR_MASK;
AjK 8:cb4d323ce6fd 308 #define p27_SET LPC_GPIO0->FIOSET = p27_SET_MASK
AjK 8:cb4d323ce6fd 309 #define p27_CLR LPC_GPIO0->FIOCLR = p27_SET_MASK
AjK 8:cb4d323ce6fd 310 #define p27_IS_SET (bool)(LPC_GPIO0->FIOPIN & p27_SET_MASK)
AjK 8:cb4d323ce6fd 311 #define p27_IS_CLR !(p27_IS_SET)
AjK 8:cb4d323ce6fd 312 #define p27_MODE(x) LPC_PINCON->PINMODE0&=p27_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<22)
AjK 8:cb4d323ce6fd 313
AjK 8:cb4d323ce6fd 314 /* p28 is P0.10 */
AjK 8:cb4d323ce6fd 315 #define p28_SEL_MASK ~(3UL << 20)
AjK 8:cb4d323ce6fd 316 #define p28_SET_MASK (1UL << 10)
AjK 8:cb4d323ce6fd 317 #define p28_CLR_MASK ~(p28_SET_MASK)
AjK 8:cb4d323ce6fd 318 #define p28_AS_OUTPUT LPC_PINCON->PINSEL0&=p28_SEL_MASK;LPC_GPIO0->FIODIR|=p28_SET_MASK
AjK 8:cb4d323ce6fd 319 #define p28_AS_INPUT LPC_GPIO0->FIOMASK &= p28_CLR_MASK;
AjK 8:cb4d323ce6fd 320 #define p28_SET LPC_GPIO0->FIOSET = p28_SET_MASK
AjK 8:cb4d323ce6fd 321 #define p28_CLR LPC_GPIO0->FIOCLR = p28_SET_MASK
AjK 8:cb4d323ce6fd 322 #define p28_IS_SET (bool)(LPC_GPIO0->FIOPIN & p28_SET_MASK)
AjK 8:cb4d323ce6fd 323 #define p28_IS_CLR !(p28_IS_SET)
AjK 8:cb4d323ce6fd 324 #define p28_MODE(x) LPC_PINCON->PINMODE0&=p28_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<20)
AjK 8:cb4d323ce6fd 325
AjK 8:cb4d323ce6fd 326 /* p29 is P0.5 */
AjK 8:cb4d323ce6fd 327 #define p29_SEL_MASK ~(3UL << 10)
AjK 8:cb4d323ce6fd 328 #define p29_SET_MASK (1UL << 5)
AjK 8:cb4d323ce6fd 329 #define p29_CLR_MASK ~(p29_SET_MASK)
AjK 8:cb4d323ce6fd 330 #define p29_AS_OUTPUT LPC_PINCON->PINSEL0&=p29_SEL_MASK;LPC_GPIO0->FIODIR|=p29_SET_MASK
AjK 8:cb4d323ce6fd 331 #define p29_AS_INPUT LPC_GPIO0->FIOMASK &= p29_CLR_MASK;
AjK 8:cb4d323ce6fd 332 #define p29_SET LPC_GPIO0->FIOSET = p29_SET_MASK
AjK 8:cb4d323ce6fd 333 #define p29_CLR LPC_GPIO0->FIOCLR = p29_SET_MASK
AjK 8:cb4d323ce6fd 334 #define p29_IS_SET (bool)(LPC_GPIO0->FIOPIN & p29_SET_MASK)
AjK 8:cb4d323ce6fd 335 #define p29_IS_CLR !(p29_IS_SET)
AjK 8:cb4d323ce6fd 336 #define p29_TOGGLE p29_IS_SET?p29_CLR:p29_SET
AjK 8:cb4d323ce6fd 337 #define p29_MODE(x) LPC_PINCON->PINMODE0&=p29_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<10)
AjK 8:cb4d323ce6fd 338
AjK 8:cb4d323ce6fd 339 /* p30 is P0.4 */
AjK 8:cb4d323ce6fd 340 #define p30_SEL_MASK ~(3UL << 8)
AjK 8:cb4d323ce6fd 341 #define p30_SET_MASK (1UL << 4)
AjK 8:cb4d323ce6fd 342 #define p30_CLR_MASK ~(p30_SET_MASK)
AjK 8:cb4d323ce6fd 343 #define p30_AS_OUTPUT LPC_PINCON->PINSEL0&=p30_SEL_MASK;LPC_GPIO0->FIODIR|=p30_SET_MASK
AjK 8:cb4d323ce6fd 344 #define p30_AS_INPUT LPC_GPIO0->FIOMASK &= p30_CLR_MASK;
AjK 8:cb4d323ce6fd 345 #define p30_SET LPC_GPIO0->FIOSET = p30_SET_MASK
AjK 8:cb4d323ce6fd 346 #define p30_CLR LPC_GPIO0->FIOCLR = p30_SET_MASK
AjK 8:cb4d323ce6fd 347 #define p30_IS_SET (bool)(LPC_GPIO0->FIOPIN & p30_SET_MASK)
AjK 8:cb4d323ce6fd 348 #define p30_IS_CLR !(p30_IS_SET)
AjK 8:cb4d323ce6fd 349 #define p30_MODE(x) LPC_PINCON->PINMODE0&=p30_SEL_MASK;LPC_PINCON->PINMODE0|=((x&0x3)<<8)
AjK 8:cb4d323ce6fd 350
AjK 8:cb4d323ce6fd 351 /* The following definitions are for the four Mbed LEDs.
AjK 8:cb4d323ce6fd 352 LED1 = P1.18
AjK 8:cb4d323ce6fd 353 LED2 = P1.20
AjK 8:cb4d323ce6fd 354 LED3 = P1.21
AjK 8:cb4d323ce6fd 355 LED4 = P1.23 */
AjK 8:cb4d323ce6fd 356
AjK 8:cb4d323ce6fd 357 #define P1_18_SEL_MASK ~(3UL << 4)
AjK 8:cb4d323ce6fd 358 #define P1_18_SET_MASK (1UL << 18)
AjK 8:cb4d323ce6fd 359 #define P1_18_CLR_MASK ~(P1_18_SET_MASK)
AjK 8:cb4d323ce6fd 360 #define P1_18_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_18_SEL_MASK;LPC_GPIO1->FIODIR|=P1_18_SET_MASK
AjK 8:cb4d323ce6fd 361 #define P1_18_AS_INPUT LPC_GPIO1->FIOMASK &= P1_18_CLR_MASK;
AjK 8:cb4d323ce6fd 362 #define P1_18_SET LPC_GPIO1->FIOSET = P1_18_SET_MASK
AjK 8:cb4d323ce6fd 363 #define P1_18_CLR LPC_GPIO1->FIOCLR = P1_18_SET_MASK
AjK 8:cb4d323ce6fd 364 #define P1_18_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_18_SET_MASK)
AjK 8:cb4d323ce6fd 365 #define P1_18_IS_CLR !(P1_18_IS_SET)
AjK 8:cb4d323ce6fd 366 #define LED1_USE P1_18_AS_OUTPUT;P1_18_AS_INPUT
AjK 8:cb4d323ce6fd 367 #define LED1_ON P1_18_SET
AjK 8:cb4d323ce6fd 368 #define LED1_OFF P1_18_CLR
AjK 8:cb4d323ce6fd 369 #define LED1_IS_ON P1_18_IS_SET
AjK 8:cb4d323ce6fd 370 #define LED1_TOGGLE P1_18_IS_SET?LED1_OFF:LED1_ON
AjK 8:cb4d323ce6fd 371
AjK 8:cb4d323ce6fd 372 #define P1_20_SEL_MASK ~(3UL << 8)
AjK 8:cb4d323ce6fd 373 #define P1_20_SET_MASK (1UL << 20)
AjK 8:cb4d323ce6fd 374 #define P1_20_CLR_MASK ~(P1_20_SET_MASK)
AjK 8:cb4d323ce6fd 375 #define P1_20_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_20_SEL_MASK;LPC_GPIO1->FIODIR|=P1_20_SET_MASK
AjK 8:cb4d323ce6fd 376 #define P1_20_AS_INPUT LPC_GPIO1->FIOMASK &= P1_20_CLR_MASK;
AjK 8:cb4d323ce6fd 377 #define P1_20_SET LPC_GPIO1->FIOSET = P1_20_SET_MASK
AjK 8:cb4d323ce6fd 378 #define P1_20_CLR LPC_GPIO1->FIOCLR = P1_20_SET_MASK
AjK 8:cb4d323ce6fd 379 #define P1_20_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_20_SET_MASK)
AjK 8:cb4d323ce6fd 380 #define P1_20_IS_CLR !(P1_20_IS_SET)
AjK 8:cb4d323ce6fd 381 #define LED2_USE P1_20_AS_OUTPUT;P1_20_AS_INPUT
AjK 8:cb4d323ce6fd 382 #define LED2_ON P1_20_SET
AjK 8:cb4d323ce6fd 383 #define LED2_OFF P1_20_CLR
AjK 8:cb4d323ce6fd 384 #define LED2_IS_ON P1_20_IS_SET
AjK 8:cb4d323ce6fd 385 #define LED2_TOGGLE P1_20_IS_SET?LED2_OFF:LED2_ON
AjK 8:cb4d323ce6fd 386
AjK 8:cb4d323ce6fd 387 #define P1_21_SEL_MASK ~(3UL << 10)
AjK 8:cb4d323ce6fd 388 #define P1_21_SET_MASK (1UL << 21)
AjK 8:cb4d323ce6fd 389 #define P1_21_CLR_MASK ~(P1_21_SET_MASK)
AjK 8:cb4d323ce6fd 390 #define P1_21_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_21_SEL_MASK;LPC_GPIO1->FIODIR|=P1_21_SET_MASK
AjK 8:cb4d323ce6fd 391 #define P1_21_AS_INPUT LPC_GPIO1->FIOMASK &= P1_21_CLR_MASK;
AjK 8:cb4d323ce6fd 392 #define P1_21_SET LPC_GPIO1->FIOSET = P1_21_SET_MASK
AjK 8:cb4d323ce6fd 393 #define P1_21_CLR LPC_GPIO1->FIOCLR = P1_21_SET_MASK
AjK 8:cb4d323ce6fd 394 #define P1_21_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_21_SET_MASK)
AjK 8:cb4d323ce6fd 395 #define P1_21_IS_CLR !(P1_21_IS_SET)
AjK 8:cb4d323ce6fd 396 #define LED3_USE P1_21_AS_OUTPUT;P1_21_AS_INPUT
AjK 8:cb4d323ce6fd 397 #define LED3_ON P1_21_SET
AjK 8:cb4d323ce6fd 398 #define LED3_OFF P1_21_CLR
AjK 8:cb4d323ce6fd 399 #define LED3_IS_ON P1_21_IS_SET
AjK 8:cb4d323ce6fd 400 #define LED3_TOGGLE P1_21_IS_SET?LED3_OFF:LED3_ON
AjK 8:cb4d323ce6fd 401
AjK 8:cb4d323ce6fd 402 #define P1_23_SEL_MASK ~(3UL << 14)
AjK 8:cb4d323ce6fd 403 #define P1_23_SET_MASK (1UL << 23)
AjK 8:cb4d323ce6fd 404 #define P1_23_CLR_MASK ~(P1_23_SET_MASK)
AjK 8:cb4d323ce6fd 405 #define P1_23_AS_OUTPUT LPC_PINCON->PINSEL3&=P1_23_SEL_MASK;LPC_GPIO1->FIODIR|=P1_23_SET_MASK
AjK 8:cb4d323ce6fd 406 #define P1_23_AS_INPUT LPC_GPIO1->FIOMASK &= P1_23_CLR_MASK;
AjK 8:cb4d323ce6fd 407 #define P1_23_SET LPC_GPIO1->FIOSET = P1_23_SET_MASK
AjK 8:cb4d323ce6fd 408 #define P1_23_CLR LPC_GPIO1->FIOCLR = P1_23_SET_MASK
AjK 8:cb4d323ce6fd 409 #define P1_23_IS_SET (bool)(LPC_GPIO1->FIOPIN & P1_23_SET_MASK)
AjK 8:cb4d323ce6fd 410 #define P1_23_IS_CLR !(P1_23_IS_SET)
AjK 8:cb4d323ce6fd 411 #define LED4_USE P1_23_AS_OUTPUT;P1_23_AS_INPUT
AjK 8:cb4d323ce6fd 412 #define LED4_ON P1_23_SET
AjK 8:cb4d323ce6fd 413 #define LED4_OFF P1_23_CLR
AjK 8:cb4d323ce6fd 414 #define LED4_IS_ON P1_23_IS_SET
AjK 8:cb4d323ce6fd 415 #define LED4_TOGGLE P1_23_IS_SET?LED4_OFF:LED4_ON
AjK 8:cb4d323ce6fd 416
AjK 8:cb4d323ce6fd 417 #endif
AjK 8:cb4d323ce6fd 418