Zoltan Hudak / Mbed OS Baremetal_EventQue_Bluepill

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TARGET_BLUEPILL/device/stm32f103xb.h@0:2cf53c219693, 2020-05-14 (annotated)

Committer:
hudakz
Date:
Thu May 14 05:27:57 2020 +0000
Revision:
0:2cf53c219693
Bare-metal configuration with EventQueue for a Bluepill board.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hudakz 0:2cf53c219693 1 /**
hudakz 0:2cf53c219693 2 ******************************************************************************
hudakz 0:2cf53c219693 3 * @file stm32f103xb.h
hudakz 0:2cf53c219693 4 * @author MCD Application Team
hudakz 0:2cf53c219693 5 * @version V4.2.0
hudakz 0:2cf53c219693 6 * @date 31-March-2017
hudakz 0:2cf53c219693 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
hudakz 0:2cf53c219693 8 * This file contains all the peripheral register's definitions, bits
hudakz 0:2cf53c219693 9 * definitions and memory mapping for STM32F1xx devices.
hudakz 0:2cf53c219693 10 *
hudakz 0:2cf53c219693 11 * This file contains:
hudakz 0:2cf53c219693 12 * - Data structures and the address mapping for all peripherals
hudakz 0:2cf53c219693 13 * - Peripheral's registers declarations and bits definition
hudakz 0:2cf53c219693 14 * - Macros to access peripheral’s registers hardware
hudakz 0:2cf53c219693 15 *
hudakz 0:2cf53c219693 16 ******************************************************************************
hudakz 0:2cf53c219693 17 * @attention
hudakz 0:2cf53c219693 18 *
hudakz 0:2cf53c219693 19 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
hudakz 0:2cf53c219693 20 *
hudakz 0:2cf53c219693 21 * Redistribution and use in source and binary forms, with or without modification,
hudakz 0:2cf53c219693 22 * are permitted provided that the following conditions are met:
hudakz 0:2cf53c219693 23 * 1. Redistributions of source code must retain the above copyright notice,
hudakz 0:2cf53c219693 24 * this list of conditions and the following disclaimer.
hudakz 0:2cf53c219693 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
hudakz 0:2cf53c219693 26 * this list of conditions and the following disclaimer in the documentation
hudakz 0:2cf53c219693 27 * and/or other materials provided with the distribution.
hudakz 0:2cf53c219693 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
hudakz 0:2cf53c219693 29 * may be used to endorse or promote products derived from this software
hudakz 0:2cf53c219693 30 * without specific prior written permission.
hudakz 0:2cf53c219693 31 *
hudakz 0:2cf53c219693 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
hudakz 0:2cf53c219693 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
hudakz 0:2cf53c219693 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
hudakz 0:2cf53c219693 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
hudakz 0:2cf53c219693 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
hudakz 0:2cf53c219693 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
hudakz 0:2cf53c219693 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
hudakz 0:2cf53c219693 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
hudakz 0:2cf53c219693 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
hudakz 0:2cf53c219693 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
hudakz 0:2cf53c219693 42 *
hudakz 0:2cf53c219693 43 ******************************************************************************
hudakz 0:2cf53c219693 44 */
hudakz 0:2cf53c219693 45
hudakz 0:2cf53c219693 46
hudakz 0:2cf53c219693 47 /** @addtogroup CMSIS
hudakz 0:2cf53c219693 48 * @{
hudakz 0:2cf53c219693 49 */
hudakz 0:2cf53c219693 50
hudakz 0:2cf53c219693 51 /** @addtogroup stm32f103xb
hudakz 0:2cf53c219693 52 * @{
hudakz 0:2cf53c219693 53 */
hudakz 0:2cf53c219693 54
hudakz 0:2cf53c219693 55 #ifndef __STM32F103xB_H
hudakz 0:2cf53c219693 56 #define __STM32F103xB_H
hudakz 0:2cf53c219693 57
hudakz 0:2cf53c219693 58 #ifdef __cplusplus
hudakz 0:2cf53c219693 59 extern "C" {
hudakz 0:2cf53c219693 60 #endif
hudakz 0:2cf53c219693 61
hudakz 0:2cf53c219693 62 /** @addtogroup Configuration_section_for_CMSIS
hudakz 0:2cf53c219693 63 * @{
hudakz 0:2cf53c219693 64 */
hudakz 0:2cf53c219693 65 /**
hudakz 0:2cf53c219693 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
hudakz 0:2cf53c219693 67 */
hudakz 0:2cf53c219693 68 #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
hudakz 0:2cf53c219693 69 #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
hudakz 0:2cf53c219693 70 #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
hudakz 0:2cf53c219693 71 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
hudakz 0:2cf53c219693 72
hudakz 0:2cf53c219693 73 /**
hudakz 0:2cf53c219693 74 * @}
hudakz 0:2cf53c219693 75 */
hudakz 0:2cf53c219693 76
hudakz 0:2cf53c219693 77 /** @addtogroup Peripheral_interrupt_number_definition
hudakz 0:2cf53c219693 78 * @{
hudakz 0:2cf53c219693 79 */
hudakz 0:2cf53c219693 80
hudakz 0:2cf53c219693 81 /**
hudakz 0:2cf53c219693 82 * @brief STM32F10x Interrupt Number Definition, according to the selected device
hudakz 0:2cf53c219693 83 * in @ref Library_configuration_section
hudakz 0:2cf53c219693 84 */
hudakz 0:2cf53c219693 85
hudakz 0:2cf53c219693 86 /*!< Interrupt Number Definition */
hudakz 0:2cf53c219693 87 typedef enum
hudakz 0:2cf53c219693 88 {
hudakz 0:2cf53c219693 89 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
hudakz 0:2cf53c219693 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
hudakz 0:2cf53c219693 91 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
hudakz 0:2cf53c219693 92 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
hudakz 0:2cf53c219693 93 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
hudakz 0:2cf53c219693 94 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
hudakz 0:2cf53c219693 95 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
hudakz 0:2cf53c219693 96 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
hudakz 0:2cf53c219693 97 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
hudakz 0:2cf53c219693 98 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
hudakz 0:2cf53c219693 99
hudakz 0:2cf53c219693 100 /****** STM32 specific Interrupt Numbers *********************************************************/
hudakz 0:2cf53c219693 101 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
hudakz 0:2cf53c219693 102 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
hudakz 0:2cf53c219693 103 TAMPER_IRQn = 2, /*!< Tamper Interrupt */
hudakz 0:2cf53c219693 104 RTC_IRQn = 3, /*!< RTC global Interrupt */
hudakz 0:2cf53c219693 105 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
hudakz 0:2cf53c219693 106 RCC_IRQn = 5, /*!< RCC global Interrupt */
hudakz 0:2cf53c219693 107 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
hudakz 0:2cf53c219693 108 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
hudakz 0:2cf53c219693 109 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
hudakz 0:2cf53c219693 110 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
hudakz 0:2cf53c219693 111 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
hudakz 0:2cf53c219693 112 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
hudakz 0:2cf53c219693 113 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
hudakz 0:2cf53c219693 114 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
hudakz 0:2cf53c219693 115 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
hudakz 0:2cf53c219693 116 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
hudakz 0:2cf53c219693 117 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
hudakz 0:2cf53c219693 118 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
hudakz 0:2cf53c219693 119 ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
hudakz 0:2cf53c219693 120 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
hudakz 0:2cf53c219693 121 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
hudakz 0:2cf53c219693 122 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
hudakz 0:2cf53c219693 123 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
hudakz 0:2cf53c219693 124 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
hudakz 0:2cf53c219693 125 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
hudakz 0:2cf53c219693 126 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
hudakz 0:2cf53c219693 127 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
hudakz 0:2cf53c219693 128 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
hudakz 0:2cf53c219693 129 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
hudakz 0:2cf53c219693 130 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
hudakz 0:2cf53c219693 131 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
hudakz 0:2cf53c219693 132 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
hudakz 0:2cf53c219693 133 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
hudakz 0:2cf53c219693 134 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
hudakz 0:2cf53c219693 135 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
hudakz 0:2cf53c219693 136 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
hudakz 0:2cf53c219693 137 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
hudakz 0:2cf53c219693 138 USART1_IRQn = 37, /*!< USART1 global Interrupt */
hudakz 0:2cf53c219693 139 USART2_IRQn = 38, /*!< USART2 global Interrupt */
hudakz 0:2cf53c219693 140 USART3_IRQn = 39, /*!< USART3 global Interrupt */
hudakz 0:2cf53c219693 141 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
hudakz 0:2cf53c219693 142 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
hudakz 0:2cf53c219693 143 USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
hudakz 0:2cf53c219693 144 } IRQn_Type;
hudakz 0:2cf53c219693 145
hudakz 0:2cf53c219693 146 /**
hudakz 0:2cf53c219693 147 * @}
hudakz 0:2cf53c219693 148 */
hudakz 0:2cf53c219693 149
hudakz 0:2cf53c219693 150 #include "core_cm3.h"
hudakz 0:2cf53c219693 151 #include "system_stm32f1xx.h"
hudakz 0:2cf53c219693 152 #include <stdint.h>
hudakz 0:2cf53c219693 153
hudakz 0:2cf53c219693 154 /** @addtogroup Peripheral_registers_structures
hudakz 0:2cf53c219693 155 * @{
hudakz 0:2cf53c219693 156 */
hudakz 0:2cf53c219693 157
hudakz 0:2cf53c219693 158 /**
hudakz 0:2cf53c219693 159 * @brief Analog to Digital Converter
hudakz 0:2cf53c219693 160 */
hudakz 0:2cf53c219693 161
hudakz 0:2cf53c219693 162 typedef struct
hudakz 0:2cf53c219693 163 {
hudakz 0:2cf53c219693 164 __IO uint32_t SR;
hudakz 0:2cf53c219693 165 __IO uint32_t CR1;
hudakz 0:2cf53c219693 166 __IO uint32_t CR2;
hudakz 0:2cf53c219693 167 __IO uint32_t SMPR1;
hudakz 0:2cf53c219693 168 __IO uint32_t SMPR2;
hudakz 0:2cf53c219693 169 __IO uint32_t JOFR1;
hudakz 0:2cf53c219693 170 __IO uint32_t JOFR2;
hudakz 0:2cf53c219693 171 __IO uint32_t JOFR3;
hudakz 0:2cf53c219693 172 __IO uint32_t JOFR4;
hudakz 0:2cf53c219693 173 __IO uint32_t HTR;
hudakz 0:2cf53c219693 174 __IO uint32_t LTR;
hudakz 0:2cf53c219693 175 __IO uint32_t SQR1;
hudakz 0:2cf53c219693 176 __IO uint32_t SQR2;
hudakz 0:2cf53c219693 177 __IO uint32_t SQR3;
hudakz 0:2cf53c219693 178 __IO uint32_t JSQR;
hudakz 0:2cf53c219693 179 __IO uint32_t JDR1;
hudakz 0:2cf53c219693 180 __IO uint32_t JDR2;
hudakz 0:2cf53c219693 181 __IO uint32_t JDR3;
hudakz 0:2cf53c219693 182 __IO uint32_t JDR4;
hudakz 0:2cf53c219693 183 __IO uint32_t DR;
hudakz 0:2cf53c219693 184 } ADC_TypeDef;
hudakz 0:2cf53c219693 185
hudakz 0:2cf53c219693 186 typedef struct
hudakz 0:2cf53c219693 187 {
hudakz 0:2cf53c219693 188 __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
hudakz 0:2cf53c219693 189 __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
hudakz 0:2cf53c219693 190 __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
hudakz 0:2cf53c219693 191 uint32_t RESERVED[16];
hudakz 0:2cf53c219693 192 __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
hudakz 0:2cf53c219693 193 } ADC_Common_TypeDef;
hudakz 0:2cf53c219693 194
hudakz 0:2cf53c219693 195 /**
hudakz 0:2cf53c219693 196 * @brief Backup Registers
hudakz 0:2cf53c219693 197 */
hudakz 0:2cf53c219693 198
hudakz 0:2cf53c219693 199 typedef struct
hudakz 0:2cf53c219693 200 {
hudakz 0:2cf53c219693 201 uint32_t RESERVED0;
hudakz 0:2cf53c219693 202 __IO uint32_t DR1;
hudakz 0:2cf53c219693 203 __IO uint32_t DR2;
hudakz 0:2cf53c219693 204 __IO uint32_t DR3;
hudakz 0:2cf53c219693 205 __IO uint32_t DR4;
hudakz 0:2cf53c219693 206 __IO uint32_t DR5;
hudakz 0:2cf53c219693 207 __IO uint32_t DR6;
hudakz 0:2cf53c219693 208 __IO uint32_t DR7;
hudakz 0:2cf53c219693 209 __IO uint32_t DR8;
hudakz 0:2cf53c219693 210 __IO uint32_t DR9;
hudakz 0:2cf53c219693 211 __IO uint32_t DR10;
hudakz 0:2cf53c219693 212 __IO uint32_t RTCCR;
hudakz 0:2cf53c219693 213 __IO uint32_t CR;
hudakz 0:2cf53c219693 214 __IO uint32_t CSR;
hudakz 0:2cf53c219693 215 } BKP_TypeDef;
hudakz 0:2cf53c219693 216
hudakz 0:2cf53c219693 217 /**
hudakz 0:2cf53c219693 218 * @brief Controller Area Network TxMailBox
hudakz 0:2cf53c219693 219 */
hudakz 0:2cf53c219693 220
hudakz 0:2cf53c219693 221 typedef struct
hudakz 0:2cf53c219693 222 {
hudakz 0:2cf53c219693 223 __IO uint32_t TIR;
hudakz 0:2cf53c219693 224 __IO uint32_t TDTR;
hudakz 0:2cf53c219693 225 __IO uint32_t TDLR;
hudakz 0:2cf53c219693 226 __IO uint32_t TDHR;
hudakz 0:2cf53c219693 227 } CAN_TxMailBox_TypeDef;
hudakz 0:2cf53c219693 228
hudakz 0:2cf53c219693 229 /**
hudakz 0:2cf53c219693 230 * @brief Controller Area Network FIFOMailBox
hudakz 0:2cf53c219693 231 */
hudakz 0:2cf53c219693 232
hudakz 0:2cf53c219693 233 typedef struct
hudakz 0:2cf53c219693 234 {
hudakz 0:2cf53c219693 235 __IO uint32_t RIR;
hudakz 0:2cf53c219693 236 __IO uint32_t RDTR;
hudakz 0:2cf53c219693 237 __IO uint32_t RDLR;
hudakz 0:2cf53c219693 238 __IO uint32_t RDHR;
hudakz 0:2cf53c219693 239 } CAN_FIFOMailBox_TypeDef;
hudakz 0:2cf53c219693 240
hudakz 0:2cf53c219693 241 /**
hudakz 0:2cf53c219693 242 * @brief Controller Area Network FilterRegister
hudakz 0:2cf53c219693 243 */
hudakz 0:2cf53c219693 244
hudakz 0:2cf53c219693 245 typedef struct
hudakz 0:2cf53c219693 246 {
hudakz 0:2cf53c219693 247 __IO uint32_t FR1;
hudakz 0:2cf53c219693 248 __IO uint32_t FR2;
hudakz 0:2cf53c219693 249 } CAN_FilterRegister_TypeDef;
hudakz 0:2cf53c219693 250
hudakz 0:2cf53c219693 251 /**
hudakz 0:2cf53c219693 252 * @brief Controller Area Network
hudakz 0:2cf53c219693 253 */
hudakz 0:2cf53c219693 254
hudakz 0:2cf53c219693 255 typedef struct
hudakz 0:2cf53c219693 256 {
hudakz 0:2cf53c219693 257 __IO uint32_t MCR;
hudakz 0:2cf53c219693 258 __IO uint32_t MSR;
hudakz 0:2cf53c219693 259 __IO uint32_t TSR;
hudakz 0:2cf53c219693 260 __IO uint32_t RF0R;
hudakz 0:2cf53c219693 261 __IO uint32_t RF1R;
hudakz 0:2cf53c219693 262 __IO uint32_t IER;
hudakz 0:2cf53c219693 263 __IO uint32_t ESR;
hudakz 0:2cf53c219693 264 __IO uint32_t BTR;
hudakz 0:2cf53c219693 265 uint32_t RESERVED0[88];
hudakz 0:2cf53c219693 266 CAN_TxMailBox_TypeDef sTxMailBox[3];
hudakz 0:2cf53c219693 267 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
hudakz 0:2cf53c219693 268 uint32_t RESERVED1[12];
hudakz 0:2cf53c219693 269 __IO uint32_t FMR;
hudakz 0:2cf53c219693 270 __IO uint32_t FM1R;
hudakz 0:2cf53c219693 271 uint32_t RESERVED2;
hudakz 0:2cf53c219693 272 __IO uint32_t FS1R;
hudakz 0:2cf53c219693 273 uint32_t RESERVED3;
hudakz 0:2cf53c219693 274 __IO uint32_t FFA1R;
hudakz 0:2cf53c219693 275 uint32_t RESERVED4;
hudakz 0:2cf53c219693 276 __IO uint32_t FA1R;
hudakz 0:2cf53c219693 277 uint32_t RESERVED5[8];
hudakz 0:2cf53c219693 278 CAN_FilterRegister_TypeDef sFilterRegister[14];
hudakz 0:2cf53c219693 279 } CAN_TypeDef;
hudakz 0:2cf53c219693 280
hudakz 0:2cf53c219693 281 /**
hudakz 0:2cf53c219693 282 * @brief CRC calculation unit
hudakz 0:2cf53c219693 283 */
hudakz 0:2cf53c219693 284
hudakz 0:2cf53c219693 285 typedef struct
hudakz 0:2cf53c219693 286 {
hudakz 0:2cf53c219693 287 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
hudakz 0:2cf53c219693 288 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
hudakz 0:2cf53c219693 289 uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
hudakz 0:2cf53c219693 290 uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
hudakz 0:2cf53c219693 291 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
hudakz 0:2cf53c219693 292 } CRC_TypeDef;
hudakz 0:2cf53c219693 293
hudakz 0:2cf53c219693 294
hudakz 0:2cf53c219693 295 /**
hudakz 0:2cf53c219693 296 * @brief Debug MCU
hudakz 0:2cf53c219693 297 */
hudakz 0:2cf53c219693 298
hudakz 0:2cf53c219693 299 typedef struct
hudakz 0:2cf53c219693 300 {
hudakz 0:2cf53c219693 301 __IO uint32_t IDCODE;
hudakz 0:2cf53c219693 302 __IO uint32_t CR;
hudakz 0:2cf53c219693 303 }DBGMCU_TypeDef;
hudakz 0:2cf53c219693 304
hudakz 0:2cf53c219693 305 /**
hudakz 0:2cf53c219693 306 * @brief DMA Controller
hudakz 0:2cf53c219693 307 */
hudakz 0:2cf53c219693 308
hudakz 0:2cf53c219693 309 typedef struct
hudakz 0:2cf53c219693 310 {
hudakz 0:2cf53c219693 311 __IO uint32_t CCR;
hudakz 0:2cf53c219693 312 __IO uint32_t CNDTR;
hudakz 0:2cf53c219693 313 __IO uint32_t CPAR;
hudakz 0:2cf53c219693 314 __IO uint32_t CMAR;
hudakz 0:2cf53c219693 315 } DMA_Channel_TypeDef;
hudakz 0:2cf53c219693 316
hudakz 0:2cf53c219693 317 typedef struct
hudakz 0:2cf53c219693 318 {
hudakz 0:2cf53c219693 319 __IO uint32_t ISR;
hudakz 0:2cf53c219693 320 __IO uint32_t IFCR;
hudakz 0:2cf53c219693 321 } DMA_TypeDef;
hudakz 0:2cf53c219693 322
hudakz 0:2cf53c219693 323
hudakz 0:2cf53c219693 324
hudakz 0:2cf53c219693 325 /**
hudakz 0:2cf53c219693 326 * @brief External Interrupt/Event Controller
hudakz 0:2cf53c219693 327 */
hudakz 0:2cf53c219693 328
hudakz 0:2cf53c219693 329 typedef struct
hudakz 0:2cf53c219693 330 {
hudakz 0:2cf53c219693 331 __IO uint32_t IMR;
hudakz 0:2cf53c219693 332 __IO uint32_t EMR;
hudakz 0:2cf53c219693 333 __IO uint32_t RTSR;
hudakz 0:2cf53c219693 334 __IO uint32_t FTSR;
hudakz 0:2cf53c219693 335 __IO uint32_t SWIER;
hudakz 0:2cf53c219693 336 __IO uint32_t PR;
hudakz 0:2cf53c219693 337 } EXTI_TypeDef;
hudakz 0:2cf53c219693 338
hudakz 0:2cf53c219693 339 /**
hudakz 0:2cf53c219693 340 * @brief FLASH Registers
hudakz 0:2cf53c219693 341 */
hudakz 0:2cf53c219693 342
hudakz 0:2cf53c219693 343 typedef struct
hudakz 0:2cf53c219693 344 {
hudakz 0:2cf53c219693 345 __IO uint32_t ACR;
hudakz 0:2cf53c219693 346 __IO uint32_t KEYR;
hudakz 0:2cf53c219693 347 __IO uint32_t OPTKEYR;
hudakz 0:2cf53c219693 348 __IO uint32_t SR;
hudakz 0:2cf53c219693 349 __IO uint32_t CR;
hudakz 0:2cf53c219693 350 __IO uint32_t AR;
hudakz 0:2cf53c219693 351 __IO uint32_t RESERVED;
hudakz 0:2cf53c219693 352 __IO uint32_t OBR;
hudakz 0:2cf53c219693 353 __IO uint32_t WRPR;
hudakz 0:2cf53c219693 354 } FLASH_TypeDef;
hudakz 0:2cf53c219693 355
hudakz 0:2cf53c219693 356 /**
hudakz 0:2cf53c219693 357 * @brief Option Bytes Registers
hudakz 0:2cf53c219693 358 */
hudakz 0:2cf53c219693 359
hudakz 0:2cf53c219693 360 typedef struct
hudakz 0:2cf53c219693 361 {
hudakz 0:2cf53c219693 362 __IO uint16_t RDP;
hudakz 0:2cf53c219693 363 __IO uint16_t USER;
hudakz 0:2cf53c219693 364 __IO uint16_t Data0;
hudakz 0:2cf53c219693 365 __IO uint16_t Data1;
hudakz 0:2cf53c219693 366 __IO uint16_t WRP0;
hudakz 0:2cf53c219693 367 __IO uint16_t WRP1;
hudakz 0:2cf53c219693 368 __IO uint16_t WRP2;
hudakz 0:2cf53c219693 369 __IO uint16_t WRP3;
hudakz 0:2cf53c219693 370 } OB_TypeDef;
hudakz 0:2cf53c219693 371
hudakz 0:2cf53c219693 372 /**
hudakz 0:2cf53c219693 373 * @brief General Purpose I/O
hudakz 0:2cf53c219693 374 */
hudakz 0:2cf53c219693 375
hudakz 0:2cf53c219693 376 typedef struct
hudakz 0:2cf53c219693 377 {
hudakz 0:2cf53c219693 378 __IO uint32_t CRL;
hudakz 0:2cf53c219693 379 __IO uint32_t CRH;
hudakz 0:2cf53c219693 380 __IO uint32_t IDR;
hudakz 0:2cf53c219693 381 __IO uint32_t ODR;
hudakz 0:2cf53c219693 382 __IO uint32_t BSRR;
hudakz 0:2cf53c219693 383 __IO uint32_t BRR;
hudakz 0:2cf53c219693 384 __IO uint32_t LCKR;
hudakz 0:2cf53c219693 385 } GPIO_TypeDef;
hudakz 0:2cf53c219693 386
hudakz 0:2cf53c219693 387 /**
hudakz 0:2cf53c219693 388 * @brief Alternate Function I/O
hudakz 0:2cf53c219693 389 */
hudakz 0:2cf53c219693 390
hudakz 0:2cf53c219693 391 typedef struct
hudakz 0:2cf53c219693 392 {
hudakz 0:2cf53c219693 393 __IO uint32_t EVCR;
hudakz 0:2cf53c219693 394 __IO uint32_t MAPR;
hudakz 0:2cf53c219693 395 __IO uint32_t EXTICR[4];
hudakz 0:2cf53c219693 396 uint32_t RESERVED0;
hudakz 0:2cf53c219693 397 __IO uint32_t MAPR2;
hudakz 0:2cf53c219693 398 } AFIO_TypeDef;
hudakz 0:2cf53c219693 399 /**
hudakz 0:2cf53c219693 400 * @brief Inter Integrated Circuit Interface
hudakz 0:2cf53c219693 401 */
hudakz 0:2cf53c219693 402
hudakz 0:2cf53c219693 403 typedef struct
hudakz 0:2cf53c219693 404 {
hudakz 0:2cf53c219693 405 __IO uint32_t CR1;
hudakz 0:2cf53c219693 406 __IO uint32_t CR2;
hudakz 0:2cf53c219693 407 __IO uint32_t OAR1;
hudakz 0:2cf53c219693 408 __IO uint32_t OAR2;
hudakz 0:2cf53c219693 409 __IO uint32_t DR;
hudakz 0:2cf53c219693 410 __IO uint32_t SR1;
hudakz 0:2cf53c219693 411 __IO uint32_t SR2;
hudakz 0:2cf53c219693 412 __IO uint32_t CCR;
hudakz 0:2cf53c219693 413 __IO uint32_t TRISE;
hudakz 0:2cf53c219693 414 } I2C_TypeDef;
hudakz 0:2cf53c219693 415
hudakz 0:2cf53c219693 416 /**
hudakz 0:2cf53c219693 417 * @brief Independent WATCHDOG
hudakz 0:2cf53c219693 418 */
hudakz 0:2cf53c219693 419
hudakz 0:2cf53c219693 420 typedef struct
hudakz 0:2cf53c219693 421 {
hudakz 0:2cf53c219693 422 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
hudakz 0:2cf53c219693 423 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
hudakz 0:2cf53c219693 424 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
hudakz 0:2cf53c219693 425 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
hudakz 0:2cf53c219693 426 } IWDG_TypeDef;
hudakz 0:2cf53c219693 427
hudakz 0:2cf53c219693 428 /**
hudakz 0:2cf53c219693 429 * @brief Power Control
hudakz 0:2cf53c219693 430 */
hudakz 0:2cf53c219693 431
hudakz 0:2cf53c219693 432 typedef struct
hudakz 0:2cf53c219693 433 {
hudakz 0:2cf53c219693 434 __IO uint32_t CR;
hudakz 0:2cf53c219693 435 __IO uint32_t CSR;
hudakz 0:2cf53c219693 436 } PWR_TypeDef;
hudakz 0:2cf53c219693 437
hudakz 0:2cf53c219693 438 /**
hudakz 0:2cf53c219693 439 * @brief Reset and Clock Control
hudakz 0:2cf53c219693 440 */
hudakz 0:2cf53c219693 441
hudakz 0:2cf53c219693 442 typedef struct
hudakz 0:2cf53c219693 443 {
hudakz 0:2cf53c219693 444 __IO uint32_t CR;
hudakz 0:2cf53c219693 445 __IO uint32_t CFGR;
hudakz 0:2cf53c219693 446 __IO uint32_t CIR;
hudakz 0:2cf53c219693 447 __IO uint32_t APB2RSTR;
hudakz 0:2cf53c219693 448 __IO uint32_t APB1RSTR;
hudakz 0:2cf53c219693 449 __IO uint32_t AHBENR;
hudakz 0:2cf53c219693 450 __IO uint32_t APB2ENR;
hudakz 0:2cf53c219693 451 __IO uint32_t APB1ENR;
hudakz 0:2cf53c219693 452 __IO uint32_t BDCR;
hudakz 0:2cf53c219693 453 __IO uint32_t CSR;
hudakz 0:2cf53c219693 454
hudakz 0:2cf53c219693 455
hudakz 0:2cf53c219693 456 } RCC_TypeDef;
hudakz 0:2cf53c219693 457
hudakz 0:2cf53c219693 458 /**
hudakz 0:2cf53c219693 459 * @brief Real-Time Clock
hudakz 0:2cf53c219693 460 */
hudakz 0:2cf53c219693 461
hudakz 0:2cf53c219693 462 typedef struct
hudakz 0:2cf53c219693 463 {
hudakz 0:2cf53c219693 464 __IO uint32_t CRH;
hudakz 0:2cf53c219693 465 __IO uint32_t CRL;
hudakz 0:2cf53c219693 466 __IO uint32_t PRLH;
hudakz 0:2cf53c219693 467 __IO uint32_t PRLL;
hudakz 0:2cf53c219693 468 __IO uint32_t DIVH;
hudakz 0:2cf53c219693 469 __IO uint32_t DIVL;
hudakz 0:2cf53c219693 470 __IO uint32_t CNTH;
hudakz 0:2cf53c219693 471 __IO uint32_t CNTL;
hudakz 0:2cf53c219693 472 __IO uint32_t ALRH;
hudakz 0:2cf53c219693 473 __IO uint32_t ALRL;
hudakz 0:2cf53c219693 474 } RTC_TypeDef;
hudakz 0:2cf53c219693 475
hudakz 0:2cf53c219693 476 /**
hudakz 0:2cf53c219693 477 * @brief SD host Interface
hudakz 0:2cf53c219693 478 */
hudakz 0:2cf53c219693 479
hudakz 0:2cf53c219693 480 typedef struct
hudakz 0:2cf53c219693 481 {
hudakz 0:2cf53c219693 482 __IO uint32_t POWER;
hudakz 0:2cf53c219693 483 __IO uint32_t CLKCR;
hudakz 0:2cf53c219693 484 __IO uint32_t ARG;
hudakz 0:2cf53c219693 485 __IO uint32_t CMD;
hudakz 0:2cf53c219693 486 __I uint32_t RESPCMD;
hudakz 0:2cf53c219693 487 __I uint32_t RESP1;
hudakz 0:2cf53c219693 488 __I uint32_t RESP2;
hudakz 0:2cf53c219693 489 __I uint32_t RESP3;
hudakz 0:2cf53c219693 490 __I uint32_t RESP4;
hudakz 0:2cf53c219693 491 __IO uint32_t DTIMER;
hudakz 0:2cf53c219693 492 __IO uint32_t DLEN;
hudakz 0:2cf53c219693 493 __IO uint32_t DCTRL;
hudakz 0:2cf53c219693 494 __I uint32_t DCOUNT;
hudakz 0:2cf53c219693 495 __I uint32_t STA;
hudakz 0:2cf53c219693 496 __IO uint32_t ICR;
hudakz 0:2cf53c219693 497 __IO uint32_t MASK;
hudakz 0:2cf53c219693 498 uint32_t RESERVED0[2];
hudakz 0:2cf53c219693 499 __I uint32_t FIFOCNT;
hudakz 0:2cf53c219693 500 uint32_t RESERVED1[13];
hudakz 0:2cf53c219693 501 __IO uint32_t FIFO;
hudakz 0:2cf53c219693 502 } SDIO_TypeDef;
hudakz 0:2cf53c219693 503
hudakz 0:2cf53c219693 504 /**
hudakz 0:2cf53c219693 505 * @brief Serial Peripheral Interface
hudakz 0:2cf53c219693 506 */
hudakz 0:2cf53c219693 507
hudakz 0:2cf53c219693 508 typedef struct
hudakz 0:2cf53c219693 509 {
hudakz 0:2cf53c219693 510 __IO uint32_t CR1;
hudakz 0:2cf53c219693 511 __IO uint32_t CR2;
hudakz 0:2cf53c219693 512 __IO uint32_t SR;
hudakz 0:2cf53c219693 513 __IO uint32_t DR;
hudakz 0:2cf53c219693 514 __IO uint32_t CRCPR;
hudakz 0:2cf53c219693 515 __IO uint32_t RXCRCR;
hudakz 0:2cf53c219693 516 __IO uint32_t TXCRCR;
hudakz 0:2cf53c219693 517 __IO uint32_t I2SCFGR;
hudakz 0:2cf53c219693 518 } SPI_TypeDef;
hudakz 0:2cf53c219693 519
hudakz 0:2cf53c219693 520 /**
hudakz 0:2cf53c219693 521 * @brief TIM Timers
hudakz 0:2cf53c219693 522 */
hudakz 0:2cf53c219693 523 typedef struct
hudakz 0:2cf53c219693 524 {
hudakz 0:2cf53c219693 525 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
hudakz 0:2cf53c219693 526 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
hudakz 0:2cf53c219693 527 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
hudakz 0:2cf53c219693 528 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
hudakz 0:2cf53c219693 529 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
hudakz 0:2cf53c219693 530 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
hudakz 0:2cf53c219693 531 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
hudakz 0:2cf53c219693 532 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
hudakz 0:2cf53c219693 533 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
hudakz 0:2cf53c219693 534 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
hudakz 0:2cf53c219693 535 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
hudakz 0:2cf53c219693 536 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
hudakz 0:2cf53c219693 537 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
hudakz 0:2cf53c219693 538 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
hudakz 0:2cf53c219693 539 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
hudakz 0:2cf53c219693 540 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
hudakz 0:2cf53c219693 541 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
hudakz 0:2cf53c219693 542 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
hudakz 0:2cf53c219693 543 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
hudakz 0:2cf53c219693 544 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
hudakz 0:2cf53c219693 545 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
hudakz 0:2cf53c219693 546 }TIM_TypeDef;
hudakz 0:2cf53c219693 547
hudakz 0:2cf53c219693 548
hudakz 0:2cf53c219693 549 /**
hudakz 0:2cf53c219693 550 * @brief Universal Synchronous Asynchronous Receiver Transmitter
hudakz 0:2cf53c219693 551 */
hudakz 0:2cf53c219693 552
hudakz 0:2cf53c219693 553 typedef struct
hudakz 0:2cf53c219693 554 {
hudakz 0:2cf53c219693 555 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
hudakz 0:2cf53c219693 556 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
hudakz 0:2cf53c219693 557 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
hudakz 0:2cf53c219693 558 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
hudakz 0:2cf53c219693 559 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
hudakz 0:2cf53c219693 560 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
hudakz 0:2cf53c219693 561 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
hudakz 0:2cf53c219693 562 } USART_TypeDef;
hudakz 0:2cf53c219693 563
hudakz 0:2cf53c219693 564 /**
hudakz 0:2cf53c219693 565 * @brief Universal Serial Bus Full Speed Device
hudakz 0:2cf53c219693 566 */
hudakz 0:2cf53c219693 567
hudakz 0:2cf53c219693 568 typedef struct
hudakz 0:2cf53c219693 569 {
hudakz 0:2cf53c219693 570 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
hudakz 0:2cf53c219693 571 __IO uint16_t RESERVED0; /*!< Reserved */
hudakz 0:2cf53c219693 572 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
hudakz 0:2cf53c219693 573 __IO uint16_t RESERVED1; /*!< Reserved */
hudakz 0:2cf53c219693 574 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
hudakz 0:2cf53c219693 575 __IO uint16_t RESERVED2; /*!< Reserved */
hudakz 0:2cf53c219693 576 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
hudakz 0:2cf53c219693 577 __IO uint16_t RESERVED3; /*!< Reserved */
hudakz 0:2cf53c219693 578 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
hudakz 0:2cf53c219693 579 __IO uint16_t RESERVED4; /*!< Reserved */
hudakz 0:2cf53c219693 580 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
hudakz 0:2cf53c219693 581 __IO uint16_t RESERVED5; /*!< Reserved */
hudakz 0:2cf53c219693 582 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
hudakz 0:2cf53c219693 583 __IO uint16_t RESERVED6; /*!< Reserved */
hudakz 0:2cf53c219693 584 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
hudakz 0:2cf53c219693 585 __IO uint16_t RESERVED7[17]; /*!< Reserved */
hudakz 0:2cf53c219693 586 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
hudakz 0:2cf53c219693 587 __IO uint16_t RESERVED8; /*!< Reserved */
hudakz 0:2cf53c219693 588 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
hudakz 0:2cf53c219693 589 __IO uint16_t RESERVED9; /*!< Reserved */
hudakz 0:2cf53c219693 590 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
hudakz 0:2cf53c219693 591 __IO uint16_t RESERVEDA; /*!< Reserved */
hudakz 0:2cf53c219693 592 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
hudakz 0:2cf53c219693 593 __IO uint16_t RESERVEDB; /*!< Reserved */
hudakz 0:2cf53c219693 594 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
hudakz 0:2cf53c219693 595 __IO uint16_t RESERVEDC; /*!< Reserved */
hudakz 0:2cf53c219693 596 } USB_TypeDef;
hudakz 0:2cf53c219693 597
hudakz 0:2cf53c219693 598
hudakz 0:2cf53c219693 599 /**
hudakz 0:2cf53c219693 600 * @brief Window WATCHDOG
hudakz 0:2cf53c219693 601 */
hudakz 0:2cf53c219693 602
hudakz 0:2cf53c219693 603 typedef struct
hudakz 0:2cf53c219693 604 {
hudakz 0:2cf53c219693 605 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
hudakz 0:2cf53c219693 606 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
hudakz 0:2cf53c219693 607 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
hudakz 0:2cf53c219693 608 } WWDG_TypeDef;
hudakz 0:2cf53c219693 609
hudakz 0:2cf53c219693 610 /**
hudakz 0:2cf53c219693 611 * @}
hudakz 0:2cf53c219693 612 */
hudakz 0:2cf53c219693 613
hudakz 0:2cf53c219693 614 /** @addtogroup Peripheral_memory_map
hudakz 0:2cf53c219693 615 * @{
hudakz 0:2cf53c219693 616 */
hudakz 0:2cf53c219693 617
hudakz 0:2cf53c219693 618
hudakz 0:2cf53c219693 619 #define FLASH_BASE 0x08000000U /*!< FLASH base address in the alias region */
hudakz 0:2cf53c219693 620 #define FLASH_BANK1_END 0x0801FFFFU /*!< FLASH END address of bank1 */
hudakz 0:2cf53c219693 621 #define SRAM_BASE 0x20000000U /*!< SRAM base address in the alias region */
hudakz 0:2cf53c219693 622 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
hudakz 0:2cf53c219693 623
hudakz 0:2cf53c219693 624 #define SRAM_BB_BASE 0x22000000U /*!< SRAM base address in the bit-band region */
hudakz 0:2cf53c219693 625 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
hudakz 0:2cf53c219693 626
hudakz 0:2cf53c219693 627
hudakz 0:2cf53c219693 628 /*!< Peripheral memory map */
hudakz 0:2cf53c219693 629 #define APB1PERIPH_BASE PERIPH_BASE
hudakz 0:2cf53c219693 630 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
hudakz 0:2cf53c219693 631 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U)
hudakz 0:2cf53c219693 632
hudakz 0:2cf53c219693 633 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000U)
hudakz 0:2cf53c219693 634 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400U)
hudakz 0:2cf53c219693 635 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800U)
hudakz 0:2cf53c219693 636 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800U)
hudakz 0:2cf53c219693 637 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00U)
hudakz 0:2cf53c219693 638 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000U)
hudakz 0:2cf53c219693 639 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800U)
hudakz 0:2cf53c219693 640 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400U)
hudakz 0:2cf53c219693 641 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800U)
hudakz 0:2cf53c219693 642 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400U)
hudakz 0:2cf53c219693 643 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
hudakz 0:2cf53c219693 644 #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400U)
hudakz 0:2cf53c219693 645 #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00U)
hudakz 0:2cf53c219693 646 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000U)
hudakz 0:2cf53c219693 647 #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000U)
hudakz 0:2cf53c219693 648 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400U)
hudakz 0:2cf53c219693 649 #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800U)
hudakz 0:2cf53c219693 650 #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00U)
hudakz 0:2cf53c219693 651 #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000U)
hudakz 0:2cf53c219693 652 #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400U)
hudakz 0:2cf53c219693 653 #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800U)
hudakz 0:2cf53c219693 654 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400U)
hudakz 0:2cf53c219693 655 #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800U)
hudakz 0:2cf53c219693 656 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00U)
hudakz 0:2cf53c219693 657 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000U)
hudakz 0:2cf53c219693 658 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800U)
hudakz 0:2cf53c219693 659
hudakz 0:2cf53c219693 660 #define SDIO_BASE (PERIPH_BASE + 0x00018000U)
hudakz 0:2cf53c219693 661
hudakz 0:2cf53c219693 662 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U)
hudakz 0:2cf53c219693 663 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008U)
hudakz 0:2cf53c219693 664 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CU)
hudakz 0:2cf53c219693 665 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030U)
hudakz 0:2cf53c219693 666 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044U)
hudakz 0:2cf53c219693 667 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058U)
hudakz 0:2cf53c219693 668 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CU)
hudakz 0:2cf53c219693 669 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080U)
hudakz 0:2cf53c219693 670 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U)
hudakz 0:2cf53c219693 671 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U)
hudakz 0:2cf53c219693 672
hudakz 0:2cf53c219693 673 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< Flash registers base address */
hudakz 0:2cf53c219693 674 #define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
hudakz 0:2cf53c219693 675 #define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
hudakz 0:2cf53c219693 676 #define OB_BASE 0x1FFFF800U /*!< Flash Option Bytes base address */
hudakz 0:2cf53c219693 677
hudakz 0:2cf53c219693 678
hudakz 0:2cf53c219693 679
hudakz 0:2cf53c219693 680 #define DBGMCU_BASE 0xE0042000U /*!< Debug MCU registers base address */
hudakz 0:2cf53c219693 681
hudakz 0:2cf53c219693 682 /* USB device FS */
hudakz 0:2cf53c219693 683 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
hudakz 0:2cf53c219693 684 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
hudakz 0:2cf53c219693 685
hudakz 0:2cf53c219693 686
hudakz 0:2cf53c219693 687 /**
hudakz 0:2cf53c219693 688 * @}
hudakz 0:2cf53c219693 689 */
hudakz 0:2cf53c219693 690
hudakz 0:2cf53c219693 691 /** @addtogroup Peripheral_declaration
hudakz 0:2cf53c219693 692 * @{
hudakz 0:2cf53c219693 693 */
hudakz 0:2cf53c219693 694
hudakz 0:2cf53c219693 695 #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
hudakz 0:2cf53c219693 696 #define TIM3 ((TIM_TypeDef *)TIM3_BASE)
hudakz 0:2cf53c219693 697 #define TIM4 ((TIM_TypeDef *)TIM4_BASE)
hudakz 0:2cf53c219693 698 #define RTC ((RTC_TypeDef *)RTC_BASE)
hudakz 0:2cf53c219693 699 #define WWDG ((WWDG_TypeDef *)WWDG_BASE)
hudakz 0:2cf53c219693 700 #define IWDG ((IWDG_TypeDef *)IWDG_BASE)
hudakz 0:2cf53c219693 701 #define SPI2 ((SPI_TypeDef *)SPI2_BASE)
hudakz 0:2cf53c219693 702 #define USART2 ((USART_TypeDef *)USART2_BASE)
hudakz 0:2cf53c219693 703 #define USART3 ((USART_TypeDef *)USART3_BASE)
hudakz 0:2cf53c219693 704 #define I2C1 ((I2C_TypeDef *)I2C1_BASE)
hudakz 0:2cf53c219693 705 #define I2C2 ((I2C_TypeDef *)I2C2_BASE)
hudakz 0:2cf53c219693 706 #define USB ((USB_TypeDef *)USB_BASE)
hudakz 0:2cf53c219693 707 #define CAN1 ((CAN_TypeDef *)CAN1_BASE)
hudakz 0:2cf53c219693 708 #define BKP ((BKP_TypeDef *)BKP_BASE)
hudakz 0:2cf53c219693 709 #define PWR ((PWR_TypeDef *)PWR_BASE)
hudakz 0:2cf53c219693 710 #define AFIO ((AFIO_TypeDef *)AFIO_BASE)
hudakz 0:2cf53c219693 711 #define EXTI ((EXTI_TypeDef *)EXTI_BASE)
hudakz 0:2cf53c219693 712 #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
hudakz 0:2cf53c219693 713 #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
hudakz 0:2cf53c219693 714 #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
hudakz 0:2cf53c219693 715 #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
hudakz 0:2cf53c219693 716 #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
hudakz 0:2cf53c219693 717 #define ADC1 ((ADC_TypeDef *)ADC1_BASE)
hudakz 0:2cf53c219693 718 #define ADC2 ((ADC_TypeDef *)ADC2_BASE)
hudakz 0:2cf53c219693 719 #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
hudakz 0:2cf53c219693 720 #define TIM1 ((TIM_TypeDef *)TIM1_BASE)
hudakz 0:2cf53c219693 721 #define SPI1 ((SPI_TypeDef *)SPI1_BASE)
hudakz 0:2cf53c219693 722 #define USART1 ((USART_TypeDef *)USART1_BASE)
hudakz 0:2cf53c219693 723 #define SDIO ((SDIO_TypeDef *)SDIO_BASE)
hudakz 0:2cf53c219693 724 #define DMA1 ((DMA_TypeDef *)DMA1_BASE)
hudakz 0:2cf53c219693 725 #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
hudakz 0:2cf53c219693 726 #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
hudakz 0:2cf53c219693 727 #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
hudakz 0:2cf53c219693 728 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
hudakz 0:2cf53c219693 729 #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
hudakz 0:2cf53c219693 730 #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
hudakz 0:2cf53c219693 731 #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
hudakz 0:2cf53c219693 732 #define RCC ((RCC_TypeDef *)RCC_BASE)
hudakz 0:2cf53c219693 733 #define CRC ((CRC_TypeDef *)CRC_BASE)
hudakz 0:2cf53c219693 734 #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
hudakz 0:2cf53c219693 735 #define OB ((OB_TypeDef *)OB_BASE)
hudakz 0:2cf53c219693 736 #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
hudakz 0:2cf53c219693 737
hudakz 0:2cf53c219693 738
hudakz 0:2cf53c219693 739 /**
hudakz 0:2cf53c219693 740 * @}
hudakz 0:2cf53c219693 741 */
hudakz 0:2cf53c219693 742
hudakz 0:2cf53c219693 743 /** @addtogroup Exported_constants
hudakz 0:2cf53c219693 744 * @{
hudakz 0:2cf53c219693 745 */
hudakz 0:2cf53c219693 746
hudakz 0:2cf53c219693 747 /** @addtogroup Peripheral_Registers_Bits_Definition
hudakz 0:2cf53c219693 748 * @{
hudakz 0:2cf53c219693 749 */
hudakz 0:2cf53c219693 750
hudakz 0:2cf53c219693 751 /******************************************************************************/
hudakz 0:2cf53c219693 752 /* Peripheral Registers_Bits_Definition */
hudakz 0:2cf53c219693 753 /******************************************************************************/
hudakz 0:2cf53c219693 754
hudakz 0:2cf53c219693 755 /******************************************************************************/
hudakz 0:2cf53c219693 756 /* */
hudakz 0:2cf53c219693 757 /* CRC calculation unit (CRC) */
hudakz 0:2cf53c219693 758 /* */
hudakz 0:2cf53c219693 759 /******************************************************************************/
hudakz 0:2cf53c219693 760
hudakz 0:2cf53c219693 761 /******************* Bit definition for CRC_DR register *********************/
hudakz 0:2cf53c219693 762 #define CRC_DR_DR_Pos (0U)
hudakz 0:2cf53c219693 763 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 764 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
hudakz 0:2cf53c219693 765
hudakz 0:2cf53c219693 766 /******************* Bit definition for CRC_IDR register ********************/
hudakz 0:2cf53c219693 767 #define CRC_IDR_IDR_Pos (0U)
hudakz 0:2cf53c219693 768 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 769 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
hudakz 0:2cf53c219693 770
hudakz 0:2cf53c219693 771 /******************** Bit definition for CRC_CR register ********************/
hudakz 0:2cf53c219693 772 #define CRC_CR_RESET_Pos (0U)
hudakz 0:2cf53c219693 773 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 774 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
hudakz 0:2cf53c219693 775
hudakz 0:2cf53c219693 776 /******************************************************************************/
hudakz 0:2cf53c219693 777 /* */
hudakz 0:2cf53c219693 778 /* Power Control */
hudakz 0:2cf53c219693 779 /* */
hudakz 0:2cf53c219693 780 /******************************************************************************/
hudakz 0:2cf53c219693 781
hudakz 0:2cf53c219693 782 /******************** Bit definition for PWR_CR register ********************/
hudakz 0:2cf53c219693 783 #define PWR_CR_LPDS_Pos (0U)
hudakz 0:2cf53c219693 784 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 785 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
hudakz 0:2cf53c219693 786 #define PWR_CR_PDDS_Pos (1U)
hudakz 0:2cf53c219693 787 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 788 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
hudakz 0:2cf53c219693 789 #define PWR_CR_CWUF_Pos (2U)
hudakz 0:2cf53c219693 790 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 791 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
hudakz 0:2cf53c219693 792 #define PWR_CR_CSBF_Pos (3U)
hudakz 0:2cf53c219693 793 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 794 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
hudakz 0:2cf53c219693 795 #define PWR_CR_PVDE_Pos (4U)
hudakz 0:2cf53c219693 796 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 797 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
hudakz 0:2cf53c219693 798
hudakz 0:2cf53c219693 799 #define PWR_CR_PLS_Pos (5U)
hudakz 0:2cf53c219693 800 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
hudakz 0:2cf53c219693 801 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
hudakz 0:2cf53c219693 802 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 803 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 804 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 805
hudakz 0:2cf53c219693 806 /*!< PVD level configuration */
hudakz 0:2cf53c219693 807 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
hudakz 0:2cf53c219693 808 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
hudakz 0:2cf53c219693 809 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
hudakz 0:2cf53c219693 810 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
hudakz 0:2cf53c219693 811 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
hudakz 0:2cf53c219693 812 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
hudakz 0:2cf53c219693 813 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
hudakz 0:2cf53c219693 814 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
hudakz 0:2cf53c219693 815
hudakz 0:2cf53c219693 816 /* Legacy defines */
hudakz 0:2cf53c219693 817 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
hudakz 0:2cf53c219693 818 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
hudakz 0:2cf53c219693 819 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
hudakz 0:2cf53c219693 820 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
hudakz 0:2cf53c219693 821 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
hudakz 0:2cf53c219693 822 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
hudakz 0:2cf53c219693 823 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
hudakz 0:2cf53c219693 824 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
hudakz 0:2cf53c219693 825
hudakz 0:2cf53c219693 826 #define PWR_CR_DBP_Pos (8U)
hudakz 0:2cf53c219693 827 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 828 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
hudakz 0:2cf53c219693 829
hudakz 0:2cf53c219693 830
hudakz 0:2cf53c219693 831 /******************* Bit definition for PWR_CSR register ********************/
hudakz 0:2cf53c219693 832 #define PWR_CSR_WUF_Pos (0U)
hudakz 0:2cf53c219693 833 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 834 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
hudakz 0:2cf53c219693 835 #define PWR_CSR_SBF_Pos (1U)
hudakz 0:2cf53c219693 836 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 837 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
hudakz 0:2cf53c219693 838 #define PWR_CSR_PVDO_Pos (2U)
hudakz 0:2cf53c219693 839 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 840 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
hudakz 0:2cf53c219693 841 #define PWR_CSR_EWUP_Pos (8U)
hudakz 0:2cf53c219693 842 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 843 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
hudakz 0:2cf53c219693 844
hudakz 0:2cf53c219693 845 /******************************************************************************/
hudakz 0:2cf53c219693 846 /* */
hudakz 0:2cf53c219693 847 /* Backup registers */
hudakz 0:2cf53c219693 848 /* */
hudakz 0:2cf53c219693 849 /******************************************************************************/
hudakz 0:2cf53c219693 850
hudakz 0:2cf53c219693 851 /******************* Bit definition for BKP_DR1 register ********************/
hudakz 0:2cf53c219693 852 #define BKP_DR1_D_Pos (0U)
hudakz 0:2cf53c219693 853 #define BKP_DR1_D_Msk (0xFFFFU << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 854 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 855
hudakz 0:2cf53c219693 856 /******************* Bit definition for BKP_DR2 register ********************/
hudakz 0:2cf53c219693 857 #define BKP_DR2_D_Pos (0U)
hudakz 0:2cf53c219693 858 #define BKP_DR2_D_Msk (0xFFFFU << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 859 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 860
hudakz 0:2cf53c219693 861 /******************* Bit definition for BKP_DR3 register ********************/
hudakz 0:2cf53c219693 862 #define BKP_DR3_D_Pos (0U)
hudakz 0:2cf53c219693 863 #define BKP_DR3_D_Msk (0xFFFFU << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 864 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 865
hudakz 0:2cf53c219693 866 /******************* Bit definition for BKP_DR4 register ********************/
hudakz 0:2cf53c219693 867 #define BKP_DR4_D_Pos (0U)
hudakz 0:2cf53c219693 868 #define BKP_DR4_D_Msk (0xFFFFU << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 869 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 870
hudakz 0:2cf53c219693 871 /******************* Bit definition for BKP_DR5 register ********************/
hudakz 0:2cf53c219693 872 #define BKP_DR5_D_Pos (0U)
hudakz 0:2cf53c219693 873 #define BKP_DR5_D_Msk (0xFFFFU << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 874 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 875
hudakz 0:2cf53c219693 876 /******************* Bit definition for BKP_DR6 register ********************/
hudakz 0:2cf53c219693 877 #define BKP_DR6_D_Pos (0U)
hudakz 0:2cf53c219693 878 #define BKP_DR6_D_Msk (0xFFFFU << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 879 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 880
hudakz 0:2cf53c219693 881 /******************* Bit definition for BKP_DR7 register ********************/
hudakz 0:2cf53c219693 882 #define BKP_DR7_D_Pos (0U)
hudakz 0:2cf53c219693 883 #define BKP_DR7_D_Msk (0xFFFFU << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 884 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 885
hudakz 0:2cf53c219693 886 /******************* Bit definition for BKP_DR8 register ********************/
hudakz 0:2cf53c219693 887 #define BKP_DR8_D_Pos (0U)
hudakz 0:2cf53c219693 888 #define BKP_DR8_D_Msk (0xFFFFU << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 889 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 890
hudakz 0:2cf53c219693 891 /******************* Bit definition for BKP_DR9 register ********************/
hudakz 0:2cf53c219693 892 #define BKP_DR9_D_Pos (0U)
hudakz 0:2cf53c219693 893 #define BKP_DR9_D_Msk (0xFFFFU << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 894 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 895
hudakz 0:2cf53c219693 896 /******************* Bit definition for BKP_DR10 register *******************/
hudakz 0:2cf53c219693 897 #define BKP_DR10_D_Pos (0U)
hudakz 0:2cf53c219693 898 #define BKP_DR10_D_Msk (0xFFFFU << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 899 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
hudakz 0:2cf53c219693 900
hudakz 0:2cf53c219693 901 #define RTC_BKP_NUMBER 10
hudakz 0:2cf53c219693 902
hudakz 0:2cf53c219693 903 /****************** Bit definition for BKP_RTCCR register *******************/
hudakz 0:2cf53c219693 904 #define BKP_RTCCR_CAL_Pos (0U)
hudakz 0:2cf53c219693 905 #define BKP_RTCCR_CAL_Msk (0x7FU << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
hudakz 0:2cf53c219693 906 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
hudakz 0:2cf53c219693 907 #define BKP_RTCCR_CCO_Pos (7U)
hudakz 0:2cf53c219693 908 #define BKP_RTCCR_CCO_Msk (0x1U << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 909 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
hudakz 0:2cf53c219693 910 #define BKP_RTCCR_ASOE_Pos (8U)
hudakz 0:2cf53c219693 911 #define BKP_RTCCR_ASOE_Msk (0x1U << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 912 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
hudakz 0:2cf53c219693 913 #define BKP_RTCCR_ASOS_Pos (9U)
hudakz 0:2cf53c219693 914 #define BKP_RTCCR_ASOS_Msk (0x1U << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 915 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
hudakz 0:2cf53c219693 916
hudakz 0:2cf53c219693 917 /******************** Bit definition for BKP_CR register ********************/
hudakz 0:2cf53c219693 918 #define BKP_CR_TPE_Pos (0U)
hudakz 0:2cf53c219693 919 #define BKP_CR_TPE_Msk (0x1U << BKP_CR_TPE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 920 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
hudakz 0:2cf53c219693 921 #define BKP_CR_TPAL_Pos (1U)
hudakz 0:2cf53c219693 922 #define BKP_CR_TPAL_Msk (0x1U << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 923 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
hudakz 0:2cf53c219693 924
hudakz 0:2cf53c219693 925 /******************* Bit definition for BKP_CSR register ********************/
hudakz 0:2cf53c219693 926 #define BKP_CSR_CTE_Pos (0U)
hudakz 0:2cf53c219693 927 #define BKP_CSR_CTE_Msk (0x1U << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 928 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
hudakz 0:2cf53c219693 929 #define BKP_CSR_CTI_Pos (1U)
hudakz 0:2cf53c219693 930 #define BKP_CSR_CTI_Msk (0x1U << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 931 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
hudakz 0:2cf53c219693 932 #define BKP_CSR_TPIE_Pos (2U)
hudakz 0:2cf53c219693 933 #define BKP_CSR_TPIE_Msk (0x1U << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 934 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
hudakz 0:2cf53c219693 935 #define BKP_CSR_TEF_Pos (8U)
hudakz 0:2cf53c219693 936 #define BKP_CSR_TEF_Msk (0x1U << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 937 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
hudakz 0:2cf53c219693 938 #define BKP_CSR_TIF_Pos (9U)
hudakz 0:2cf53c219693 939 #define BKP_CSR_TIF_Msk (0x1U << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 940 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
hudakz 0:2cf53c219693 941
hudakz 0:2cf53c219693 942 /******************************************************************************/
hudakz 0:2cf53c219693 943 /* */
hudakz 0:2cf53c219693 944 /* Reset and Clock Control */
hudakz 0:2cf53c219693 945 /* */
hudakz 0:2cf53c219693 946 /******************************************************************************/
hudakz 0:2cf53c219693 947
hudakz 0:2cf53c219693 948 /******************** Bit definition for RCC_CR register ********************/
hudakz 0:2cf53c219693 949 #define RCC_CR_HSION_Pos (0U)
hudakz 0:2cf53c219693 950 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 951 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
hudakz 0:2cf53c219693 952 #define RCC_CR_HSIRDY_Pos (1U)
hudakz 0:2cf53c219693 953 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 954 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
hudakz 0:2cf53c219693 955 #define RCC_CR_HSITRIM_Pos (3U)
hudakz 0:2cf53c219693 956 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
hudakz 0:2cf53c219693 957 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
hudakz 0:2cf53c219693 958 #define RCC_CR_HSICAL_Pos (8U)
hudakz 0:2cf53c219693 959 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 960 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
hudakz 0:2cf53c219693 961 #define RCC_CR_HSEON_Pos (16U)
hudakz 0:2cf53c219693 962 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 963 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
hudakz 0:2cf53c219693 964 #define RCC_CR_HSERDY_Pos (17U)
hudakz 0:2cf53c219693 965 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 966 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
hudakz 0:2cf53c219693 967 #define RCC_CR_HSEBYP_Pos (18U)
hudakz 0:2cf53c219693 968 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 969 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
hudakz 0:2cf53c219693 970 #define RCC_CR_CSSON_Pos (19U)
hudakz 0:2cf53c219693 971 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 972 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
hudakz 0:2cf53c219693 973 #define RCC_CR_PLLON_Pos (24U)
hudakz 0:2cf53c219693 974 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 975 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
hudakz 0:2cf53c219693 976 #define RCC_CR_PLLRDY_Pos (25U)
hudakz 0:2cf53c219693 977 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 978 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
hudakz 0:2cf53c219693 979
hudakz 0:2cf53c219693 980
hudakz 0:2cf53c219693 981 /******************* Bit definition for RCC_CFGR register *******************/
hudakz 0:2cf53c219693 982 /*!< SW configuration */
hudakz 0:2cf53c219693 983 #define RCC_CFGR_SW_Pos (0U)
hudakz 0:2cf53c219693 984 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 985 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
hudakz 0:2cf53c219693 986 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 987 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 988
hudakz 0:2cf53c219693 989 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
hudakz 0:2cf53c219693 990 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
hudakz 0:2cf53c219693 991 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
hudakz 0:2cf53c219693 992
hudakz 0:2cf53c219693 993 /*!< SWS configuration */
hudakz 0:2cf53c219693 994 #define RCC_CFGR_SWS_Pos (2U)
hudakz 0:2cf53c219693 995 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
hudakz 0:2cf53c219693 996 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
hudakz 0:2cf53c219693 997 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 998 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 999
hudakz 0:2cf53c219693 1000 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
hudakz 0:2cf53c219693 1001 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
hudakz 0:2cf53c219693 1002 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
hudakz 0:2cf53c219693 1003
hudakz 0:2cf53c219693 1004 /*!< HPRE configuration */
hudakz 0:2cf53c219693 1005 #define RCC_CFGR_HPRE_Pos (4U)
hudakz 0:2cf53c219693 1006 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 1007 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
hudakz 0:2cf53c219693 1008 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1009 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1010 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1011 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1012
hudakz 0:2cf53c219693 1013 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
hudakz 0:2cf53c219693 1014 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
hudakz 0:2cf53c219693 1015 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
hudakz 0:2cf53c219693 1016 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
hudakz 0:2cf53c219693 1017 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
hudakz 0:2cf53c219693 1018 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
hudakz 0:2cf53c219693 1019 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
hudakz 0:2cf53c219693 1020 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
hudakz 0:2cf53c219693 1021 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
hudakz 0:2cf53c219693 1022
hudakz 0:2cf53c219693 1023 /*!< PPRE1 configuration */
hudakz 0:2cf53c219693 1024 #define RCC_CFGR_PPRE1_Pos (8U)
hudakz 0:2cf53c219693 1025 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
hudakz 0:2cf53c219693 1026 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
hudakz 0:2cf53c219693 1027 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1028 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1029 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1030
hudakz 0:2cf53c219693 1031 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
hudakz 0:2cf53c219693 1032 #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
hudakz 0:2cf53c219693 1033 #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
hudakz 0:2cf53c219693 1034 #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
hudakz 0:2cf53c219693 1035 #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
hudakz 0:2cf53c219693 1036
hudakz 0:2cf53c219693 1037 /*!< PPRE2 configuration */
hudakz 0:2cf53c219693 1038 #define RCC_CFGR_PPRE2_Pos (11U)
hudakz 0:2cf53c219693 1039 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
hudakz 0:2cf53c219693 1040 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
hudakz 0:2cf53c219693 1041 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1042 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1043 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1044
hudakz 0:2cf53c219693 1045 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
hudakz 0:2cf53c219693 1046 #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
hudakz 0:2cf53c219693 1047 #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
hudakz 0:2cf53c219693 1048 #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
hudakz 0:2cf53c219693 1049 #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
hudakz 0:2cf53c219693 1050
hudakz 0:2cf53c219693 1051 /*!< ADCPPRE configuration */
hudakz 0:2cf53c219693 1052 #define RCC_CFGR_ADCPRE_Pos (14U)
hudakz 0:2cf53c219693 1053 #define RCC_CFGR_ADCPRE_Msk (0x3U << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
hudakz 0:2cf53c219693 1054 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
hudakz 0:2cf53c219693 1055 #define RCC_CFGR_ADCPRE_0 (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1056 #define RCC_CFGR_ADCPRE_1 (0x2U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1057
hudakz 0:2cf53c219693 1058 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
hudakz 0:2cf53c219693 1059 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
hudakz 0:2cf53c219693 1060 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
hudakz 0:2cf53c219693 1061 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
hudakz 0:2cf53c219693 1062
hudakz 0:2cf53c219693 1063 #define RCC_CFGR_PLLSRC_Pos (16U)
hudakz 0:2cf53c219693 1064 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 1065 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
hudakz 0:2cf53c219693 1066
hudakz 0:2cf53c219693 1067 #define RCC_CFGR_PLLXTPRE_Pos (17U)
hudakz 0:2cf53c219693 1068 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 1069 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
hudakz 0:2cf53c219693 1070
hudakz 0:2cf53c219693 1071 /*!< PLLMUL configuration */
hudakz 0:2cf53c219693 1072 #define RCC_CFGR_PLLMULL_Pos (18U)
hudakz 0:2cf53c219693 1073 #define RCC_CFGR_PLLMULL_Msk (0xFU << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
hudakz 0:2cf53c219693 1074 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
hudakz 0:2cf53c219693 1075 #define RCC_CFGR_PLLMULL_0 (0x1U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1076 #define RCC_CFGR_PLLMULL_1 (0x2U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 1077 #define RCC_CFGR_PLLMULL_2 (0x4U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 1078 #define RCC_CFGR_PLLMULL_3 (0x8U << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 1079
hudakz 0:2cf53c219693 1080 #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
hudakz 0:2cf53c219693 1081 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
hudakz 0:2cf53c219693 1082
hudakz 0:2cf53c219693 1083 #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
hudakz 0:2cf53c219693 1084 #define RCC_CFGR_PLLMULL3_Pos (18U)
hudakz 0:2cf53c219693 1085 #define RCC_CFGR_PLLMULL3_Msk (0x1U << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1086 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
hudakz 0:2cf53c219693 1087 #define RCC_CFGR_PLLMULL4_Pos (19U)
hudakz 0:2cf53c219693 1088 #define RCC_CFGR_PLLMULL4_Msk (0x1U << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 1089 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
hudakz 0:2cf53c219693 1090 #define RCC_CFGR_PLLMULL5_Pos (18U)
hudakz 0:2cf53c219693 1091 #define RCC_CFGR_PLLMULL5_Msk (0x3U << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
hudakz 0:2cf53c219693 1092 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
hudakz 0:2cf53c219693 1093 #define RCC_CFGR_PLLMULL6_Pos (20U)
hudakz 0:2cf53c219693 1094 #define RCC_CFGR_PLLMULL6_Msk (0x1U << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 1095 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
hudakz 0:2cf53c219693 1096 #define RCC_CFGR_PLLMULL7_Pos (18U)
hudakz 0:2cf53c219693 1097 #define RCC_CFGR_PLLMULL7_Msk (0x5U << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
hudakz 0:2cf53c219693 1098 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
hudakz 0:2cf53c219693 1099 #define RCC_CFGR_PLLMULL8_Pos (19U)
hudakz 0:2cf53c219693 1100 #define RCC_CFGR_PLLMULL8_Msk (0x3U << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
hudakz 0:2cf53c219693 1101 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
hudakz 0:2cf53c219693 1102 #define RCC_CFGR_PLLMULL9_Pos (18U)
hudakz 0:2cf53c219693 1103 #define RCC_CFGR_PLLMULL9_Msk (0x7U << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
hudakz 0:2cf53c219693 1104 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
hudakz 0:2cf53c219693 1105 #define RCC_CFGR_PLLMULL10_Pos (21U)
hudakz 0:2cf53c219693 1106 #define RCC_CFGR_PLLMULL10_Msk (0x1U << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 1107 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
hudakz 0:2cf53c219693 1108 #define RCC_CFGR_PLLMULL11_Pos (18U)
hudakz 0:2cf53c219693 1109 #define RCC_CFGR_PLLMULL11_Msk (0x9U << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
hudakz 0:2cf53c219693 1110 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
hudakz 0:2cf53c219693 1111 #define RCC_CFGR_PLLMULL12_Pos (19U)
hudakz 0:2cf53c219693 1112 #define RCC_CFGR_PLLMULL12_Msk (0x5U << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
hudakz 0:2cf53c219693 1113 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
hudakz 0:2cf53c219693 1114 #define RCC_CFGR_PLLMULL13_Pos (18U)
hudakz 0:2cf53c219693 1115 #define RCC_CFGR_PLLMULL13_Msk (0xBU << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
hudakz 0:2cf53c219693 1116 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
hudakz 0:2cf53c219693 1117 #define RCC_CFGR_PLLMULL14_Pos (20U)
hudakz 0:2cf53c219693 1118 #define RCC_CFGR_PLLMULL14_Msk (0x3U << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
hudakz 0:2cf53c219693 1119 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
hudakz 0:2cf53c219693 1120 #define RCC_CFGR_PLLMULL15_Pos (18U)
hudakz 0:2cf53c219693 1121 #define RCC_CFGR_PLLMULL15_Msk (0xDU << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
hudakz 0:2cf53c219693 1122 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
hudakz 0:2cf53c219693 1123 #define RCC_CFGR_PLLMULL16_Pos (19U)
hudakz 0:2cf53c219693 1124 #define RCC_CFGR_PLLMULL16_Msk (0x7U << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
hudakz 0:2cf53c219693 1125 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
hudakz 0:2cf53c219693 1126 #define RCC_CFGR_USBPRE_Pos (22U)
hudakz 0:2cf53c219693 1127 #define RCC_CFGR_USBPRE_Msk (0x1U << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 1128 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
hudakz 0:2cf53c219693 1129
hudakz 0:2cf53c219693 1130 /*!< MCO configuration */
hudakz 0:2cf53c219693 1131 #define RCC_CFGR_MCO_Pos (24U)
hudakz 0:2cf53c219693 1132 #define RCC_CFGR_MCO_Msk (0x7U << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
hudakz 0:2cf53c219693 1133 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
hudakz 0:2cf53c219693 1134 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 1135 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 1136 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 1137
hudakz 0:2cf53c219693 1138 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
hudakz 0:2cf53c219693 1139 #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
hudakz 0:2cf53c219693 1140 #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
hudakz 0:2cf53c219693 1141 #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
hudakz 0:2cf53c219693 1142 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
hudakz 0:2cf53c219693 1143
hudakz 0:2cf53c219693 1144 /* Reference defines */
hudakz 0:2cf53c219693 1145 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
hudakz 0:2cf53c219693 1146 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
hudakz 0:2cf53c219693 1147 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
hudakz 0:2cf53c219693 1148 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
hudakz 0:2cf53c219693 1149 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
hudakz 0:2cf53c219693 1150 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
hudakz 0:2cf53c219693 1151 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
hudakz 0:2cf53c219693 1152 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
hudakz 0:2cf53c219693 1153 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
hudakz 0:2cf53c219693 1154
hudakz 0:2cf53c219693 1155 /*!<****************** Bit definition for RCC_CIR register ********************/
hudakz 0:2cf53c219693 1156 #define RCC_CIR_LSIRDYF_Pos (0U)
hudakz 0:2cf53c219693 1157 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1158 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
hudakz 0:2cf53c219693 1159 #define RCC_CIR_LSERDYF_Pos (1U)
hudakz 0:2cf53c219693 1160 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1161 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
hudakz 0:2cf53c219693 1162 #define RCC_CIR_HSIRDYF_Pos (2U)
hudakz 0:2cf53c219693 1163 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1164 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
hudakz 0:2cf53c219693 1165 #define RCC_CIR_HSERDYF_Pos (3U)
hudakz 0:2cf53c219693 1166 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1167 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
hudakz 0:2cf53c219693 1168 #define RCC_CIR_PLLRDYF_Pos (4U)
hudakz 0:2cf53c219693 1169 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1170 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
hudakz 0:2cf53c219693 1171 #define RCC_CIR_CSSF_Pos (7U)
hudakz 0:2cf53c219693 1172 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1173 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
hudakz 0:2cf53c219693 1174 #define RCC_CIR_LSIRDYIE_Pos (8U)
hudakz 0:2cf53c219693 1175 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1176 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
hudakz 0:2cf53c219693 1177 #define RCC_CIR_LSERDYIE_Pos (9U)
hudakz 0:2cf53c219693 1178 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1179 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
hudakz 0:2cf53c219693 1180 #define RCC_CIR_HSIRDYIE_Pos (10U)
hudakz 0:2cf53c219693 1181 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1182 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
hudakz 0:2cf53c219693 1183 #define RCC_CIR_HSERDYIE_Pos (11U)
hudakz 0:2cf53c219693 1184 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1185 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
hudakz 0:2cf53c219693 1186 #define RCC_CIR_PLLRDYIE_Pos (12U)
hudakz 0:2cf53c219693 1187 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1188 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
hudakz 0:2cf53c219693 1189 #define RCC_CIR_LSIRDYC_Pos (16U)
hudakz 0:2cf53c219693 1190 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 1191 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
hudakz 0:2cf53c219693 1192 #define RCC_CIR_LSERDYC_Pos (17U)
hudakz 0:2cf53c219693 1193 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 1194 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
hudakz 0:2cf53c219693 1195 #define RCC_CIR_HSIRDYC_Pos (18U)
hudakz 0:2cf53c219693 1196 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1197 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
hudakz 0:2cf53c219693 1198 #define RCC_CIR_HSERDYC_Pos (19U)
hudakz 0:2cf53c219693 1199 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 1200 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
hudakz 0:2cf53c219693 1201 #define RCC_CIR_PLLRDYC_Pos (20U)
hudakz 0:2cf53c219693 1202 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 1203 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
hudakz 0:2cf53c219693 1204 #define RCC_CIR_CSSC_Pos (23U)
hudakz 0:2cf53c219693 1205 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 1206 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
hudakz 0:2cf53c219693 1207
hudakz 0:2cf53c219693 1208
hudakz 0:2cf53c219693 1209 /***************** Bit definition for RCC_APB2RSTR register *****************/
hudakz 0:2cf53c219693 1210 #define RCC_APB2RSTR_AFIORST_Pos (0U)
hudakz 0:2cf53c219693 1211 #define RCC_APB2RSTR_AFIORST_Msk (0x1U << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1212 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
hudakz 0:2cf53c219693 1213 #define RCC_APB2RSTR_IOPARST_Pos (2U)
hudakz 0:2cf53c219693 1214 #define RCC_APB2RSTR_IOPARST_Msk (0x1U << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1215 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
hudakz 0:2cf53c219693 1216 #define RCC_APB2RSTR_IOPBRST_Pos (3U)
hudakz 0:2cf53c219693 1217 #define RCC_APB2RSTR_IOPBRST_Msk (0x1U << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1218 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
hudakz 0:2cf53c219693 1219 #define RCC_APB2RSTR_IOPCRST_Pos (4U)
hudakz 0:2cf53c219693 1220 #define RCC_APB2RSTR_IOPCRST_Msk (0x1U << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1221 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
hudakz 0:2cf53c219693 1222 #define RCC_APB2RSTR_IOPDRST_Pos (5U)
hudakz 0:2cf53c219693 1223 #define RCC_APB2RSTR_IOPDRST_Msk (0x1U << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1224 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
hudakz 0:2cf53c219693 1225 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
hudakz 0:2cf53c219693 1226 #define RCC_APB2RSTR_ADC1RST_Msk (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1227 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
hudakz 0:2cf53c219693 1228
hudakz 0:2cf53c219693 1229 #define RCC_APB2RSTR_ADC2RST_Pos (10U)
hudakz 0:2cf53c219693 1230 #define RCC_APB2RSTR_ADC2RST_Msk (0x1U << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1231 #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
hudakz 0:2cf53c219693 1232
hudakz 0:2cf53c219693 1233 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
hudakz 0:2cf53c219693 1234 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1235 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
hudakz 0:2cf53c219693 1236 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
hudakz 0:2cf53c219693 1237 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1238 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
hudakz 0:2cf53c219693 1239 #define RCC_APB2RSTR_USART1RST_Pos (14U)
hudakz 0:2cf53c219693 1240 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1241 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
hudakz 0:2cf53c219693 1242
hudakz 0:2cf53c219693 1243
hudakz 0:2cf53c219693 1244 #define RCC_APB2RSTR_IOPERST_Pos (6U)
hudakz 0:2cf53c219693 1245 #define RCC_APB2RSTR_IOPERST_Msk (0x1U << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1246 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
hudakz 0:2cf53c219693 1247
hudakz 0:2cf53c219693 1248
hudakz 0:2cf53c219693 1249
hudakz 0:2cf53c219693 1250
hudakz 0:2cf53c219693 1251 /***************** Bit definition for RCC_APB1RSTR register *****************/
hudakz 0:2cf53c219693 1252 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
hudakz 0:2cf53c219693 1253 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1254 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
hudakz 0:2cf53c219693 1255 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
hudakz 0:2cf53c219693 1256 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1257 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
hudakz 0:2cf53c219693 1258 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
hudakz 0:2cf53c219693 1259 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1260 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
hudakz 0:2cf53c219693 1261 #define RCC_APB1RSTR_USART2RST_Pos (17U)
hudakz 0:2cf53c219693 1262 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 1263 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
hudakz 0:2cf53c219693 1264 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
hudakz 0:2cf53c219693 1265 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 1266 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
hudakz 0:2cf53c219693 1267
hudakz 0:2cf53c219693 1268 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
hudakz 0:2cf53c219693 1269 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 1270 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
hudakz 0:2cf53c219693 1271
hudakz 0:2cf53c219693 1272 #define RCC_APB1RSTR_BKPRST_Pos (27U)
hudakz 0:2cf53c219693 1273 #define RCC_APB1RSTR_BKPRST_Msk (0x1U << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 1274 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
hudakz 0:2cf53c219693 1275 #define RCC_APB1RSTR_PWRRST_Pos (28U)
hudakz 0:2cf53c219693 1276 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 1277 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
hudakz 0:2cf53c219693 1278
hudakz 0:2cf53c219693 1279 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
hudakz 0:2cf53c219693 1280 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1281 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
hudakz 0:2cf53c219693 1282 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
hudakz 0:2cf53c219693 1283 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1284 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
hudakz 0:2cf53c219693 1285 #define RCC_APB1RSTR_USART3RST_Pos (18U)
hudakz 0:2cf53c219693 1286 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1287 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
hudakz 0:2cf53c219693 1288 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
hudakz 0:2cf53c219693 1289 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 1290 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
hudakz 0:2cf53c219693 1291
hudakz 0:2cf53c219693 1292 #define RCC_APB1RSTR_USBRST_Pos (23U)
hudakz 0:2cf53c219693 1293 #define RCC_APB1RSTR_USBRST_Msk (0x1U << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 1294 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
hudakz 0:2cf53c219693 1295
hudakz 0:2cf53c219693 1296
hudakz 0:2cf53c219693 1297
hudakz 0:2cf53c219693 1298
hudakz 0:2cf53c219693 1299
hudakz 0:2cf53c219693 1300
hudakz 0:2cf53c219693 1301 /****************** Bit definition for RCC_AHBENR register ******************/
hudakz 0:2cf53c219693 1302 #define RCC_AHBENR_DMA1EN_Pos (0U)
hudakz 0:2cf53c219693 1303 #define RCC_AHBENR_DMA1EN_Msk (0x1U << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1304 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
hudakz 0:2cf53c219693 1305 #define RCC_AHBENR_SRAMEN_Pos (2U)
hudakz 0:2cf53c219693 1306 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1307 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
hudakz 0:2cf53c219693 1308 #define RCC_AHBENR_FLITFEN_Pos (4U)
hudakz 0:2cf53c219693 1309 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1310 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
hudakz 0:2cf53c219693 1311 #define RCC_AHBENR_CRCEN_Pos (6U)
hudakz 0:2cf53c219693 1312 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1313 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
hudakz 0:2cf53c219693 1314
hudakz 0:2cf53c219693 1315
hudakz 0:2cf53c219693 1316
hudakz 0:2cf53c219693 1317
hudakz 0:2cf53c219693 1318 /****************** Bit definition for RCC_APB2ENR register *****************/
hudakz 0:2cf53c219693 1319 #define RCC_APB2ENR_AFIOEN_Pos (0U)
hudakz 0:2cf53c219693 1320 #define RCC_APB2ENR_AFIOEN_Msk (0x1U << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1321 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
hudakz 0:2cf53c219693 1322 #define RCC_APB2ENR_IOPAEN_Pos (2U)
hudakz 0:2cf53c219693 1323 #define RCC_APB2ENR_IOPAEN_Msk (0x1U << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1324 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
hudakz 0:2cf53c219693 1325 #define RCC_APB2ENR_IOPBEN_Pos (3U)
hudakz 0:2cf53c219693 1326 #define RCC_APB2ENR_IOPBEN_Msk (0x1U << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1327 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
hudakz 0:2cf53c219693 1328 #define RCC_APB2ENR_IOPCEN_Pos (4U)
hudakz 0:2cf53c219693 1329 #define RCC_APB2ENR_IOPCEN_Msk (0x1U << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1330 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
hudakz 0:2cf53c219693 1331 #define RCC_APB2ENR_IOPDEN_Pos (5U)
hudakz 0:2cf53c219693 1332 #define RCC_APB2ENR_IOPDEN_Msk (0x1U << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1333 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
hudakz 0:2cf53c219693 1334 #define RCC_APB2ENR_ADC1EN_Pos (9U)
hudakz 0:2cf53c219693 1335 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1336 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
hudakz 0:2cf53c219693 1337
hudakz 0:2cf53c219693 1338 #define RCC_APB2ENR_ADC2EN_Pos (10U)
hudakz 0:2cf53c219693 1339 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1340 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
hudakz 0:2cf53c219693 1341
hudakz 0:2cf53c219693 1342 #define RCC_APB2ENR_TIM1EN_Pos (11U)
hudakz 0:2cf53c219693 1343 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1344 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
hudakz 0:2cf53c219693 1345 #define RCC_APB2ENR_SPI1EN_Pos (12U)
hudakz 0:2cf53c219693 1346 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1347 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
hudakz 0:2cf53c219693 1348 #define RCC_APB2ENR_USART1EN_Pos (14U)
hudakz 0:2cf53c219693 1349 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1350 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
hudakz 0:2cf53c219693 1351
hudakz 0:2cf53c219693 1352
hudakz 0:2cf53c219693 1353 #define RCC_APB2ENR_IOPEEN_Pos (6U)
hudakz 0:2cf53c219693 1354 #define RCC_APB2ENR_IOPEEN_Msk (0x1U << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1355 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
hudakz 0:2cf53c219693 1356
hudakz 0:2cf53c219693 1357
hudakz 0:2cf53c219693 1358
hudakz 0:2cf53c219693 1359
hudakz 0:2cf53c219693 1360 /***************** Bit definition for RCC_APB1ENR register ******************/
hudakz 0:2cf53c219693 1361 #define RCC_APB1ENR_TIM2EN_Pos (0U)
hudakz 0:2cf53c219693 1362 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1363 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
hudakz 0:2cf53c219693 1364 #define RCC_APB1ENR_TIM3EN_Pos (1U)
hudakz 0:2cf53c219693 1365 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1366 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
hudakz 0:2cf53c219693 1367 #define RCC_APB1ENR_WWDGEN_Pos (11U)
hudakz 0:2cf53c219693 1368 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1369 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
hudakz 0:2cf53c219693 1370 #define RCC_APB1ENR_USART2EN_Pos (17U)
hudakz 0:2cf53c219693 1371 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 1372 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
hudakz 0:2cf53c219693 1373 #define RCC_APB1ENR_I2C1EN_Pos (21U)
hudakz 0:2cf53c219693 1374 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 1375 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
hudakz 0:2cf53c219693 1376
hudakz 0:2cf53c219693 1377 #define RCC_APB1ENR_CAN1EN_Pos (25U)
hudakz 0:2cf53c219693 1378 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 1379 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
hudakz 0:2cf53c219693 1380
hudakz 0:2cf53c219693 1381 #define RCC_APB1ENR_BKPEN_Pos (27U)
hudakz 0:2cf53c219693 1382 #define RCC_APB1ENR_BKPEN_Msk (0x1U << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 1383 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
hudakz 0:2cf53c219693 1384 #define RCC_APB1ENR_PWREN_Pos (28U)
hudakz 0:2cf53c219693 1385 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 1386 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
hudakz 0:2cf53c219693 1387
hudakz 0:2cf53c219693 1388 #define RCC_APB1ENR_TIM4EN_Pos (2U)
hudakz 0:2cf53c219693 1389 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1390 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
hudakz 0:2cf53c219693 1391 #define RCC_APB1ENR_SPI2EN_Pos (14U)
hudakz 0:2cf53c219693 1392 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1393 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
hudakz 0:2cf53c219693 1394 #define RCC_APB1ENR_USART3EN_Pos (18U)
hudakz 0:2cf53c219693 1395 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1396 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
hudakz 0:2cf53c219693 1397 #define RCC_APB1ENR_I2C2EN_Pos (22U)
hudakz 0:2cf53c219693 1398 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 1399 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
hudakz 0:2cf53c219693 1400
hudakz 0:2cf53c219693 1401 #define RCC_APB1ENR_USBEN_Pos (23U)
hudakz 0:2cf53c219693 1402 #define RCC_APB1ENR_USBEN_Msk (0x1U << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 1403 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
hudakz 0:2cf53c219693 1404
hudakz 0:2cf53c219693 1405
hudakz 0:2cf53c219693 1406
hudakz 0:2cf53c219693 1407
hudakz 0:2cf53c219693 1408
hudakz 0:2cf53c219693 1409
hudakz 0:2cf53c219693 1410 /******************* Bit definition for RCC_BDCR register *******************/
hudakz 0:2cf53c219693 1411 #define RCC_BDCR_LSEON_Pos (0U)
hudakz 0:2cf53c219693 1412 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1413 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
hudakz 0:2cf53c219693 1414 #define RCC_BDCR_LSERDY_Pos (1U)
hudakz 0:2cf53c219693 1415 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1416 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
hudakz 0:2cf53c219693 1417 #define RCC_BDCR_LSEBYP_Pos (2U)
hudakz 0:2cf53c219693 1418 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1419 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
hudakz 0:2cf53c219693 1420
hudakz 0:2cf53c219693 1421 #define RCC_BDCR_RTCSEL_Pos (8U)
hudakz 0:2cf53c219693 1422 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 1423 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
hudakz 0:2cf53c219693 1424 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1425 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1426
hudakz 0:2cf53c219693 1427 /*!< RTC congiguration */
hudakz 0:2cf53c219693 1428 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
hudakz 0:2cf53c219693 1429 #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
hudakz 0:2cf53c219693 1430 #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
hudakz 0:2cf53c219693 1431 #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
hudakz 0:2cf53c219693 1432
hudakz 0:2cf53c219693 1433 #define RCC_BDCR_RTCEN_Pos (15U)
hudakz 0:2cf53c219693 1434 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1435 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
hudakz 0:2cf53c219693 1436 #define RCC_BDCR_BDRST_Pos (16U)
hudakz 0:2cf53c219693 1437 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 1438 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
hudakz 0:2cf53c219693 1439
hudakz 0:2cf53c219693 1440 /******************* Bit definition for RCC_CSR register ********************/
hudakz 0:2cf53c219693 1441 #define RCC_CSR_LSION_Pos (0U)
hudakz 0:2cf53c219693 1442 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1443 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
hudakz 0:2cf53c219693 1444 #define RCC_CSR_LSIRDY_Pos (1U)
hudakz 0:2cf53c219693 1445 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1446 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
hudakz 0:2cf53c219693 1447 #define RCC_CSR_RMVF_Pos (24U)
hudakz 0:2cf53c219693 1448 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 1449 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
hudakz 0:2cf53c219693 1450 #define RCC_CSR_PINRSTF_Pos (26U)
hudakz 0:2cf53c219693 1451 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 1452 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
hudakz 0:2cf53c219693 1453 #define RCC_CSR_PORRSTF_Pos (27U)
hudakz 0:2cf53c219693 1454 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 1455 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
hudakz 0:2cf53c219693 1456 #define RCC_CSR_SFTRSTF_Pos (28U)
hudakz 0:2cf53c219693 1457 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 1458 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
hudakz 0:2cf53c219693 1459 #define RCC_CSR_IWDGRSTF_Pos (29U)
hudakz 0:2cf53c219693 1460 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 1461 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
hudakz 0:2cf53c219693 1462 #define RCC_CSR_WWDGRSTF_Pos (30U)
hudakz 0:2cf53c219693 1463 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 1464 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
hudakz 0:2cf53c219693 1465 #define RCC_CSR_LPWRRSTF_Pos (31U)
hudakz 0:2cf53c219693 1466 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 1467 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
hudakz 0:2cf53c219693 1468
hudakz 0:2cf53c219693 1469
hudakz 0:2cf53c219693 1470
hudakz 0:2cf53c219693 1471 /******************************************************************************/
hudakz 0:2cf53c219693 1472 /* */
hudakz 0:2cf53c219693 1473 /* General Purpose and Alternate Function I/O */
hudakz 0:2cf53c219693 1474 /* */
hudakz 0:2cf53c219693 1475 /******************************************************************************/
hudakz 0:2cf53c219693 1476
hudakz 0:2cf53c219693 1477 /******************* Bit definition for GPIO_CRL register *******************/
hudakz 0:2cf53c219693 1478 #define GPIO_CRL_MODE_Pos (0U)
hudakz 0:2cf53c219693 1479 #define GPIO_CRL_MODE_Msk (0x33333333U << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
hudakz 0:2cf53c219693 1480 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
hudakz 0:2cf53c219693 1481
hudakz 0:2cf53c219693 1482 #define GPIO_CRL_MODE0_Pos (0U)
hudakz 0:2cf53c219693 1483 #define GPIO_CRL_MODE0_Msk (0x3U << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 1484 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
hudakz 0:2cf53c219693 1485 #define GPIO_CRL_MODE0_0 (0x1U << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1486 #define GPIO_CRL_MODE0_1 (0x2U << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1487
hudakz 0:2cf53c219693 1488 #define GPIO_CRL_MODE1_Pos (4U)
hudakz 0:2cf53c219693 1489 #define GPIO_CRL_MODE1_Msk (0x3U << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 1490 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
hudakz 0:2cf53c219693 1491 #define GPIO_CRL_MODE1_0 (0x1U << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1492 #define GPIO_CRL_MODE1_1 (0x2U << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1493
hudakz 0:2cf53c219693 1494 #define GPIO_CRL_MODE2_Pos (8U)
hudakz 0:2cf53c219693 1495 #define GPIO_CRL_MODE2_Msk (0x3U << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 1496 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
hudakz 0:2cf53c219693 1497 #define GPIO_CRL_MODE2_0 (0x1U << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1498 #define GPIO_CRL_MODE2_1 (0x2U << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1499
hudakz 0:2cf53c219693 1500 #define GPIO_CRL_MODE3_Pos (12U)
hudakz 0:2cf53c219693 1501 #define GPIO_CRL_MODE3_Msk (0x3U << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 1502 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
hudakz 0:2cf53c219693 1503 #define GPIO_CRL_MODE3_0 (0x1U << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1504 #define GPIO_CRL_MODE3_1 (0x2U << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1505
hudakz 0:2cf53c219693 1506 #define GPIO_CRL_MODE4_Pos (16U)
hudakz 0:2cf53c219693 1507 #define GPIO_CRL_MODE4_Msk (0x3U << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
hudakz 0:2cf53c219693 1508 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
hudakz 0:2cf53c219693 1509 #define GPIO_CRL_MODE4_0 (0x1U << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 1510 #define GPIO_CRL_MODE4_1 (0x2U << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 1511
hudakz 0:2cf53c219693 1512 #define GPIO_CRL_MODE5_Pos (20U)
hudakz 0:2cf53c219693 1513 #define GPIO_CRL_MODE5_Msk (0x3U << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
hudakz 0:2cf53c219693 1514 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
hudakz 0:2cf53c219693 1515 #define GPIO_CRL_MODE5_0 (0x1U << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 1516 #define GPIO_CRL_MODE5_1 (0x2U << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 1517
hudakz 0:2cf53c219693 1518 #define GPIO_CRL_MODE6_Pos (24U)
hudakz 0:2cf53c219693 1519 #define GPIO_CRL_MODE6_Msk (0x3U << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
hudakz 0:2cf53c219693 1520 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
hudakz 0:2cf53c219693 1521 #define GPIO_CRL_MODE6_0 (0x1U << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 1522 #define GPIO_CRL_MODE6_1 (0x2U << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 1523
hudakz 0:2cf53c219693 1524 #define GPIO_CRL_MODE7_Pos (28U)
hudakz 0:2cf53c219693 1525 #define GPIO_CRL_MODE7_Msk (0x3U << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
hudakz 0:2cf53c219693 1526 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
hudakz 0:2cf53c219693 1527 #define GPIO_CRL_MODE7_0 (0x1U << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 1528 #define GPIO_CRL_MODE7_1 (0x2U << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 1529
hudakz 0:2cf53c219693 1530 #define GPIO_CRL_CNF_Pos (2U)
hudakz 0:2cf53c219693 1531 #define GPIO_CRL_CNF_Msk (0x33333333U << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
hudakz 0:2cf53c219693 1532 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
hudakz 0:2cf53c219693 1533
hudakz 0:2cf53c219693 1534 #define GPIO_CRL_CNF0_Pos (2U)
hudakz 0:2cf53c219693 1535 #define GPIO_CRL_CNF0_Msk (0x3U << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
hudakz 0:2cf53c219693 1536 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
hudakz 0:2cf53c219693 1537 #define GPIO_CRL_CNF0_0 (0x1U << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1538 #define GPIO_CRL_CNF0_1 (0x2U << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1539
hudakz 0:2cf53c219693 1540 #define GPIO_CRL_CNF1_Pos (6U)
hudakz 0:2cf53c219693 1541 #define GPIO_CRL_CNF1_Msk (0x3U << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
hudakz 0:2cf53c219693 1542 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
hudakz 0:2cf53c219693 1543 #define GPIO_CRL_CNF1_0 (0x1U << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1544 #define GPIO_CRL_CNF1_1 (0x2U << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1545
hudakz 0:2cf53c219693 1546 #define GPIO_CRL_CNF2_Pos (10U)
hudakz 0:2cf53c219693 1547 #define GPIO_CRL_CNF2_Msk (0x3U << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
hudakz 0:2cf53c219693 1548 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
hudakz 0:2cf53c219693 1549 #define GPIO_CRL_CNF2_0 (0x1U << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1550 #define GPIO_CRL_CNF2_1 (0x2U << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1551
hudakz 0:2cf53c219693 1552 #define GPIO_CRL_CNF3_Pos (14U)
hudakz 0:2cf53c219693 1553 #define GPIO_CRL_CNF3_Msk (0x3U << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
hudakz 0:2cf53c219693 1554 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
hudakz 0:2cf53c219693 1555 #define GPIO_CRL_CNF3_0 (0x1U << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1556 #define GPIO_CRL_CNF3_1 (0x2U << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1557
hudakz 0:2cf53c219693 1558 #define GPIO_CRL_CNF4_Pos (18U)
hudakz 0:2cf53c219693 1559 #define GPIO_CRL_CNF4_Msk (0x3U << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
hudakz 0:2cf53c219693 1560 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
hudakz 0:2cf53c219693 1561 #define GPIO_CRL_CNF4_0 (0x1U << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1562 #define GPIO_CRL_CNF4_1 (0x2U << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 1563
hudakz 0:2cf53c219693 1564 #define GPIO_CRL_CNF5_Pos (22U)
hudakz 0:2cf53c219693 1565 #define GPIO_CRL_CNF5_Msk (0x3U << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
hudakz 0:2cf53c219693 1566 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
hudakz 0:2cf53c219693 1567 #define GPIO_CRL_CNF5_0 (0x1U << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 1568 #define GPIO_CRL_CNF5_1 (0x2U << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 1569
hudakz 0:2cf53c219693 1570 #define GPIO_CRL_CNF6_Pos (26U)
hudakz 0:2cf53c219693 1571 #define GPIO_CRL_CNF6_Msk (0x3U << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
hudakz 0:2cf53c219693 1572 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
hudakz 0:2cf53c219693 1573 #define GPIO_CRL_CNF6_0 (0x1U << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 1574 #define GPIO_CRL_CNF6_1 (0x2U << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 1575
hudakz 0:2cf53c219693 1576 #define GPIO_CRL_CNF7_Pos (30U)
hudakz 0:2cf53c219693 1577 #define GPIO_CRL_CNF7_Msk (0x3U << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
hudakz 0:2cf53c219693 1578 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
hudakz 0:2cf53c219693 1579 #define GPIO_CRL_CNF7_0 (0x1U << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 1580 #define GPIO_CRL_CNF7_1 (0x2U << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 1581
hudakz 0:2cf53c219693 1582 /******************* Bit definition for GPIO_CRH register *******************/
hudakz 0:2cf53c219693 1583 #define GPIO_CRH_MODE_Pos (0U)
hudakz 0:2cf53c219693 1584 #define GPIO_CRH_MODE_Msk (0x33333333U << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
hudakz 0:2cf53c219693 1585 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
hudakz 0:2cf53c219693 1586
hudakz 0:2cf53c219693 1587 #define GPIO_CRH_MODE8_Pos (0U)
hudakz 0:2cf53c219693 1588 #define GPIO_CRH_MODE8_Msk (0x3U << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 1589 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
hudakz 0:2cf53c219693 1590 #define GPIO_CRH_MODE8_0 (0x1U << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1591 #define GPIO_CRH_MODE8_1 (0x2U << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1592
hudakz 0:2cf53c219693 1593 #define GPIO_CRH_MODE9_Pos (4U)
hudakz 0:2cf53c219693 1594 #define GPIO_CRH_MODE9_Msk (0x3U << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 1595 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
hudakz 0:2cf53c219693 1596 #define GPIO_CRH_MODE9_0 (0x1U << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1597 #define GPIO_CRH_MODE9_1 (0x2U << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1598
hudakz 0:2cf53c219693 1599 #define GPIO_CRH_MODE10_Pos (8U)
hudakz 0:2cf53c219693 1600 #define GPIO_CRH_MODE10_Msk (0x3U << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 1601 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
hudakz 0:2cf53c219693 1602 #define GPIO_CRH_MODE10_0 (0x1U << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1603 #define GPIO_CRH_MODE10_1 (0x2U << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1604
hudakz 0:2cf53c219693 1605 #define GPIO_CRH_MODE11_Pos (12U)
hudakz 0:2cf53c219693 1606 #define GPIO_CRH_MODE11_Msk (0x3U << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 1607 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
hudakz 0:2cf53c219693 1608 #define GPIO_CRH_MODE11_0 (0x1U << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1609 #define GPIO_CRH_MODE11_1 (0x2U << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1610
hudakz 0:2cf53c219693 1611 #define GPIO_CRH_MODE12_Pos (16U)
hudakz 0:2cf53c219693 1612 #define GPIO_CRH_MODE12_Msk (0x3U << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
hudakz 0:2cf53c219693 1613 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
hudakz 0:2cf53c219693 1614 #define GPIO_CRH_MODE12_0 (0x1U << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 1615 #define GPIO_CRH_MODE12_1 (0x2U << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 1616
hudakz 0:2cf53c219693 1617 #define GPIO_CRH_MODE13_Pos (20U)
hudakz 0:2cf53c219693 1618 #define GPIO_CRH_MODE13_Msk (0x3U << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
hudakz 0:2cf53c219693 1619 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
hudakz 0:2cf53c219693 1620 #define GPIO_CRH_MODE13_0 (0x1U << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 1621 #define GPIO_CRH_MODE13_1 (0x2U << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 1622
hudakz 0:2cf53c219693 1623 #define GPIO_CRH_MODE14_Pos (24U)
hudakz 0:2cf53c219693 1624 #define GPIO_CRH_MODE14_Msk (0x3U << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
hudakz 0:2cf53c219693 1625 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
hudakz 0:2cf53c219693 1626 #define GPIO_CRH_MODE14_0 (0x1U << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 1627 #define GPIO_CRH_MODE14_1 (0x2U << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 1628
hudakz 0:2cf53c219693 1629 #define GPIO_CRH_MODE15_Pos (28U)
hudakz 0:2cf53c219693 1630 #define GPIO_CRH_MODE15_Msk (0x3U << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
hudakz 0:2cf53c219693 1631 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
hudakz 0:2cf53c219693 1632 #define GPIO_CRH_MODE15_0 (0x1U << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 1633 #define GPIO_CRH_MODE15_1 (0x2U << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 1634
hudakz 0:2cf53c219693 1635 #define GPIO_CRH_CNF_Pos (2U)
hudakz 0:2cf53c219693 1636 #define GPIO_CRH_CNF_Msk (0x33333333U << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
hudakz 0:2cf53c219693 1637 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
hudakz 0:2cf53c219693 1638
hudakz 0:2cf53c219693 1639 #define GPIO_CRH_CNF8_Pos (2U)
hudakz 0:2cf53c219693 1640 #define GPIO_CRH_CNF8_Msk (0x3U << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
hudakz 0:2cf53c219693 1641 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
hudakz 0:2cf53c219693 1642 #define GPIO_CRH_CNF8_0 (0x1U << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1643 #define GPIO_CRH_CNF8_1 (0x2U << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1644
hudakz 0:2cf53c219693 1645 #define GPIO_CRH_CNF9_Pos (6U)
hudakz 0:2cf53c219693 1646 #define GPIO_CRH_CNF9_Msk (0x3U << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
hudakz 0:2cf53c219693 1647 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
hudakz 0:2cf53c219693 1648 #define GPIO_CRH_CNF9_0 (0x1U << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1649 #define GPIO_CRH_CNF9_1 (0x2U << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1650
hudakz 0:2cf53c219693 1651 #define GPIO_CRH_CNF10_Pos (10U)
hudakz 0:2cf53c219693 1652 #define GPIO_CRH_CNF10_Msk (0x3U << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
hudakz 0:2cf53c219693 1653 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
hudakz 0:2cf53c219693 1654 #define GPIO_CRH_CNF10_0 (0x1U << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1655 #define GPIO_CRH_CNF10_1 (0x2U << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1656
hudakz 0:2cf53c219693 1657 #define GPIO_CRH_CNF11_Pos (14U)
hudakz 0:2cf53c219693 1658 #define GPIO_CRH_CNF11_Msk (0x3U << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
hudakz 0:2cf53c219693 1659 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
hudakz 0:2cf53c219693 1660 #define GPIO_CRH_CNF11_0 (0x1U << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1661 #define GPIO_CRH_CNF11_1 (0x2U << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1662
hudakz 0:2cf53c219693 1663 #define GPIO_CRH_CNF12_Pos (18U)
hudakz 0:2cf53c219693 1664 #define GPIO_CRH_CNF12_Msk (0x3U << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
hudakz 0:2cf53c219693 1665 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
hudakz 0:2cf53c219693 1666 #define GPIO_CRH_CNF12_0 (0x1U << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1667 #define GPIO_CRH_CNF12_1 (0x2U << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 1668
hudakz 0:2cf53c219693 1669 #define GPIO_CRH_CNF13_Pos (22U)
hudakz 0:2cf53c219693 1670 #define GPIO_CRH_CNF13_Msk (0x3U << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
hudakz 0:2cf53c219693 1671 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
hudakz 0:2cf53c219693 1672 #define GPIO_CRH_CNF13_0 (0x1U << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 1673 #define GPIO_CRH_CNF13_1 (0x2U << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 1674
hudakz 0:2cf53c219693 1675 #define GPIO_CRH_CNF14_Pos (26U)
hudakz 0:2cf53c219693 1676 #define GPIO_CRH_CNF14_Msk (0x3U << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
hudakz 0:2cf53c219693 1677 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
hudakz 0:2cf53c219693 1678 #define GPIO_CRH_CNF14_0 (0x1U << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 1679 #define GPIO_CRH_CNF14_1 (0x2U << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 1680
hudakz 0:2cf53c219693 1681 #define GPIO_CRH_CNF15_Pos (30U)
hudakz 0:2cf53c219693 1682 #define GPIO_CRH_CNF15_Msk (0x3U << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
hudakz 0:2cf53c219693 1683 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
hudakz 0:2cf53c219693 1684 #define GPIO_CRH_CNF15_0 (0x1U << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 1685 #define GPIO_CRH_CNF15_1 (0x2U << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 1686
hudakz 0:2cf53c219693 1687 /*!<****************** Bit definition for GPIO_IDR register *******************/
hudakz 0:2cf53c219693 1688 #define GPIO_IDR_IDR0_Pos (0U)
hudakz 0:2cf53c219693 1689 #define GPIO_IDR_IDR0_Msk (0x1U << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1690 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
hudakz 0:2cf53c219693 1691 #define GPIO_IDR_IDR1_Pos (1U)
hudakz 0:2cf53c219693 1692 #define GPIO_IDR_IDR1_Msk (0x1U << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1693 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
hudakz 0:2cf53c219693 1694 #define GPIO_IDR_IDR2_Pos (2U)
hudakz 0:2cf53c219693 1695 #define GPIO_IDR_IDR2_Msk (0x1U << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1696 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
hudakz 0:2cf53c219693 1697 #define GPIO_IDR_IDR3_Pos (3U)
hudakz 0:2cf53c219693 1698 #define GPIO_IDR_IDR3_Msk (0x1U << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1699 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
hudakz 0:2cf53c219693 1700 #define GPIO_IDR_IDR4_Pos (4U)
hudakz 0:2cf53c219693 1701 #define GPIO_IDR_IDR4_Msk (0x1U << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1702 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
hudakz 0:2cf53c219693 1703 #define GPIO_IDR_IDR5_Pos (5U)
hudakz 0:2cf53c219693 1704 #define GPIO_IDR_IDR5_Msk (0x1U << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1705 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
hudakz 0:2cf53c219693 1706 #define GPIO_IDR_IDR6_Pos (6U)
hudakz 0:2cf53c219693 1707 #define GPIO_IDR_IDR6_Msk (0x1U << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1708 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
hudakz 0:2cf53c219693 1709 #define GPIO_IDR_IDR7_Pos (7U)
hudakz 0:2cf53c219693 1710 #define GPIO_IDR_IDR7_Msk (0x1U << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1711 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
hudakz 0:2cf53c219693 1712 #define GPIO_IDR_IDR8_Pos (8U)
hudakz 0:2cf53c219693 1713 #define GPIO_IDR_IDR8_Msk (0x1U << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1714 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
hudakz 0:2cf53c219693 1715 #define GPIO_IDR_IDR9_Pos (9U)
hudakz 0:2cf53c219693 1716 #define GPIO_IDR_IDR9_Msk (0x1U << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1717 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
hudakz 0:2cf53c219693 1718 #define GPIO_IDR_IDR10_Pos (10U)
hudakz 0:2cf53c219693 1719 #define GPIO_IDR_IDR10_Msk (0x1U << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1720 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
hudakz 0:2cf53c219693 1721 #define GPIO_IDR_IDR11_Pos (11U)
hudakz 0:2cf53c219693 1722 #define GPIO_IDR_IDR11_Msk (0x1U << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1723 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
hudakz 0:2cf53c219693 1724 #define GPIO_IDR_IDR12_Pos (12U)
hudakz 0:2cf53c219693 1725 #define GPIO_IDR_IDR12_Msk (0x1U << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1726 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
hudakz 0:2cf53c219693 1727 #define GPIO_IDR_IDR13_Pos (13U)
hudakz 0:2cf53c219693 1728 #define GPIO_IDR_IDR13_Msk (0x1U << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1729 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
hudakz 0:2cf53c219693 1730 #define GPIO_IDR_IDR14_Pos (14U)
hudakz 0:2cf53c219693 1731 #define GPIO_IDR_IDR14_Msk (0x1U << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1732 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
hudakz 0:2cf53c219693 1733 #define GPIO_IDR_IDR15_Pos (15U)
hudakz 0:2cf53c219693 1734 #define GPIO_IDR_IDR15_Msk (0x1U << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1735 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
hudakz 0:2cf53c219693 1736
hudakz 0:2cf53c219693 1737 /******************* Bit definition for GPIO_ODR register *******************/
hudakz 0:2cf53c219693 1738 #define GPIO_ODR_ODR0_Pos (0U)
hudakz 0:2cf53c219693 1739 #define GPIO_ODR_ODR0_Msk (0x1U << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1740 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
hudakz 0:2cf53c219693 1741 #define GPIO_ODR_ODR1_Pos (1U)
hudakz 0:2cf53c219693 1742 #define GPIO_ODR_ODR1_Msk (0x1U << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1743 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
hudakz 0:2cf53c219693 1744 #define GPIO_ODR_ODR2_Pos (2U)
hudakz 0:2cf53c219693 1745 #define GPIO_ODR_ODR2_Msk (0x1U << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1746 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
hudakz 0:2cf53c219693 1747 #define GPIO_ODR_ODR3_Pos (3U)
hudakz 0:2cf53c219693 1748 #define GPIO_ODR_ODR3_Msk (0x1U << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1749 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
hudakz 0:2cf53c219693 1750 #define GPIO_ODR_ODR4_Pos (4U)
hudakz 0:2cf53c219693 1751 #define GPIO_ODR_ODR4_Msk (0x1U << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1752 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
hudakz 0:2cf53c219693 1753 #define GPIO_ODR_ODR5_Pos (5U)
hudakz 0:2cf53c219693 1754 #define GPIO_ODR_ODR5_Msk (0x1U << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1755 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
hudakz 0:2cf53c219693 1756 #define GPIO_ODR_ODR6_Pos (6U)
hudakz 0:2cf53c219693 1757 #define GPIO_ODR_ODR6_Msk (0x1U << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1758 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
hudakz 0:2cf53c219693 1759 #define GPIO_ODR_ODR7_Pos (7U)
hudakz 0:2cf53c219693 1760 #define GPIO_ODR_ODR7_Msk (0x1U << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1761 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
hudakz 0:2cf53c219693 1762 #define GPIO_ODR_ODR8_Pos (8U)
hudakz 0:2cf53c219693 1763 #define GPIO_ODR_ODR8_Msk (0x1U << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1764 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
hudakz 0:2cf53c219693 1765 #define GPIO_ODR_ODR9_Pos (9U)
hudakz 0:2cf53c219693 1766 #define GPIO_ODR_ODR9_Msk (0x1U << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1767 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
hudakz 0:2cf53c219693 1768 #define GPIO_ODR_ODR10_Pos (10U)
hudakz 0:2cf53c219693 1769 #define GPIO_ODR_ODR10_Msk (0x1U << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1770 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
hudakz 0:2cf53c219693 1771 #define GPIO_ODR_ODR11_Pos (11U)
hudakz 0:2cf53c219693 1772 #define GPIO_ODR_ODR11_Msk (0x1U << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1773 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
hudakz 0:2cf53c219693 1774 #define GPIO_ODR_ODR12_Pos (12U)
hudakz 0:2cf53c219693 1775 #define GPIO_ODR_ODR12_Msk (0x1U << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1776 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
hudakz 0:2cf53c219693 1777 #define GPIO_ODR_ODR13_Pos (13U)
hudakz 0:2cf53c219693 1778 #define GPIO_ODR_ODR13_Msk (0x1U << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1779 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
hudakz 0:2cf53c219693 1780 #define GPIO_ODR_ODR14_Pos (14U)
hudakz 0:2cf53c219693 1781 #define GPIO_ODR_ODR14_Msk (0x1U << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1782 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
hudakz 0:2cf53c219693 1783 #define GPIO_ODR_ODR15_Pos (15U)
hudakz 0:2cf53c219693 1784 #define GPIO_ODR_ODR15_Msk (0x1U << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1785 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
hudakz 0:2cf53c219693 1786
hudakz 0:2cf53c219693 1787 /****************** Bit definition for GPIO_BSRR register *******************/
hudakz 0:2cf53c219693 1788 #define GPIO_BSRR_BS0_Pos (0U)
hudakz 0:2cf53c219693 1789 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1790 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
hudakz 0:2cf53c219693 1791 #define GPIO_BSRR_BS1_Pos (1U)
hudakz 0:2cf53c219693 1792 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1793 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
hudakz 0:2cf53c219693 1794 #define GPIO_BSRR_BS2_Pos (2U)
hudakz 0:2cf53c219693 1795 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1796 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
hudakz 0:2cf53c219693 1797 #define GPIO_BSRR_BS3_Pos (3U)
hudakz 0:2cf53c219693 1798 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1799 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
hudakz 0:2cf53c219693 1800 #define GPIO_BSRR_BS4_Pos (4U)
hudakz 0:2cf53c219693 1801 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1802 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
hudakz 0:2cf53c219693 1803 #define GPIO_BSRR_BS5_Pos (5U)
hudakz 0:2cf53c219693 1804 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1805 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
hudakz 0:2cf53c219693 1806 #define GPIO_BSRR_BS6_Pos (6U)
hudakz 0:2cf53c219693 1807 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1808 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
hudakz 0:2cf53c219693 1809 #define GPIO_BSRR_BS7_Pos (7U)
hudakz 0:2cf53c219693 1810 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1811 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
hudakz 0:2cf53c219693 1812 #define GPIO_BSRR_BS8_Pos (8U)
hudakz 0:2cf53c219693 1813 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1814 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
hudakz 0:2cf53c219693 1815 #define GPIO_BSRR_BS9_Pos (9U)
hudakz 0:2cf53c219693 1816 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1817 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
hudakz 0:2cf53c219693 1818 #define GPIO_BSRR_BS10_Pos (10U)
hudakz 0:2cf53c219693 1819 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1820 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
hudakz 0:2cf53c219693 1821 #define GPIO_BSRR_BS11_Pos (11U)
hudakz 0:2cf53c219693 1822 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1823 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
hudakz 0:2cf53c219693 1824 #define GPIO_BSRR_BS12_Pos (12U)
hudakz 0:2cf53c219693 1825 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1826 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
hudakz 0:2cf53c219693 1827 #define GPIO_BSRR_BS13_Pos (13U)
hudakz 0:2cf53c219693 1828 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1829 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
hudakz 0:2cf53c219693 1830 #define GPIO_BSRR_BS14_Pos (14U)
hudakz 0:2cf53c219693 1831 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1832 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
hudakz 0:2cf53c219693 1833 #define GPIO_BSRR_BS15_Pos (15U)
hudakz 0:2cf53c219693 1834 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1835 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
hudakz 0:2cf53c219693 1836
hudakz 0:2cf53c219693 1837 #define GPIO_BSRR_BR0_Pos (16U)
hudakz 0:2cf53c219693 1838 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 1839 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
hudakz 0:2cf53c219693 1840 #define GPIO_BSRR_BR1_Pos (17U)
hudakz 0:2cf53c219693 1841 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 1842 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
hudakz 0:2cf53c219693 1843 #define GPIO_BSRR_BR2_Pos (18U)
hudakz 0:2cf53c219693 1844 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 1845 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
hudakz 0:2cf53c219693 1846 #define GPIO_BSRR_BR3_Pos (19U)
hudakz 0:2cf53c219693 1847 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 1848 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
hudakz 0:2cf53c219693 1849 #define GPIO_BSRR_BR4_Pos (20U)
hudakz 0:2cf53c219693 1850 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 1851 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
hudakz 0:2cf53c219693 1852 #define GPIO_BSRR_BR5_Pos (21U)
hudakz 0:2cf53c219693 1853 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 1854 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
hudakz 0:2cf53c219693 1855 #define GPIO_BSRR_BR6_Pos (22U)
hudakz 0:2cf53c219693 1856 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 1857 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
hudakz 0:2cf53c219693 1858 #define GPIO_BSRR_BR7_Pos (23U)
hudakz 0:2cf53c219693 1859 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 1860 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
hudakz 0:2cf53c219693 1861 #define GPIO_BSRR_BR8_Pos (24U)
hudakz 0:2cf53c219693 1862 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 1863 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
hudakz 0:2cf53c219693 1864 #define GPIO_BSRR_BR9_Pos (25U)
hudakz 0:2cf53c219693 1865 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 1866 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
hudakz 0:2cf53c219693 1867 #define GPIO_BSRR_BR10_Pos (26U)
hudakz 0:2cf53c219693 1868 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 1869 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
hudakz 0:2cf53c219693 1870 #define GPIO_BSRR_BR11_Pos (27U)
hudakz 0:2cf53c219693 1871 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 1872 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
hudakz 0:2cf53c219693 1873 #define GPIO_BSRR_BR12_Pos (28U)
hudakz 0:2cf53c219693 1874 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 1875 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
hudakz 0:2cf53c219693 1876 #define GPIO_BSRR_BR13_Pos (29U)
hudakz 0:2cf53c219693 1877 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 1878 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
hudakz 0:2cf53c219693 1879 #define GPIO_BSRR_BR14_Pos (30U)
hudakz 0:2cf53c219693 1880 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 1881 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
hudakz 0:2cf53c219693 1882 #define GPIO_BSRR_BR15_Pos (31U)
hudakz 0:2cf53c219693 1883 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 1884 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
hudakz 0:2cf53c219693 1885
hudakz 0:2cf53c219693 1886 /******************* Bit definition for GPIO_BRR register *******************/
hudakz 0:2cf53c219693 1887 #define GPIO_BRR_BR0_Pos (0U)
hudakz 0:2cf53c219693 1888 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1889 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
hudakz 0:2cf53c219693 1890 #define GPIO_BRR_BR1_Pos (1U)
hudakz 0:2cf53c219693 1891 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1892 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
hudakz 0:2cf53c219693 1893 #define GPIO_BRR_BR2_Pos (2U)
hudakz 0:2cf53c219693 1894 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1895 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
hudakz 0:2cf53c219693 1896 #define GPIO_BRR_BR3_Pos (3U)
hudakz 0:2cf53c219693 1897 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1898 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
hudakz 0:2cf53c219693 1899 #define GPIO_BRR_BR4_Pos (4U)
hudakz 0:2cf53c219693 1900 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1901 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
hudakz 0:2cf53c219693 1902 #define GPIO_BRR_BR5_Pos (5U)
hudakz 0:2cf53c219693 1903 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1904 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
hudakz 0:2cf53c219693 1905 #define GPIO_BRR_BR6_Pos (6U)
hudakz 0:2cf53c219693 1906 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1907 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
hudakz 0:2cf53c219693 1908 #define GPIO_BRR_BR7_Pos (7U)
hudakz 0:2cf53c219693 1909 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1910 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
hudakz 0:2cf53c219693 1911 #define GPIO_BRR_BR8_Pos (8U)
hudakz 0:2cf53c219693 1912 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1913 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
hudakz 0:2cf53c219693 1914 #define GPIO_BRR_BR9_Pos (9U)
hudakz 0:2cf53c219693 1915 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1916 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
hudakz 0:2cf53c219693 1917 #define GPIO_BRR_BR10_Pos (10U)
hudakz 0:2cf53c219693 1918 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1919 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
hudakz 0:2cf53c219693 1920 #define GPIO_BRR_BR11_Pos (11U)
hudakz 0:2cf53c219693 1921 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1922 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
hudakz 0:2cf53c219693 1923 #define GPIO_BRR_BR12_Pos (12U)
hudakz 0:2cf53c219693 1924 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1925 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
hudakz 0:2cf53c219693 1926 #define GPIO_BRR_BR13_Pos (13U)
hudakz 0:2cf53c219693 1927 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1928 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
hudakz 0:2cf53c219693 1929 #define GPIO_BRR_BR14_Pos (14U)
hudakz 0:2cf53c219693 1930 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1931 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
hudakz 0:2cf53c219693 1932 #define GPIO_BRR_BR15_Pos (15U)
hudakz 0:2cf53c219693 1933 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1934 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
hudakz 0:2cf53c219693 1935
hudakz 0:2cf53c219693 1936 /****************** Bit definition for GPIO_LCKR register *******************/
hudakz 0:2cf53c219693 1937 #define GPIO_LCKR_LCK0_Pos (0U)
hudakz 0:2cf53c219693 1938 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1939 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
hudakz 0:2cf53c219693 1940 #define GPIO_LCKR_LCK1_Pos (1U)
hudakz 0:2cf53c219693 1941 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1942 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
hudakz 0:2cf53c219693 1943 #define GPIO_LCKR_LCK2_Pos (2U)
hudakz 0:2cf53c219693 1944 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1945 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
hudakz 0:2cf53c219693 1946 #define GPIO_LCKR_LCK3_Pos (3U)
hudakz 0:2cf53c219693 1947 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1948 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
hudakz 0:2cf53c219693 1949 #define GPIO_LCKR_LCK4_Pos (4U)
hudakz 0:2cf53c219693 1950 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 1951 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
hudakz 0:2cf53c219693 1952 #define GPIO_LCKR_LCK5_Pos (5U)
hudakz 0:2cf53c219693 1953 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 1954 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
hudakz 0:2cf53c219693 1955 #define GPIO_LCKR_LCK6_Pos (6U)
hudakz 0:2cf53c219693 1956 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 1957 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
hudakz 0:2cf53c219693 1958 #define GPIO_LCKR_LCK7_Pos (7U)
hudakz 0:2cf53c219693 1959 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 1960 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
hudakz 0:2cf53c219693 1961 #define GPIO_LCKR_LCK8_Pos (8U)
hudakz 0:2cf53c219693 1962 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 1963 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
hudakz 0:2cf53c219693 1964 #define GPIO_LCKR_LCK9_Pos (9U)
hudakz 0:2cf53c219693 1965 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 1966 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
hudakz 0:2cf53c219693 1967 #define GPIO_LCKR_LCK10_Pos (10U)
hudakz 0:2cf53c219693 1968 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 1969 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
hudakz 0:2cf53c219693 1970 #define GPIO_LCKR_LCK11_Pos (11U)
hudakz 0:2cf53c219693 1971 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 1972 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
hudakz 0:2cf53c219693 1973 #define GPIO_LCKR_LCK12_Pos (12U)
hudakz 0:2cf53c219693 1974 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 1975 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
hudakz 0:2cf53c219693 1976 #define GPIO_LCKR_LCK13_Pos (13U)
hudakz 0:2cf53c219693 1977 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 1978 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
hudakz 0:2cf53c219693 1979 #define GPIO_LCKR_LCK14_Pos (14U)
hudakz 0:2cf53c219693 1980 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 1981 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
hudakz 0:2cf53c219693 1982 #define GPIO_LCKR_LCK15_Pos (15U)
hudakz 0:2cf53c219693 1983 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 1984 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
hudakz 0:2cf53c219693 1985 #define GPIO_LCKR_LCKK_Pos (16U)
hudakz 0:2cf53c219693 1986 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 1987 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
hudakz 0:2cf53c219693 1988
hudakz 0:2cf53c219693 1989 /*----------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 1990
hudakz 0:2cf53c219693 1991 /****************** Bit definition for AFIO_EVCR register *******************/
hudakz 0:2cf53c219693 1992 #define AFIO_EVCR_PIN_Pos (0U)
hudakz 0:2cf53c219693 1993 #define AFIO_EVCR_PIN_Msk (0xFU << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 1994 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
hudakz 0:2cf53c219693 1995 #define AFIO_EVCR_PIN_0 (0x1U << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 1996 #define AFIO_EVCR_PIN_1 (0x2U << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 1997 #define AFIO_EVCR_PIN_2 (0x4U << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 1998 #define AFIO_EVCR_PIN_3 (0x8U << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 1999
hudakz 0:2cf53c219693 2000 /*!< PIN configuration */
hudakz 0:2cf53c219693 2001 #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
hudakz 0:2cf53c219693 2002 #define AFIO_EVCR_PIN_PX1_Pos (0U)
hudakz 0:2cf53c219693 2003 #define AFIO_EVCR_PIN_PX1_Msk (0x1U << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2004 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
hudakz 0:2cf53c219693 2005 #define AFIO_EVCR_PIN_PX2_Pos (1U)
hudakz 0:2cf53c219693 2006 #define AFIO_EVCR_PIN_PX2_Msk (0x1U << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2007 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
hudakz 0:2cf53c219693 2008 #define AFIO_EVCR_PIN_PX3_Pos (0U)
hudakz 0:2cf53c219693 2009 #define AFIO_EVCR_PIN_PX3_Msk (0x3U << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 2010 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
hudakz 0:2cf53c219693 2011 #define AFIO_EVCR_PIN_PX4_Pos (2U)
hudakz 0:2cf53c219693 2012 #define AFIO_EVCR_PIN_PX4_Msk (0x1U << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2013 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
hudakz 0:2cf53c219693 2014 #define AFIO_EVCR_PIN_PX5_Pos (0U)
hudakz 0:2cf53c219693 2015 #define AFIO_EVCR_PIN_PX5_Msk (0x5U << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
hudakz 0:2cf53c219693 2016 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
hudakz 0:2cf53c219693 2017 #define AFIO_EVCR_PIN_PX6_Pos (1U)
hudakz 0:2cf53c219693 2018 #define AFIO_EVCR_PIN_PX6_Msk (0x3U << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
hudakz 0:2cf53c219693 2019 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
hudakz 0:2cf53c219693 2020 #define AFIO_EVCR_PIN_PX7_Pos (0U)
hudakz 0:2cf53c219693 2021 #define AFIO_EVCR_PIN_PX7_Msk (0x7U << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
hudakz 0:2cf53c219693 2022 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
hudakz 0:2cf53c219693 2023 #define AFIO_EVCR_PIN_PX8_Pos (3U)
hudakz 0:2cf53c219693 2024 #define AFIO_EVCR_PIN_PX8_Msk (0x1U << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 2025 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
hudakz 0:2cf53c219693 2026 #define AFIO_EVCR_PIN_PX9_Pos (0U)
hudakz 0:2cf53c219693 2027 #define AFIO_EVCR_PIN_PX9_Msk (0x9U << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
hudakz 0:2cf53c219693 2028 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
hudakz 0:2cf53c219693 2029 #define AFIO_EVCR_PIN_PX10_Pos (1U)
hudakz 0:2cf53c219693 2030 #define AFIO_EVCR_PIN_PX10_Msk (0x5U << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
hudakz 0:2cf53c219693 2031 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
hudakz 0:2cf53c219693 2032 #define AFIO_EVCR_PIN_PX11_Pos (0U)
hudakz 0:2cf53c219693 2033 #define AFIO_EVCR_PIN_PX11_Msk (0xBU << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
hudakz 0:2cf53c219693 2034 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
hudakz 0:2cf53c219693 2035 #define AFIO_EVCR_PIN_PX12_Pos (2U)
hudakz 0:2cf53c219693 2036 #define AFIO_EVCR_PIN_PX12_Msk (0x3U << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
hudakz 0:2cf53c219693 2037 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
hudakz 0:2cf53c219693 2038 #define AFIO_EVCR_PIN_PX13_Pos (0U)
hudakz 0:2cf53c219693 2039 #define AFIO_EVCR_PIN_PX13_Msk (0xDU << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
hudakz 0:2cf53c219693 2040 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
hudakz 0:2cf53c219693 2041 #define AFIO_EVCR_PIN_PX14_Pos (1U)
hudakz 0:2cf53c219693 2042 #define AFIO_EVCR_PIN_PX14_Msk (0x7U << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
hudakz 0:2cf53c219693 2043 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
hudakz 0:2cf53c219693 2044 #define AFIO_EVCR_PIN_PX15_Pos (0U)
hudakz 0:2cf53c219693 2045 #define AFIO_EVCR_PIN_PX15_Msk (0xFU << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 2046 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
hudakz 0:2cf53c219693 2047
hudakz 0:2cf53c219693 2048 #define AFIO_EVCR_PORT_Pos (4U)
hudakz 0:2cf53c219693 2049 #define AFIO_EVCR_PORT_Msk (0x7U << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
hudakz 0:2cf53c219693 2050 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
hudakz 0:2cf53c219693 2051 #define AFIO_EVCR_PORT_0 (0x1U << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2052 #define AFIO_EVCR_PORT_1 (0x2U << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2053 #define AFIO_EVCR_PORT_2 (0x4U << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2054
hudakz 0:2cf53c219693 2055 /*!< PORT configuration */
hudakz 0:2cf53c219693 2056 #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
hudakz 0:2cf53c219693 2057 #define AFIO_EVCR_PORT_PB_Pos (4U)
hudakz 0:2cf53c219693 2058 #define AFIO_EVCR_PORT_PB_Msk (0x1U << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2059 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
hudakz 0:2cf53c219693 2060 #define AFIO_EVCR_PORT_PC_Pos (5U)
hudakz 0:2cf53c219693 2061 #define AFIO_EVCR_PORT_PC_Msk (0x1U << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2062 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
hudakz 0:2cf53c219693 2063 #define AFIO_EVCR_PORT_PD_Pos (4U)
hudakz 0:2cf53c219693 2064 #define AFIO_EVCR_PORT_PD_Msk (0x3U << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 2065 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
hudakz 0:2cf53c219693 2066 #define AFIO_EVCR_PORT_PE_Pos (6U)
hudakz 0:2cf53c219693 2067 #define AFIO_EVCR_PORT_PE_Msk (0x1U << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2068 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
hudakz 0:2cf53c219693 2069
hudakz 0:2cf53c219693 2070 #define AFIO_EVCR_EVOE_Pos (7U)
hudakz 0:2cf53c219693 2071 #define AFIO_EVCR_EVOE_Msk (0x1U << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 2072 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
hudakz 0:2cf53c219693 2073
hudakz 0:2cf53c219693 2074 /****************** Bit definition for AFIO_MAPR register *******************/
hudakz 0:2cf53c219693 2075 #define AFIO_MAPR_SPI1_REMAP_Pos (0U)
hudakz 0:2cf53c219693 2076 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1U << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2077 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
hudakz 0:2cf53c219693 2078 #define AFIO_MAPR_I2C1_REMAP_Pos (1U)
hudakz 0:2cf53c219693 2079 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1U << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2080 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
hudakz 0:2cf53c219693 2081 #define AFIO_MAPR_USART1_REMAP_Pos (2U)
hudakz 0:2cf53c219693 2082 #define AFIO_MAPR_USART1_REMAP_Msk (0x1U << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2083 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
hudakz 0:2cf53c219693 2084 #define AFIO_MAPR_USART2_REMAP_Pos (3U)
hudakz 0:2cf53c219693 2085 #define AFIO_MAPR_USART2_REMAP_Msk (0x1U << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 2086 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
hudakz 0:2cf53c219693 2087
hudakz 0:2cf53c219693 2088 #define AFIO_MAPR_USART3_REMAP_Pos (4U)
hudakz 0:2cf53c219693 2089 #define AFIO_MAPR_USART3_REMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 2090 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
hudakz 0:2cf53c219693 2091 #define AFIO_MAPR_USART3_REMAP_0 (0x1U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2092 #define AFIO_MAPR_USART3_REMAP_1 (0x2U << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2093
hudakz 0:2cf53c219693 2094 /* USART3_REMAP configuration */
hudakz 0:2cf53c219693 2095 #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
hudakz 0:2cf53c219693 2096 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
hudakz 0:2cf53c219693 2097 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2098 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
hudakz 0:2cf53c219693 2099 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
hudakz 0:2cf53c219693 2100 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 2101 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
hudakz 0:2cf53c219693 2102
hudakz 0:2cf53c219693 2103 #define AFIO_MAPR_TIM1_REMAP_Pos (6U)
hudakz 0:2cf53c219693 2104 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
hudakz 0:2cf53c219693 2105 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
hudakz 0:2cf53c219693 2106 #define AFIO_MAPR_TIM1_REMAP_0 (0x1U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2107 #define AFIO_MAPR_TIM1_REMAP_1 (0x2U << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 2108
hudakz 0:2cf53c219693 2109 /*!< TIM1_REMAP configuration */
hudakz 0:2cf53c219693 2110 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
hudakz 0:2cf53c219693 2111 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
hudakz 0:2cf53c219693 2112 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2113 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
hudakz 0:2cf53c219693 2114 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
hudakz 0:2cf53c219693 2115 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
hudakz 0:2cf53c219693 2116 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
hudakz 0:2cf53c219693 2117
hudakz 0:2cf53c219693 2118 #define AFIO_MAPR_TIM2_REMAP_Pos (8U)
hudakz 0:2cf53c219693 2119 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 2120 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
hudakz 0:2cf53c219693 2121 #define AFIO_MAPR_TIM2_REMAP_0 (0x1U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2122 #define AFIO_MAPR_TIM2_REMAP_1 (0x2U << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2123
hudakz 0:2cf53c219693 2124 /*!< TIM2_REMAP configuration */
hudakz 0:2cf53c219693 2125 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
hudakz 0:2cf53c219693 2126 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
hudakz 0:2cf53c219693 2127 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2128 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
hudakz 0:2cf53c219693 2129 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
hudakz 0:2cf53c219693 2130 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1U << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2131 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
hudakz 0:2cf53c219693 2132 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
hudakz 0:2cf53c219693 2133 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 2134 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
hudakz 0:2cf53c219693 2135
hudakz 0:2cf53c219693 2136 #define AFIO_MAPR_TIM3_REMAP_Pos (10U)
hudakz 0:2cf53c219693 2137 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
hudakz 0:2cf53c219693 2138 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
hudakz 0:2cf53c219693 2139 #define AFIO_MAPR_TIM3_REMAP_0 (0x1U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2140 #define AFIO_MAPR_TIM3_REMAP_1 (0x2U << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 2141
hudakz 0:2cf53c219693 2142 /*!< TIM3_REMAP configuration */
hudakz 0:2cf53c219693 2143 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
hudakz 0:2cf53c219693 2144 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
hudakz 0:2cf53c219693 2145 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1U << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 2146 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
hudakz 0:2cf53c219693 2147 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
hudakz 0:2cf53c219693 2148 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3U << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
hudakz 0:2cf53c219693 2149 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
hudakz 0:2cf53c219693 2150
hudakz 0:2cf53c219693 2151 #define AFIO_MAPR_TIM4_REMAP_Pos (12U)
hudakz 0:2cf53c219693 2152 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1U << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2153 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
hudakz 0:2cf53c219693 2154
hudakz 0:2cf53c219693 2155 #define AFIO_MAPR_CAN_REMAP_Pos (13U)
hudakz 0:2cf53c219693 2156 #define AFIO_MAPR_CAN_REMAP_Msk (0x3U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
hudakz 0:2cf53c219693 2157 #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
hudakz 0:2cf53c219693 2158 #define AFIO_MAPR_CAN_REMAP_0 (0x1U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2159 #define AFIO_MAPR_CAN_REMAP_1 (0x2U << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2160
hudakz 0:2cf53c219693 2161 /*!< CAN_REMAP configuration */
hudakz 0:2cf53c219693 2162 #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
hudakz 0:2cf53c219693 2163 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
hudakz 0:2cf53c219693 2164 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1U << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2165 #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
hudakz 0:2cf53c219693 2166 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
hudakz 0:2cf53c219693 2167 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3U << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
hudakz 0:2cf53c219693 2168 #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
hudakz 0:2cf53c219693 2169
hudakz 0:2cf53c219693 2170 #define AFIO_MAPR_PD01_REMAP_Pos (15U)
hudakz 0:2cf53c219693 2171 #define AFIO_MAPR_PD01_REMAP_Msk (0x1U << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 2172 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
hudakz 0:2cf53c219693 2173
hudakz 0:2cf53c219693 2174 /*!< SWJ_CFG configuration */
hudakz 0:2cf53c219693 2175 #define AFIO_MAPR_SWJ_CFG_Pos (24U)
hudakz 0:2cf53c219693 2176 #define AFIO_MAPR_SWJ_CFG_Msk (0x7U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
hudakz 0:2cf53c219693 2177 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
hudakz 0:2cf53c219693 2178 #define AFIO_MAPR_SWJ_CFG_0 (0x1U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 2179 #define AFIO_MAPR_SWJ_CFG_1 (0x2U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 2180 #define AFIO_MAPR_SWJ_CFG_2 (0x4U << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 2181
hudakz 0:2cf53c219693 2182 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
hudakz 0:2cf53c219693 2183 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
hudakz 0:2cf53c219693 2184 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1U << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 2185 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
hudakz 0:2cf53c219693 2186 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
hudakz 0:2cf53c219693 2187 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 2188 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
hudakz 0:2cf53c219693 2189 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
hudakz 0:2cf53c219693 2190 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1U << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 2191 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
hudakz 0:2cf53c219693 2192
hudakz 0:2cf53c219693 2193
hudakz 0:2cf53c219693 2194 /***************** Bit definition for AFIO_EXTICR1 register *****************/
hudakz 0:2cf53c219693 2195 #define AFIO_EXTICR1_EXTI0_Pos (0U)
hudakz 0:2cf53c219693 2196 #define AFIO_EXTICR1_EXTI0_Msk (0xFU << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 2197 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
hudakz 0:2cf53c219693 2198 #define AFIO_EXTICR1_EXTI1_Pos (4U)
hudakz 0:2cf53c219693 2199 #define AFIO_EXTICR1_EXTI1_Msk (0xFU << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 2200 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
hudakz 0:2cf53c219693 2201 #define AFIO_EXTICR1_EXTI2_Pos (8U)
hudakz 0:2cf53c219693 2202 #define AFIO_EXTICR1_EXTI2_Msk (0xFU << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
hudakz 0:2cf53c219693 2203 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
hudakz 0:2cf53c219693 2204 #define AFIO_EXTICR1_EXTI3_Pos (12U)
hudakz 0:2cf53c219693 2205 #define AFIO_EXTICR1_EXTI3_Msk (0xFU << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
hudakz 0:2cf53c219693 2206 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
hudakz 0:2cf53c219693 2207
hudakz 0:2cf53c219693 2208 /*!< EXTI0 configuration */
hudakz 0:2cf53c219693 2209 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
hudakz 0:2cf53c219693 2210 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
hudakz 0:2cf53c219693 2211 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1U << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2212 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
hudakz 0:2cf53c219693 2213 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
hudakz 0:2cf53c219693 2214 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1U << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2215 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
hudakz 0:2cf53c219693 2216 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
hudakz 0:2cf53c219693 2217 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3U << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 2218 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
hudakz 0:2cf53c219693 2219 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
hudakz 0:2cf53c219693 2220 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1U << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2221 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
hudakz 0:2cf53c219693 2222 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
hudakz 0:2cf53c219693 2223 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5U << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
hudakz 0:2cf53c219693 2224 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
hudakz 0:2cf53c219693 2225 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
hudakz 0:2cf53c219693 2226 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3U << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
hudakz 0:2cf53c219693 2227 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
hudakz 0:2cf53c219693 2228
hudakz 0:2cf53c219693 2229 /*!< EXTI1 configuration */
hudakz 0:2cf53c219693 2230 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
hudakz 0:2cf53c219693 2231 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
hudakz 0:2cf53c219693 2232 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1U << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2233 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
hudakz 0:2cf53c219693 2234 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
hudakz 0:2cf53c219693 2235 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1U << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2236 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
hudakz 0:2cf53c219693 2237 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
hudakz 0:2cf53c219693 2238 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3U << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 2239 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
hudakz 0:2cf53c219693 2240 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
hudakz 0:2cf53c219693 2241 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1U << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2242 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
hudakz 0:2cf53c219693 2243 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
hudakz 0:2cf53c219693 2244 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5U << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
hudakz 0:2cf53c219693 2245 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
hudakz 0:2cf53c219693 2246 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
hudakz 0:2cf53c219693 2247 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3U << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
hudakz 0:2cf53c219693 2248 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
hudakz 0:2cf53c219693 2249
hudakz 0:2cf53c219693 2250 /*!< EXTI2 configuration */
hudakz 0:2cf53c219693 2251 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
hudakz 0:2cf53c219693 2252 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
hudakz 0:2cf53c219693 2253 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1U << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2254 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
hudakz 0:2cf53c219693 2255 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
hudakz 0:2cf53c219693 2256 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1U << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2257 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
hudakz 0:2cf53c219693 2258 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
hudakz 0:2cf53c219693 2259 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3U << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 2260 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
hudakz 0:2cf53c219693 2261 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
hudakz 0:2cf53c219693 2262 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1U << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2263 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
hudakz 0:2cf53c219693 2264 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
hudakz 0:2cf53c219693 2265 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5U << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
hudakz 0:2cf53c219693 2266 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
hudakz 0:2cf53c219693 2267 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
hudakz 0:2cf53c219693 2268 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3U << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 2269 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
hudakz 0:2cf53c219693 2270
hudakz 0:2cf53c219693 2271 /*!< EXTI3 configuration */
hudakz 0:2cf53c219693 2272 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
hudakz 0:2cf53c219693 2273 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
hudakz 0:2cf53c219693 2274 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1U << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2275 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
hudakz 0:2cf53c219693 2276 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
hudakz 0:2cf53c219693 2277 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1U << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2278 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
hudakz 0:2cf53c219693 2279 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
hudakz 0:2cf53c219693 2280 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3U << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 2281 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
hudakz 0:2cf53c219693 2282 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
hudakz 0:2cf53c219693 2283 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1U << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2284 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
hudakz 0:2cf53c219693 2285 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
hudakz 0:2cf53c219693 2286 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5U << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
hudakz 0:2cf53c219693 2287 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
hudakz 0:2cf53c219693 2288 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
hudakz 0:2cf53c219693 2289 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3U << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
hudakz 0:2cf53c219693 2290 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
hudakz 0:2cf53c219693 2291
hudakz 0:2cf53c219693 2292 /***************** Bit definition for AFIO_EXTICR2 register *****************/
hudakz 0:2cf53c219693 2293 #define AFIO_EXTICR2_EXTI4_Pos (0U)
hudakz 0:2cf53c219693 2294 #define AFIO_EXTICR2_EXTI4_Msk (0xFU << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 2295 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
hudakz 0:2cf53c219693 2296 #define AFIO_EXTICR2_EXTI5_Pos (4U)
hudakz 0:2cf53c219693 2297 #define AFIO_EXTICR2_EXTI5_Msk (0xFU << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 2298 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
hudakz 0:2cf53c219693 2299 #define AFIO_EXTICR2_EXTI6_Pos (8U)
hudakz 0:2cf53c219693 2300 #define AFIO_EXTICR2_EXTI6_Msk (0xFU << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
hudakz 0:2cf53c219693 2301 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
hudakz 0:2cf53c219693 2302 #define AFIO_EXTICR2_EXTI7_Pos (12U)
hudakz 0:2cf53c219693 2303 #define AFIO_EXTICR2_EXTI7_Msk (0xFU << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
hudakz 0:2cf53c219693 2304 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
hudakz 0:2cf53c219693 2305
hudakz 0:2cf53c219693 2306 /*!< EXTI4 configuration */
hudakz 0:2cf53c219693 2307 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
hudakz 0:2cf53c219693 2308 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
hudakz 0:2cf53c219693 2309 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1U << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2310 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
hudakz 0:2cf53c219693 2311 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
hudakz 0:2cf53c219693 2312 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1U << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2313 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
hudakz 0:2cf53c219693 2314 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
hudakz 0:2cf53c219693 2315 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3U << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 2316 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
hudakz 0:2cf53c219693 2317 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
hudakz 0:2cf53c219693 2318 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1U << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2319 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
hudakz 0:2cf53c219693 2320 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
hudakz 0:2cf53c219693 2321 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5U << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
hudakz 0:2cf53c219693 2322 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
hudakz 0:2cf53c219693 2323 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
hudakz 0:2cf53c219693 2324 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3U << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
hudakz 0:2cf53c219693 2325 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
hudakz 0:2cf53c219693 2326
hudakz 0:2cf53c219693 2327 /* EXTI5 configuration */
hudakz 0:2cf53c219693 2328 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
hudakz 0:2cf53c219693 2329 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
hudakz 0:2cf53c219693 2330 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1U << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2331 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
hudakz 0:2cf53c219693 2332 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
hudakz 0:2cf53c219693 2333 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1U << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2334 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
hudakz 0:2cf53c219693 2335 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
hudakz 0:2cf53c219693 2336 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3U << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 2337 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
hudakz 0:2cf53c219693 2338 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
hudakz 0:2cf53c219693 2339 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1U << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2340 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
hudakz 0:2cf53c219693 2341 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
hudakz 0:2cf53c219693 2342 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5U << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
hudakz 0:2cf53c219693 2343 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
hudakz 0:2cf53c219693 2344 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
hudakz 0:2cf53c219693 2345 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3U << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
hudakz 0:2cf53c219693 2346 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
hudakz 0:2cf53c219693 2347
hudakz 0:2cf53c219693 2348 /*!< EXTI6 configuration */
hudakz 0:2cf53c219693 2349 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
hudakz 0:2cf53c219693 2350 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
hudakz 0:2cf53c219693 2351 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1U << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2352 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
hudakz 0:2cf53c219693 2353 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
hudakz 0:2cf53c219693 2354 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1U << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2355 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
hudakz 0:2cf53c219693 2356 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
hudakz 0:2cf53c219693 2357 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3U << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 2358 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
hudakz 0:2cf53c219693 2359 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
hudakz 0:2cf53c219693 2360 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1U << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2361 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
hudakz 0:2cf53c219693 2362 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
hudakz 0:2cf53c219693 2363 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5U << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
hudakz 0:2cf53c219693 2364 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
hudakz 0:2cf53c219693 2365 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
hudakz 0:2cf53c219693 2366 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3U << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 2367 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
hudakz 0:2cf53c219693 2368
hudakz 0:2cf53c219693 2369 /*!< EXTI7 configuration */
hudakz 0:2cf53c219693 2370 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
hudakz 0:2cf53c219693 2371 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
hudakz 0:2cf53c219693 2372 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1U << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2373 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
hudakz 0:2cf53c219693 2374 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
hudakz 0:2cf53c219693 2375 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1U << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2376 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
hudakz 0:2cf53c219693 2377 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
hudakz 0:2cf53c219693 2378 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3U << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 2379 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
hudakz 0:2cf53c219693 2380 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
hudakz 0:2cf53c219693 2381 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1U << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2382 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
hudakz 0:2cf53c219693 2383 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
hudakz 0:2cf53c219693 2384 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5U << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
hudakz 0:2cf53c219693 2385 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
hudakz 0:2cf53c219693 2386 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
hudakz 0:2cf53c219693 2387 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3U << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
hudakz 0:2cf53c219693 2388 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
hudakz 0:2cf53c219693 2389
hudakz 0:2cf53c219693 2390 /***************** Bit definition for AFIO_EXTICR3 register *****************/
hudakz 0:2cf53c219693 2391 #define AFIO_EXTICR3_EXTI8_Pos (0U)
hudakz 0:2cf53c219693 2392 #define AFIO_EXTICR3_EXTI8_Msk (0xFU << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 2393 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
hudakz 0:2cf53c219693 2394 #define AFIO_EXTICR3_EXTI9_Pos (4U)
hudakz 0:2cf53c219693 2395 #define AFIO_EXTICR3_EXTI9_Msk (0xFU << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 2396 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
hudakz 0:2cf53c219693 2397 #define AFIO_EXTICR3_EXTI10_Pos (8U)
hudakz 0:2cf53c219693 2398 #define AFIO_EXTICR3_EXTI10_Msk (0xFU << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
hudakz 0:2cf53c219693 2399 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
hudakz 0:2cf53c219693 2400 #define AFIO_EXTICR3_EXTI11_Pos (12U)
hudakz 0:2cf53c219693 2401 #define AFIO_EXTICR3_EXTI11_Msk (0xFU << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
hudakz 0:2cf53c219693 2402 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
hudakz 0:2cf53c219693 2403
hudakz 0:2cf53c219693 2404 /*!< EXTI8 configuration */
hudakz 0:2cf53c219693 2405 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
hudakz 0:2cf53c219693 2406 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
hudakz 0:2cf53c219693 2407 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1U << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2408 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
hudakz 0:2cf53c219693 2409 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
hudakz 0:2cf53c219693 2410 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1U << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2411 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
hudakz 0:2cf53c219693 2412 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
hudakz 0:2cf53c219693 2413 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3U << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 2414 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
hudakz 0:2cf53c219693 2415 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
hudakz 0:2cf53c219693 2416 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1U << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2417 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
hudakz 0:2cf53c219693 2418 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
hudakz 0:2cf53c219693 2419 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5U << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
hudakz 0:2cf53c219693 2420 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
hudakz 0:2cf53c219693 2421 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
hudakz 0:2cf53c219693 2422 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3U << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
hudakz 0:2cf53c219693 2423 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
hudakz 0:2cf53c219693 2424
hudakz 0:2cf53c219693 2425 /*!< EXTI9 configuration */
hudakz 0:2cf53c219693 2426 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
hudakz 0:2cf53c219693 2427 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
hudakz 0:2cf53c219693 2428 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1U << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2429 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
hudakz 0:2cf53c219693 2430 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
hudakz 0:2cf53c219693 2431 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1U << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2432 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
hudakz 0:2cf53c219693 2433 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
hudakz 0:2cf53c219693 2434 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3U << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 2435 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
hudakz 0:2cf53c219693 2436 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
hudakz 0:2cf53c219693 2437 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1U << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2438 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
hudakz 0:2cf53c219693 2439 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
hudakz 0:2cf53c219693 2440 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5U << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
hudakz 0:2cf53c219693 2441 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
hudakz 0:2cf53c219693 2442 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
hudakz 0:2cf53c219693 2443 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3U << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
hudakz 0:2cf53c219693 2444 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
hudakz 0:2cf53c219693 2445
hudakz 0:2cf53c219693 2446 /*!< EXTI10 configuration */
hudakz 0:2cf53c219693 2447 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
hudakz 0:2cf53c219693 2448 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
hudakz 0:2cf53c219693 2449 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1U << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2450 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
hudakz 0:2cf53c219693 2451 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
hudakz 0:2cf53c219693 2452 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1U << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2453 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
hudakz 0:2cf53c219693 2454 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
hudakz 0:2cf53c219693 2455 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3U << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 2456 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
hudakz 0:2cf53c219693 2457 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
hudakz 0:2cf53c219693 2458 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1U << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2459 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
hudakz 0:2cf53c219693 2460 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
hudakz 0:2cf53c219693 2461 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5U << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
hudakz 0:2cf53c219693 2462 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
hudakz 0:2cf53c219693 2463 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
hudakz 0:2cf53c219693 2464 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3U << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 2465 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
hudakz 0:2cf53c219693 2466
hudakz 0:2cf53c219693 2467 /*!< EXTI11 configuration */
hudakz 0:2cf53c219693 2468 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
hudakz 0:2cf53c219693 2469 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
hudakz 0:2cf53c219693 2470 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1U << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2471 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
hudakz 0:2cf53c219693 2472 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
hudakz 0:2cf53c219693 2473 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1U << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2474 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
hudakz 0:2cf53c219693 2475 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
hudakz 0:2cf53c219693 2476 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3U << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 2477 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
hudakz 0:2cf53c219693 2478 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
hudakz 0:2cf53c219693 2479 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1U << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2480 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
hudakz 0:2cf53c219693 2481 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
hudakz 0:2cf53c219693 2482 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5U << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
hudakz 0:2cf53c219693 2483 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
hudakz 0:2cf53c219693 2484 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
hudakz 0:2cf53c219693 2485 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3U << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
hudakz 0:2cf53c219693 2486 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
hudakz 0:2cf53c219693 2487
hudakz 0:2cf53c219693 2488 /***************** Bit definition for AFIO_EXTICR4 register *****************/
hudakz 0:2cf53c219693 2489 #define AFIO_EXTICR4_EXTI12_Pos (0U)
hudakz 0:2cf53c219693 2490 #define AFIO_EXTICR4_EXTI12_Msk (0xFU << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 2491 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
hudakz 0:2cf53c219693 2492 #define AFIO_EXTICR4_EXTI13_Pos (4U)
hudakz 0:2cf53c219693 2493 #define AFIO_EXTICR4_EXTI13_Msk (0xFU << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 2494 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
hudakz 0:2cf53c219693 2495 #define AFIO_EXTICR4_EXTI14_Pos (8U)
hudakz 0:2cf53c219693 2496 #define AFIO_EXTICR4_EXTI14_Msk (0xFU << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
hudakz 0:2cf53c219693 2497 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
hudakz 0:2cf53c219693 2498 #define AFIO_EXTICR4_EXTI15_Pos (12U)
hudakz 0:2cf53c219693 2499 #define AFIO_EXTICR4_EXTI15_Msk (0xFU << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
hudakz 0:2cf53c219693 2500 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
hudakz 0:2cf53c219693 2501
hudakz 0:2cf53c219693 2502 /* EXTI12 configuration */
hudakz 0:2cf53c219693 2503 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
hudakz 0:2cf53c219693 2504 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
hudakz 0:2cf53c219693 2505 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1U << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2506 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
hudakz 0:2cf53c219693 2507 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
hudakz 0:2cf53c219693 2508 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1U << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2509 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
hudakz 0:2cf53c219693 2510 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
hudakz 0:2cf53c219693 2511 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3U << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 2512 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
hudakz 0:2cf53c219693 2513 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
hudakz 0:2cf53c219693 2514 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1U << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2515 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
hudakz 0:2cf53c219693 2516 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
hudakz 0:2cf53c219693 2517 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5U << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
hudakz 0:2cf53c219693 2518 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
hudakz 0:2cf53c219693 2519 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
hudakz 0:2cf53c219693 2520 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3U << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
hudakz 0:2cf53c219693 2521 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
hudakz 0:2cf53c219693 2522
hudakz 0:2cf53c219693 2523 /* EXTI13 configuration */
hudakz 0:2cf53c219693 2524 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
hudakz 0:2cf53c219693 2525 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
hudakz 0:2cf53c219693 2526 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1U << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2527 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
hudakz 0:2cf53c219693 2528 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
hudakz 0:2cf53c219693 2529 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1U << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2530 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
hudakz 0:2cf53c219693 2531 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
hudakz 0:2cf53c219693 2532 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3U << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 2533 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
hudakz 0:2cf53c219693 2534 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
hudakz 0:2cf53c219693 2535 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1U << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2536 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
hudakz 0:2cf53c219693 2537 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
hudakz 0:2cf53c219693 2538 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5U << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
hudakz 0:2cf53c219693 2539 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
hudakz 0:2cf53c219693 2540 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
hudakz 0:2cf53c219693 2541 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3U << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
hudakz 0:2cf53c219693 2542 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
hudakz 0:2cf53c219693 2543
hudakz 0:2cf53c219693 2544 /*!< EXTI14 configuration */
hudakz 0:2cf53c219693 2545 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
hudakz 0:2cf53c219693 2546 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
hudakz 0:2cf53c219693 2547 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1U << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2548 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
hudakz 0:2cf53c219693 2549 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
hudakz 0:2cf53c219693 2550 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1U << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2551 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
hudakz 0:2cf53c219693 2552 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
hudakz 0:2cf53c219693 2553 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3U << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 2554 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
hudakz 0:2cf53c219693 2555 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
hudakz 0:2cf53c219693 2556 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1U << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2557 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
hudakz 0:2cf53c219693 2558 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
hudakz 0:2cf53c219693 2559 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5U << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
hudakz 0:2cf53c219693 2560 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
hudakz 0:2cf53c219693 2561 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
hudakz 0:2cf53c219693 2562 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3U << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 2563 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
hudakz 0:2cf53c219693 2564
hudakz 0:2cf53c219693 2565 /*!< EXTI15 configuration */
hudakz 0:2cf53c219693 2566 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
hudakz 0:2cf53c219693 2567 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
hudakz 0:2cf53c219693 2568 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1U << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2569 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
hudakz 0:2cf53c219693 2570 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
hudakz 0:2cf53c219693 2571 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1U << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2572 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
hudakz 0:2cf53c219693 2573 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
hudakz 0:2cf53c219693 2574 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3U << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 2575 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
hudakz 0:2cf53c219693 2576 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
hudakz 0:2cf53c219693 2577 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1U << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2578 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
hudakz 0:2cf53c219693 2579 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
hudakz 0:2cf53c219693 2580 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5U << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
hudakz 0:2cf53c219693 2581 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
hudakz 0:2cf53c219693 2582 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
hudakz 0:2cf53c219693 2583 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3U << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
hudakz 0:2cf53c219693 2584 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
hudakz 0:2cf53c219693 2585
hudakz 0:2cf53c219693 2586 /****************** Bit definition for AFIO_MAPR2 register ******************/
hudakz 0:2cf53c219693 2587
hudakz 0:2cf53c219693 2588
hudakz 0:2cf53c219693 2589
hudakz 0:2cf53c219693 2590 /******************************************************************************/
hudakz 0:2cf53c219693 2591 /* */
hudakz 0:2cf53c219693 2592 /* External Interrupt/Event Controller */
hudakz 0:2cf53c219693 2593 /* */
hudakz 0:2cf53c219693 2594 /******************************************************************************/
hudakz 0:2cf53c219693 2595
hudakz 0:2cf53c219693 2596 /******************* Bit definition for EXTI_IMR register *******************/
hudakz 0:2cf53c219693 2597 #define EXTI_IMR_MR0_Pos (0U)
hudakz 0:2cf53c219693 2598 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2599 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
hudakz 0:2cf53c219693 2600 #define EXTI_IMR_MR1_Pos (1U)
hudakz 0:2cf53c219693 2601 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2602 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
hudakz 0:2cf53c219693 2603 #define EXTI_IMR_MR2_Pos (2U)
hudakz 0:2cf53c219693 2604 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2605 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
hudakz 0:2cf53c219693 2606 #define EXTI_IMR_MR3_Pos (3U)
hudakz 0:2cf53c219693 2607 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 2608 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
hudakz 0:2cf53c219693 2609 #define EXTI_IMR_MR4_Pos (4U)
hudakz 0:2cf53c219693 2610 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2611 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
hudakz 0:2cf53c219693 2612 #define EXTI_IMR_MR5_Pos (5U)
hudakz 0:2cf53c219693 2613 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2614 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
hudakz 0:2cf53c219693 2615 #define EXTI_IMR_MR6_Pos (6U)
hudakz 0:2cf53c219693 2616 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2617 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
hudakz 0:2cf53c219693 2618 #define EXTI_IMR_MR7_Pos (7U)
hudakz 0:2cf53c219693 2619 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 2620 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
hudakz 0:2cf53c219693 2621 #define EXTI_IMR_MR8_Pos (8U)
hudakz 0:2cf53c219693 2622 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2623 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
hudakz 0:2cf53c219693 2624 #define EXTI_IMR_MR9_Pos (9U)
hudakz 0:2cf53c219693 2625 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2626 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
hudakz 0:2cf53c219693 2627 #define EXTI_IMR_MR10_Pos (10U)
hudakz 0:2cf53c219693 2628 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2629 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
hudakz 0:2cf53c219693 2630 #define EXTI_IMR_MR11_Pos (11U)
hudakz 0:2cf53c219693 2631 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 2632 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
hudakz 0:2cf53c219693 2633 #define EXTI_IMR_MR12_Pos (12U)
hudakz 0:2cf53c219693 2634 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2635 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
hudakz 0:2cf53c219693 2636 #define EXTI_IMR_MR13_Pos (13U)
hudakz 0:2cf53c219693 2637 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2638 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
hudakz 0:2cf53c219693 2639 #define EXTI_IMR_MR14_Pos (14U)
hudakz 0:2cf53c219693 2640 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2641 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
hudakz 0:2cf53c219693 2642 #define EXTI_IMR_MR15_Pos (15U)
hudakz 0:2cf53c219693 2643 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 2644 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
hudakz 0:2cf53c219693 2645 #define EXTI_IMR_MR16_Pos (16U)
hudakz 0:2cf53c219693 2646 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 2647 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
hudakz 0:2cf53c219693 2648 #define EXTI_IMR_MR17_Pos (17U)
hudakz 0:2cf53c219693 2649 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 2650 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
hudakz 0:2cf53c219693 2651 #define EXTI_IMR_MR18_Pos (18U)
hudakz 0:2cf53c219693 2652 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 2653 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
hudakz 0:2cf53c219693 2654
hudakz 0:2cf53c219693 2655 /* References Defines */
hudakz 0:2cf53c219693 2656 #define EXTI_IMR_IM0 EXTI_IMR_MR0
hudakz 0:2cf53c219693 2657 #define EXTI_IMR_IM1 EXTI_IMR_MR1
hudakz 0:2cf53c219693 2658 #define EXTI_IMR_IM2 EXTI_IMR_MR2
hudakz 0:2cf53c219693 2659 #define EXTI_IMR_IM3 EXTI_IMR_MR3
hudakz 0:2cf53c219693 2660 #define EXTI_IMR_IM4 EXTI_IMR_MR4
hudakz 0:2cf53c219693 2661 #define EXTI_IMR_IM5 EXTI_IMR_MR5
hudakz 0:2cf53c219693 2662 #define EXTI_IMR_IM6 EXTI_IMR_MR6
hudakz 0:2cf53c219693 2663 #define EXTI_IMR_IM7 EXTI_IMR_MR7
hudakz 0:2cf53c219693 2664 #define EXTI_IMR_IM8 EXTI_IMR_MR8
hudakz 0:2cf53c219693 2665 #define EXTI_IMR_IM9 EXTI_IMR_MR9
hudakz 0:2cf53c219693 2666 #define EXTI_IMR_IM10 EXTI_IMR_MR10
hudakz 0:2cf53c219693 2667 #define EXTI_IMR_IM11 EXTI_IMR_MR11
hudakz 0:2cf53c219693 2668 #define EXTI_IMR_IM12 EXTI_IMR_MR12
hudakz 0:2cf53c219693 2669 #define EXTI_IMR_IM13 EXTI_IMR_MR13
hudakz 0:2cf53c219693 2670 #define EXTI_IMR_IM14 EXTI_IMR_MR14
hudakz 0:2cf53c219693 2671 #define EXTI_IMR_IM15 EXTI_IMR_MR15
hudakz 0:2cf53c219693 2672 #define EXTI_IMR_IM16 EXTI_IMR_MR16
hudakz 0:2cf53c219693 2673 #define EXTI_IMR_IM17 EXTI_IMR_MR17
hudakz 0:2cf53c219693 2674 #define EXTI_IMR_IM18 EXTI_IMR_MR18
hudakz 0:2cf53c219693 2675 #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
hudakz 0:2cf53c219693 2676
hudakz 0:2cf53c219693 2677 /******************* Bit definition for EXTI_EMR register *******************/
hudakz 0:2cf53c219693 2678 #define EXTI_EMR_MR0_Pos (0U)
hudakz 0:2cf53c219693 2679 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2680 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
hudakz 0:2cf53c219693 2681 #define EXTI_EMR_MR1_Pos (1U)
hudakz 0:2cf53c219693 2682 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2683 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
hudakz 0:2cf53c219693 2684 #define EXTI_EMR_MR2_Pos (2U)
hudakz 0:2cf53c219693 2685 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2686 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
hudakz 0:2cf53c219693 2687 #define EXTI_EMR_MR3_Pos (3U)
hudakz 0:2cf53c219693 2688 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 2689 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
hudakz 0:2cf53c219693 2690 #define EXTI_EMR_MR4_Pos (4U)
hudakz 0:2cf53c219693 2691 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2692 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
hudakz 0:2cf53c219693 2693 #define EXTI_EMR_MR5_Pos (5U)
hudakz 0:2cf53c219693 2694 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2695 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
hudakz 0:2cf53c219693 2696 #define EXTI_EMR_MR6_Pos (6U)
hudakz 0:2cf53c219693 2697 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2698 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
hudakz 0:2cf53c219693 2699 #define EXTI_EMR_MR7_Pos (7U)
hudakz 0:2cf53c219693 2700 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 2701 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
hudakz 0:2cf53c219693 2702 #define EXTI_EMR_MR8_Pos (8U)
hudakz 0:2cf53c219693 2703 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2704 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
hudakz 0:2cf53c219693 2705 #define EXTI_EMR_MR9_Pos (9U)
hudakz 0:2cf53c219693 2706 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2707 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
hudakz 0:2cf53c219693 2708 #define EXTI_EMR_MR10_Pos (10U)
hudakz 0:2cf53c219693 2709 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2710 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
hudakz 0:2cf53c219693 2711 #define EXTI_EMR_MR11_Pos (11U)
hudakz 0:2cf53c219693 2712 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 2713 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
hudakz 0:2cf53c219693 2714 #define EXTI_EMR_MR12_Pos (12U)
hudakz 0:2cf53c219693 2715 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2716 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
hudakz 0:2cf53c219693 2717 #define EXTI_EMR_MR13_Pos (13U)
hudakz 0:2cf53c219693 2718 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2719 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
hudakz 0:2cf53c219693 2720 #define EXTI_EMR_MR14_Pos (14U)
hudakz 0:2cf53c219693 2721 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2722 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
hudakz 0:2cf53c219693 2723 #define EXTI_EMR_MR15_Pos (15U)
hudakz 0:2cf53c219693 2724 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 2725 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
hudakz 0:2cf53c219693 2726 #define EXTI_EMR_MR16_Pos (16U)
hudakz 0:2cf53c219693 2727 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 2728 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
hudakz 0:2cf53c219693 2729 #define EXTI_EMR_MR17_Pos (17U)
hudakz 0:2cf53c219693 2730 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 2731 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
hudakz 0:2cf53c219693 2732 #define EXTI_EMR_MR18_Pos (18U)
hudakz 0:2cf53c219693 2733 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 2734 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
hudakz 0:2cf53c219693 2735
hudakz 0:2cf53c219693 2736 /* References Defines */
hudakz 0:2cf53c219693 2737 #define EXTI_EMR_EM0 EXTI_EMR_MR0
hudakz 0:2cf53c219693 2738 #define EXTI_EMR_EM1 EXTI_EMR_MR1
hudakz 0:2cf53c219693 2739 #define EXTI_EMR_EM2 EXTI_EMR_MR2
hudakz 0:2cf53c219693 2740 #define EXTI_EMR_EM3 EXTI_EMR_MR3
hudakz 0:2cf53c219693 2741 #define EXTI_EMR_EM4 EXTI_EMR_MR4
hudakz 0:2cf53c219693 2742 #define EXTI_EMR_EM5 EXTI_EMR_MR5
hudakz 0:2cf53c219693 2743 #define EXTI_EMR_EM6 EXTI_EMR_MR6
hudakz 0:2cf53c219693 2744 #define EXTI_EMR_EM7 EXTI_EMR_MR7
hudakz 0:2cf53c219693 2745 #define EXTI_EMR_EM8 EXTI_EMR_MR8
hudakz 0:2cf53c219693 2746 #define EXTI_EMR_EM9 EXTI_EMR_MR9
hudakz 0:2cf53c219693 2747 #define EXTI_EMR_EM10 EXTI_EMR_MR10
hudakz 0:2cf53c219693 2748 #define EXTI_EMR_EM11 EXTI_EMR_MR11
hudakz 0:2cf53c219693 2749 #define EXTI_EMR_EM12 EXTI_EMR_MR12
hudakz 0:2cf53c219693 2750 #define EXTI_EMR_EM13 EXTI_EMR_MR13
hudakz 0:2cf53c219693 2751 #define EXTI_EMR_EM14 EXTI_EMR_MR14
hudakz 0:2cf53c219693 2752 #define EXTI_EMR_EM15 EXTI_EMR_MR15
hudakz 0:2cf53c219693 2753 #define EXTI_EMR_EM16 EXTI_EMR_MR16
hudakz 0:2cf53c219693 2754 #define EXTI_EMR_EM17 EXTI_EMR_MR17
hudakz 0:2cf53c219693 2755 #define EXTI_EMR_EM18 EXTI_EMR_MR18
hudakz 0:2cf53c219693 2756
hudakz 0:2cf53c219693 2757 /****************** Bit definition for EXTI_RTSR register *******************/
hudakz 0:2cf53c219693 2758 #define EXTI_RTSR_TR0_Pos (0U)
hudakz 0:2cf53c219693 2759 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2760 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
hudakz 0:2cf53c219693 2761 #define EXTI_RTSR_TR1_Pos (1U)
hudakz 0:2cf53c219693 2762 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2763 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
hudakz 0:2cf53c219693 2764 #define EXTI_RTSR_TR2_Pos (2U)
hudakz 0:2cf53c219693 2765 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2766 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
hudakz 0:2cf53c219693 2767 #define EXTI_RTSR_TR3_Pos (3U)
hudakz 0:2cf53c219693 2768 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 2769 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
hudakz 0:2cf53c219693 2770 #define EXTI_RTSR_TR4_Pos (4U)
hudakz 0:2cf53c219693 2771 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2772 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
hudakz 0:2cf53c219693 2773 #define EXTI_RTSR_TR5_Pos (5U)
hudakz 0:2cf53c219693 2774 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2775 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
hudakz 0:2cf53c219693 2776 #define EXTI_RTSR_TR6_Pos (6U)
hudakz 0:2cf53c219693 2777 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2778 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
hudakz 0:2cf53c219693 2779 #define EXTI_RTSR_TR7_Pos (7U)
hudakz 0:2cf53c219693 2780 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 2781 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
hudakz 0:2cf53c219693 2782 #define EXTI_RTSR_TR8_Pos (8U)
hudakz 0:2cf53c219693 2783 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2784 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
hudakz 0:2cf53c219693 2785 #define EXTI_RTSR_TR9_Pos (9U)
hudakz 0:2cf53c219693 2786 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2787 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
hudakz 0:2cf53c219693 2788 #define EXTI_RTSR_TR10_Pos (10U)
hudakz 0:2cf53c219693 2789 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2790 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
hudakz 0:2cf53c219693 2791 #define EXTI_RTSR_TR11_Pos (11U)
hudakz 0:2cf53c219693 2792 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 2793 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
hudakz 0:2cf53c219693 2794 #define EXTI_RTSR_TR12_Pos (12U)
hudakz 0:2cf53c219693 2795 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2796 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
hudakz 0:2cf53c219693 2797 #define EXTI_RTSR_TR13_Pos (13U)
hudakz 0:2cf53c219693 2798 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2799 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
hudakz 0:2cf53c219693 2800 #define EXTI_RTSR_TR14_Pos (14U)
hudakz 0:2cf53c219693 2801 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2802 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
hudakz 0:2cf53c219693 2803 #define EXTI_RTSR_TR15_Pos (15U)
hudakz 0:2cf53c219693 2804 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 2805 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
hudakz 0:2cf53c219693 2806 #define EXTI_RTSR_TR16_Pos (16U)
hudakz 0:2cf53c219693 2807 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 2808 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
hudakz 0:2cf53c219693 2809 #define EXTI_RTSR_TR17_Pos (17U)
hudakz 0:2cf53c219693 2810 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 2811 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
hudakz 0:2cf53c219693 2812 #define EXTI_RTSR_TR18_Pos (18U)
hudakz 0:2cf53c219693 2813 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 2814 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
hudakz 0:2cf53c219693 2815
hudakz 0:2cf53c219693 2816 /* References Defines */
hudakz 0:2cf53c219693 2817 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
hudakz 0:2cf53c219693 2818 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
hudakz 0:2cf53c219693 2819 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
hudakz 0:2cf53c219693 2820 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
hudakz 0:2cf53c219693 2821 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
hudakz 0:2cf53c219693 2822 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
hudakz 0:2cf53c219693 2823 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
hudakz 0:2cf53c219693 2824 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
hudakz 0:2cf53c219693 2825 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
hudakz 0:2cf53c219693 2826 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
hudakz 0:2cf53c219693 2827 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
hudakz 0:2cf53c219693 2828 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
hudakz 0:2cf53c219693 2829 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
hudakz 0:2cf53c219693 2830 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
hudakz 0:2cf53c219693 2831 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
hudakz 0:2cf53c219693 2832 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
hudakz 0:2cf53c219693 2833 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
hudakz 0:2cf53c219693 2834 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
hudakz 0:2cf53c219693 2835 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
hudakz 0:2cf53c219693 2836
hudakz 0:2cf53c219693 2837 /****************** Bit definition for EXTI_FTSR register *******************/
hudakz 0:2cf53c219693 2838 #define EXTI_FTSR_TR0_Pos (0U)
hudakz 0:2cf53c219693 2839 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2840 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
hudakz 0:2cf53c219693 2841 #define EXTI_FTSR_TR1_Pos (1U)
hudakz 0:2cf53c219693 2842 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2843 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
hudakz 0:2cf53c219693 2844 #define EXTI_FTSR_TR2_Pos (2U)
hudakz 0:2cf53c219693 2845 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2846 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
hudakz 0:2cf53c219693 2847 #define EXTI_FTSR_TR3_Pos (3U)
hudakz 0:2cf53c219693 2848 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 2849 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
hudakz 0:2cf53c219693 2850 #define EXTI_FTSR_TR4_Pos (4U)
hudakz 0:2cf53c219693 2851 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2852 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
hudakz 0:2cf53c219693 2853 #define EXTI_FTSR_TR5_Pos (5U)
hudakz 0:2cf53c219693 2854 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2855 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
hudakz 0:2cf53c219693 2856 #define EXTI_FTSR_TR6_Pos (6U)
hudakz 0:2cf53c219693 2857 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2858 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
hudakz 0:2cf53c219693 2859 #define EXTI_FTSR_TR7_Pos (7U)
hudakz 0:2cf53c219693 2860 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 2861 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
hudakz 0:2cf53c219693 2862 #define EXTI_FTSR_TR8_Pos (8U)
hudakz 0:2cf53c219693 2863 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2864 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
hudakz 0:2cf53c219693 2865 #define EXTI_FTSR_TR9_Pos (9U)
hudakz 0:2cf53c219693 2866 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2867 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
hudakz 0:2cf53c219693 2868 #define EXTI_FTSR_TR10_Pos (10U)
hudakz 0:2cf53c219693 2869 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2870 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
hudakz 0:2cf53c219693 2871 #define EXTI_FTSR_TR11_Pos (11U)
hudakz 0:2cf53c219693 2872 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 2873 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
hudakz 0:2cf53c219693 2874 #define EXTI_FTSR_TR12_Pos (12U)
hudakz 0:2cf53c219693 2875 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2876 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
hudakz 0:2cf53c219693 2877 #define EXTI_FTSR_TR13_Pos (13U)
hudakz 0:2cf53c219693 2878 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2879 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
hudakz 0:2cf53c219693 2880 #define EXTI_FTSR_TR14_Pos (14U)
hudakz 0:2cf53c219693 2881 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2882 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
hudakz 0:2cf53c219693 2883 #define EXTI_FTSR_TR15_Pos (15U)
hudakz 0:2cf53c219693 2884 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 2885 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
hudakz 0:2cf53c219693 2886 #define EXTI_FTSR_TR16_Pos (16U)
hudakz 0:2cf53c219693 2887 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 2888 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
hudakz 0:2cf53c219693 2889 #define EXTI_FTSR_TR17_Pos (17U)
hudakz 0:2cf53c219693 2890 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 2891 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
hudakz 0:2cf53c219693 2892 #define EXTI_FTSR_TR18_Pos (18U)
hudakz 0:2cf53c219693 2893 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 2894 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
hudakz 0:2cf53c219693 2895
hudakz 0:2cf53c219693 2896 /* References Defines */
hudakz 0:2cf53c219693 2897 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
hudakz 0:2cf53c219693 2898 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
hudakz 0:2cf53c219693 2899 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
hudakz 0:2cf53c219693 2900 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
hudakz 0:2cf53c219693 2901 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
hudakz 0:2cf53c219693 2902 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
hudakz 0:2cf53c219693 2903 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
hudakz 0:2cf53c219693 2904 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
hudakz 0:2cf53c219693 2905 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
hudakz 0:2cf53c219693 2906 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
hudakz 0:2cf53c219693 2907 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
hudakz 0:2cf53c219693 2908 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
hudakz 0:2cf53c219693 2909 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
hudakz 0:2cf53c219693 2910 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
hudakz 0:2cf53c219693 2911 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
hudakz 0:2cf53c219693 2912 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
hudakz 0:2cf53c219693 2913 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
hudakz 0:2cf53c219693 2914 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
hudakz 0:2cf53c219693 2915 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
hudakz 0:2cf53c219693 2916
hudakz 0:2cf53c219693 2917 /****************** Bit definition for EXTI_SWIER register ******************/
hudakz 0:2cf53c219693 2918 #define EXTI_SWIER_SWIER0_Pos (0U)
hudakz 0:2cf53c219693 2919 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 2920 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
hudakz 0:2cf53c219693 2921 #define EXTI_SWIER_SWIER1_Pos (1U)
hudakz 0:2cf53c219693 2922 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 2923 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
hudakz 0:2cf53c219693 2924 #define EXTI_SWIER_SWIER2_Pos (2U)
hudakz 0:2cf53c219693 2925 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 2926 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
hudakz 0:2cf53c219693 2927 #define EXTI_SWIER_SWIER3_Pos (3U)
hudakz 0:2cf53c219693 2928 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 2929 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
hudakz 0:2cf53c219693 2930 #define EXTI_SWIER_SWIER4_Pos (4U)
hudakz 0:2cf53c219693 2931 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 2932 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
hudakz 0:2cf53c219693 2933 #define EXTI_SWIER_SWIER5_Pos (5U)
hudakz 0:2cf53c219693 2934 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 2935 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
hudakz 0:2cf53c219693 2936 #define EXTI_SWIER_SWIER6_Pos (6U)
hudakz 0:2cf53c219693 2937 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 2938 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
hudakz 0:2cf53c219693 2939 #define EXTI_SWIER_SWIER7_Pos (7U)
hudakz 0:2cf53c219693 2940 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 2941 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
hudakz 0:2cf53c219693 2942 #define EXTI_SWIER_SWIER8_Pos (8U)
hudakz 0:2cf53c219693 2943 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 2944 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
hudakz 0:2cf53c219693 2945 #define EXTI_SWIER_SWIER9_Pos (9U)
hudakz 0:2cf53c219693 2946 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 2947 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
hudakz 0:2cf53c219693 2948 #define EXTI_SWIER_SWIER10_Pos (10U)
hudakz 0:2cf53c219693 2949 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 2950 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
hudakz 0:2cf53c219693 2951 #define EXTI_SWIER_SWIER11_Pos (11U)
hudakz 0:2cf53c219693 2952 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 2953 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
hudakz 0:2cf53c219693 2954 #define EXTI_SWIER_SWIER12_Pos (12U)
hudakz 0:2cf53c219693 2955 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 2956 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
hudakz 0:2cf53c219693 2957 #define EXTI_SWIER_SWIER13_Pos (13U)
hudakz 0:2cf53c219693 2958 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 2959 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
hudakz 0:2cf53c219693 2960 #define EXTI_SWIER_SWIER14_Pos (14U)
hudakz 0:2cf53c219693 2961 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 2962 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
hudakz 0:2cf53c219693 2963 #define EXTI_SWIER_SWIER15_Pos (15U)
hudakz 0:2cf53c219693 2964 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 2965 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
hudakz 0:2cf53c219693 2966 #define EXTI_SWIER_SWIER16_Pos (16U)
hudakz 0:2cf53c219693 2967 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 2968 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
hudakz 0:2cf53c219693 2969 #define EXTI_SWIER_SWIER17_Pos (17U)
hudakz 0:2cf53c219693 2970 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 2971 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
hudakz 0:2cf53c219693 2972 #define EXTI_SWIER_SWIER18_Pos (18U)
hudakz 0:2cf53c219693 2973 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 2974 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
hudakz 0:2cf53c219693 2975
hudakz 0:2cf53c219693 2976 /* References Defines */
hudakz 0:2cf53c219693 2977 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
hudakz 0:2cf53c219693 2978 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
hudakz 0:2cf53c219693 2979 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
hudakz 0:2cf53c219693 2980 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
hudakz 0:2cf53c219693 2981 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
hudakz 0:2cf53c219693 2982 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
hudakz 0:2cf53c219693 2983 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
hudakz 0:2cf53c219693 2984 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
hudakz 0:2cf53c219693 2985 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
hudakz 0:2cf53c219693 2986 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
hudakz 0:2cf53c219693 2987 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
hudakz 0:2cf53c219693 2988 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
hudakz 0:2cf53c219693 2989 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
hudakz 0:2cf53c219693 2990 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
hudakz 0:2cf53c219693 2991 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
hudakz 0:2cf53c219693 2992 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
hudakz 0:2cf53c219693 2993 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
hudakz 0:2cf53c219693 2994 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
hudakz 0:2cf53c219693 2995 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
hudakz 0:2cf53c219693 2996
hudakz 0:2cf53c219693 2997 /******************* Bit definition for EXTI_PR register ********************/
hudakz 0:2cf53c219693 2998 #define EXTI_PR_PR0_Pos (0U)
hudakz 0:2cf53c219693 2999 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3000 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
hudakz 0:2cf53c219693 3001 #define EXTI_PR_PR1_Pos (1U)
hudakz 0:2cf53c219693 3002 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3003 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
hudakz 0:2cf53c219693 3004 #define EXTI_PR_PR2_Pos (2U)
hudakz 0:2cf53c219693 3005 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3006 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
hudakz 0:2cf53c219693 3007 #define EXTI_PR_PR3_Pos (3U)
hudakz 0:2cf53c219693 3008 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3009 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
hudakz 0:2cf53c219693 3010 #define EXTI_PR_PR4_Pos (4U)
hudakz 0:2cf53c219693 3011 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3012 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
hudakz 0:2cf53c219693 3013 #define EXTI_PR_PR5_Pos (5U)
hudakz 0:2cf53c219693 3014 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3015 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
hudakz 0:2cf53c219693 3016 #define EXTI_PR_PR6_Pos (6U)
hudakz 0:2cf53c219693 3017 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3018 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
hudakz 0:2cf53c219693 3019 #define EXTI_PR_PR7_Pos (7U)
hudakz 0:2cf53c219693 3020 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3021 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
hudakz 0:2cf53c219693 3022 #define EXTI_PR_PR8_Pos (8U)
hudakz 0:2cf53c219693 3023 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3024 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
hudakz 0:2cf53c219693 3025 #define EXTI_PR_PR9_Pos (9U)
hudakz 0:2cf53c219693 3026 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3027 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
hudakz 0:2cf53c219693 3028 #define EXTI_PR_PR10_Pos (10U)
hudakz 0:2cf53c219693 3029 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3030 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
hudakz 0:2cf53c219693 3031 #define EXTI_PR_PR11_Pos (11U)
hudakz 0:2cf53c219693 3032 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3033 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
hudakz 0:2cf53c219693 3034 #define EXTI_PR_PR12_Pos (12U)
hudakz 0:2cf53c219693 3035 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3036 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
hudakz 0:2cf53c219693 3037 #define EXTI_PR_PR13_Pos (13U)
hudakz 0:2cf53c219693 3038 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3039 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
hudakz 0:2cf53c219693 3040 #define EXTI_PR_PR14_Pos (14U)
hudakz 0:2cf53c219693 3041 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3042 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
hudakz 0:2cf53c219693 3043 #define EXTI_PR_PR15_Pos (15U)
hudakz 0:2cf53c219693 3044 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3045 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
hudakz 0:2cf53c219693 3046 #define EXTI_PR_PR16_Pos (16U)
hudakz 0:2cf53c219693 3047 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3048 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
hudakz 0:2cf53c219693 3049 #define EXTI_PR_PR17_Pos (17U)
hudakz 0:2cf53c219693 3050 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3051 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
hudakz 0:2cf53c219693 3052 #define EXTI_PR_PR18_Pos (18U)
hudakz 0:2cf53c219693 3053 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3054 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
hudakz 0:2cf53c219693 3055
hudakz 0:2cf53c219693 3056 /* References Defines */
hudakz 0:2cf53c219693 3057 #define EXTI_PR_PIF0 EXTI_PR_PR0
hudakz 0:2cf53c219693 3058 #define EXTI_PR_PIF1 EXTI_PR_PR1
hudakz 0:2cf53c219693 3059 #define EXTI_PR_PIF2 EXTI_PR_PR2
hudakz 0:2cf53c219693 3060 #define EXTI_PR_PIF3 EXTI_PR_PR3
hudakz 0:2cf53c219693 3061 #define EXTI_PR_PIF4 EXTI_PR_PR4
hudakz 0:2cf53c219693 3062 #define EXTI_PR_PIF5 EXTI_PR_PR5
hudakz 0:2cf53c219693 3063 #define EXTI_PR_PIF6 EXTI_PR_PR6
hudakz 0:2cf53c219693 3064 #define EXTI_PR_PIF7 EXTI_PR_PR7
hudakz 0:2cf53c219693 3065 #define EXTI_PR_PIF8 EXTI_PR_PR8
hudakz 0:2cf53c219693 3066 #define EXTI_PR_PIF9 EXTI_PR_PR9
hudakz 0:2cf53c219693 3067 #define EXTI_PR_PIF10 EXTI_PR_PR10
hudakz 0:2cf53c219693 3068 #define EXTI_PR_PIF11 EXTI_PR_PR11
hudakz 0:2cf53c219693 3069 #define EXTI_PR_PIF12 EXTI_PR_PR12
hudakz 0:2cf53c219693 3070 #define EXTI_PR_PIF13 EXTI_PR_PR13
hudakz 0:2cf53c219693 3071 #define EXTI_PR_PIF14 EXTI_PR_PR14
hudakz 0:2cf53c219693 3072 #define EXTI_PR_PIF15 EXTI_PR_PR15
hudakz 0:2cf53c219693 3073 #define EXTI_PR_PIF16 EXTI_PR_PR16
hudakz 0:2cf53c219693 3074 #define EXTI_PR_PIF17 EXTI_PR_PR17
hudakz 0:2cf53c219693 3075 #define EXTI_PR_PIF18 EXTI_PR_PR18
hudakz 0:2cf53c219693 3076
hudakz 0:2cf53c219693 3077 /******************************************************************************/
hudakz 0:2cf53c219693 3078 /* */
hudakz 0:2cf53c219693 3079 /* DMA Controller */
hudakz 0:2cf53c219693 3080 /* */
hudakz 0:2cf53c219693 3081 /******************************************************************************/
hudakz 0:2cf53c219693 3082
hudakz 0:2cf53c219693 3083 /******************* Bit definition for DMA_ISR register ********************/
hudakz 0:2cf53c219693 3084 #define DMA_ISR_GIF1_Pos (0U)
hudakz 0:2cf53c219693 3085 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3086 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
hudakz 0:2cf53c219693 3087 #define DMA_ISR_TCIF1_Pos (1U)
hudakz 0:2cf53c219693 3088 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3089 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
hudakz 0:2cf53c219693 3090 #define DMA_ISR_HTIF1_Pos (2U)
hudakz 0:2cf53c219693 3091 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3092 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
hudakz 0:2cf53c219693 3093 #define DMA_ISR_TEIF1_Pos (3U)
hudakz 0:2cf53c219693 3094 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3095 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
hudakz 0:2cf53c219693 3096 #define DMA_ISR_GIF2_Pos (4U)
hudakz 0:2cf53c219693 3097 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3098 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
hudakz 0:2cf53c219693 3099 #define DMA_ISR_TCIF2_Pos (5U)
hudakz 0:2cf53c219693 3100 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3101 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
hudakz 0:2cf53c219693 3102 #define DMA_ISR_HTIF2_Pos (6U)
hudakz 0:2cf53c219693 3103 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3104 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
hudakz 0:2cf53c219693 3105 #define DMA_ISR_TEIF2_Pos (7U)
hudakz 0:2cf53c219693 3106 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3107 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
hudakz 0:2cf53c219693 3108 #define DMA_ISR_GIF3_Pos (8U)
hudakz 0:2cf53c219693 3109 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3110 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
hudakz 0:2cf53c219693 3111 #define DMA_ISR_TCIF3_Pos (9U)
hudakz 0:2cf53c219693 3112 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3113 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
hudakz 0:2cf53c219693 3114 #define DMA_ISR_HTIF3_Pos (10U)
hudakz 0:2cf53c219693 3115 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3116 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
hudakz 0:2cf53c219693 3117 #define DMA_ISR_TEIF3_Pos (11U)
hudakz 0:2cf53c219693 3118 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3119 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
hudakz 0:2cf53c219693 3120 #define DMA_ISR_GIF4_Pos (12U)
hudakz 0:2cf53c219693 3121 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3122 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
hudakz 0:2cf53c219693 3123 #define DMA_ISR_TCIF4_Pos (13U)
hudakz 0:2cf53c219693 3124 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3125 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
hudakz 0:2cf53c219693 3126 #define DMA_ISR_HTIF4_Pos (14U)
hudakz 0:2cf53c219693 3127 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3128 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
hudakz 0:2cf53c219693 3129 #define DMA_ISR_TEIF4_Pos (15U)
hudakz 0:2cf53c219693 3130 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3131 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
hudakz 0:2cf53c219693 3132 #define DMA_ISR_GIF5_Pos (16U)
hudakz 0:2cf53c219693 3133 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3134 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
hudakz 0:2cf53c219693 3135 #define DMA_ISR_TCIF5_Pos (17U)
hudakz 0:2cf53c219693 3136 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3137 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
hudakz 0:2cf53c219693 3138 #define DMA_ISR_HTIF5_Pos (18U)
hudakz 0:2cf53c219693 3139 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3140 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
hudakz 0:2cf53c219693 3141 #define DMA_ISR_TEIF5_Pos (19U)
hudakz 0:2cf53c219693 3142 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3143 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
hudakz 0:2cf53c219693 3144 #define DMA_ISR_GIF6_Pos (20U)
hudakz 0:2cf53c219693 3145 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3146 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
hudakz 0:2cf53c219693 3147 #define DMA_ISR_TCIF6_Pos (21U)
hudakz 0:2cf53c219693 3148 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3149 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
hudakz 0:2cf53c219693 3150 #define DMA_ISR_HTIF6_Pos (22U)
hudakz 0:2cf53c219693 3151 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3152 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
hudakz 0:2cf53c219693 3153 #define DMA_ISR_TEIF6_Pos (23U)
hudakz 0:2cf53c219693 3154 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3155 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
hudakz 0:2cf53c219693 3156 #define DMA_ISR_GIF7_Pos (24U)
hudakz 0:2cf53c219693 3157 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 3158 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
hudakz 0:2cf53c219693 3159 #define DMA_ISR_TCIF7_Pos (25U)
hudakz 0:2cf53c219693 3160 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 3161 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
hudakz 0:2cf53c219693 3162 #define DMA_ISR_HTIF7_Pos (26U)
hudakz 0:2cf53c219693 3163 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 3164 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
hudakz 0:2cf53c219693 3165 #define DMA_ISR_TEIF7_Pos (27U)
hudakz 0:2cf53c219693 3166 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 3167 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
hudakz 0:2cf53c219693 3168
hudakz 0:2cf53c219693 3169 /******************* Bit definition for DMA_IFCR register *******************/
hudakz 0:2cf53c219693 3170 #define DMA_IFCR_CGIF1_Pos (0U)
hudakz 0:2cf53c219693 3171 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3172 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
hudakz 0:2cf53c219693 3173 #define DMA_IFCR_CTCIF1_Pos (1U)
hudakz 0:2cf53c219693 3174 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3175 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
hudakz 0:2cf53c219693 3176 #define DMA_IFCR_CHTIF1_Pos (2U)
hudakz 0:2cf53c219693 3177 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3178 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
hudakz 0:2cf53c219693 3179 #define DMA_IFCR_CTEIF1_Pos (3U)
hudakz 0:2cf53c219693 3180 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3181 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
hudakz 0:2cf53c219693 3182 #define DMA_IFCR_CGIF2_Pos (4U)
hudakz 0:2cf53c219693 3183 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3184 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
hudakz 0:2cf53c219693 3185 #define DMA_IFCR_CTCIF2_Pos (5U)
hudakz 0:2cf53c219693 3186 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3187 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
hudakz 0:2cf53c219693 3188 #define DMA_IFCR_CHTIF2_Pos (6U)
hudakz 0:2cf53c219693 3189 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3190 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
hudakz 0:2cf53c219693 3191 #define DMA_IFCR_CTEIF2_Pos (7U)
hudakz 0:2cf53c219693 3192 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3193 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
hudakz 0:2cf53c219693 3194 #define DMA_IFCR_CGIF3_Pos (8U)
hudakz 0:2cf53c219693 3195 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3196 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
hudakz 0:2cf53c219693 3197 #define DMA_IFCR_CTCIF3_Pos (9U)
hudakz 0:2cf53c219693 3198 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3199 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
hudakz 0:2cf53c219693 3200 #define DMA_IFCR_CHTIF3_Pos (10U)
hudakz 0:2cf53c219693 3201 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3202 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
hudakz 0:2cf53c219693 3203 #define DMA_IFCR_CTEIF3_Pos (11U)
hudakz 0:2cf53c219693 3204 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3205 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
hudakz 0:2cf53c219693 3206 #define DMA_IFCR_CGIF4_Pos (12U)
hudakz 0:2cf53c219693 3207 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3208 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
hudakz 0:2cf53c219693 3209 #define DMA_IFCR_CTCIF4_Pos (13U)
hudakz 0:2cf53c219693 3210 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3211 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
hudakz 0:2cf53c219693 3212 #define DMA_IFCR_CHTIF4_Pos (14U)
hudakz 0:2cf53c219693 3213 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3214 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
hudakz 0:2cf53c219693 3215 #define DMA_IFCR_CTEIF4_Pos (15U)
hudakz 0:2cf53c219693 3216 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3217 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
hudakz 0:2cf53c219693 3218 #define DMA_IFCR_CGIF5_Pos (16U)
hudakz 0:2cf53c219693 3219 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3220 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
hudakz 0:2cf53c219693 3221 #define DMA_IFCR_CTCIF5_Pos (17U)
hudakz 0:2cf53c219693 3222 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3223 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
hudakz 0:2cf53c219693 3224 #define DMA_IFCR_CHTIF5_Pos (18U)
hudakz 0:2cf53c219693 3225 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3226 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
hudakz 0:2cf53c219693 3227 #define DMA_IFCR_CTEIF5_Pos (19U)
hudakz 0:2cf53c219693 3228 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3229 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
hudakz 0:2cf53c219693 3230 #define DMA_IFCR_CGIF6_Pos (20U)
hudakz 0:2cf53c219693 3231 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3232 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
hudakz 0:2cf53c219693 3233 #define DMA_IFCR_CTCIF6_Pos (21U)
hudakz 0:2cf53c219693 3234 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3235 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
hudakz 0:2cf53c219693 3236 #define DMA_IFCR_CHTIF6_Pos (22U)
hudakz 0:2cf53c219693 3237 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3238 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
hudakz 0:2cf53c219693 3239 #define DMA_IFCR_CTEIF6_Pos (23U)
hudakz 0:2cf53c219693 3240 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3241 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
hudakz 0:2cf53c219693 3242 #define DMA_IFCR_CGIF7_Pos (24U)
hudakz 0:2cf53c219693 3243 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 3244 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
hudakz 0:2cf53c219693 3245 #define DMA_IFCR_CTCIF7_Pos (25U)
hudakz 0:2cf53c219693 3246 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 3247 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
hudakz 0:2cf53c219693 3248 #define DMA_IFCR_CHTIF7_Pos (26U)
hudakz 0:2cf53c219693 3249 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 3250 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
hudakz 0:2cf53c219693 3251 #define DMA_IFCR_CTEIF7_Pos (27U)
hudakz 0:2cf53c219693 3252 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 3253 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
hudakz 0:2cf53c219693 3254
hudakz 0:2cf53c219693 3255 /******************* Bit definition for DMA_CCR register *******************/
hudakz 0:2cf53c219693 3256 #define DMA_CCR_EN_Pos (0U)
hudakz 0:2cf53c219693 3257 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3258 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
hudakz 0:2cf53c219693 3259 #define DMA_CCR_TCIE_Pos (1U)
hudakz 0:2cf53c219693 3260 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3261 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
hudakz 0:2cf53c219693 3262 #define DMA_CCR_HTIE_Pos (2U)
hudakz 0:2cf53c219693 3263 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3264 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
hudakz 0:2cf53c219693 3265 #define DMA_CCR_TEIE_Pos (3U)
hudakz 0:2cf53c219693 3266 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3267 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
hudakz 0:2cf53c219693 3268 #define DMA_CCR_DIR_Pos (4U)
hudakz 0:2cf53c219693 3269 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3270 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
hudakz 0:2cf53c219693 3271 #define DMA_CCR_CIRC_Pos (5U)
hudakz 0:2cf53c219693 3272 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3273 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
hudakz 0:2cf53c219693 3274 #define DMA_CCR_PINC_Pos (6U)
hudakz 0:2cf53c219693 3275 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3276 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
hudakz 0:2cf53c219693 3277 #define DMA_CCR_MINC_Pos (7U)
hudakz 0:2cf53c219693 3278 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3279 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
hudakz 0:2cf53c219693 3280
hudakz 0:2cf53c219693 3281 #define DMA_CCR_PSIZE_Pos (8U)
hudakz 0:2cf53c219693 3282 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 3283 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
hudakz 0:2cf53c219693 3284 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3285 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3286
hudakz 0:2cf53c219693 3287 #define DMA_CCR_MSIZE_Pos (10U)
hudakz 0:2cf53c219693 3288 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
hudakz 0:2cf53c219693 3289 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
hudakz 0:2cf53c219693 3290 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3291 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3292
hudakz 0:2cf53c219693 3293 #define DMA_CCR_PL_Pos (12U)
hudakz 0:2cf53c219693 3294 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 3295 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
hudakz 0:2cf53c219693 3296 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3297 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3298
hudakz 0:2cf53c219693 3299 #define DMA_CCR_MEM2MEM_Pos (14U)
hudakz 0:2cf53c219693 3300 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3301 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
hudakz 0:2cf53c219693 3302
hudakz 0:2cf53c219693 3303 /****************** Bit definition for DMA_CNDTR register ******************/
hudakz 0:2cf53c219693 3304 #define DMA_CNDTR_NDT_Pos (0U)
hudakz 0:2cf53c219693 3305 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 3306 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
hudakz 0:2cf53c219693 3307
hudakz 0:2cf53c219693 3308 /****************** Bit definition for DMA_CPAR register *******************/
hudakz 0:2cf53c219693 3309 #define DMA_CPAR_PA_Pos (0U)
hudakz 0:2cf53c219693 3310 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 3311 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
hudakz 0:2cf53c219693 3312
hudakz 0:2cf53c219693 3313 /****************** Bit definition for DMA_CMAR register *******************/
hudakz 0:2cf53c219693 3314 #define DMA_CMAR_MA_Pos (0U)
hudakz 0:2cf53c219693 3315 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 3316 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
hudakz 0:2cf53c219693 3317
hudakz 0:2cf53c219693 3318 /******************************************************************************/
hudakz 0:2cf53c219693 3319 /* */
hudakz 0:2cf53c219693 3320 /* Analog to Digital Converter (ADC) */
hudakz 0:2cf53c219693 3321 /* */
hudakz 0:2cf53c219693 3322 /******************************************************************************/
hudakz 0:2cf53c219693 3323
hudakz 0:2cf53c219693 3324 /*
hudakz 0:2cf53c219693 3325 * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
hudakz 0:2cf53c219693 3326 */
hudakz 0:2cf53c219693 3327 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
hudakz 0:2cf53c219693 3328
hudakz 0:2cf53c219693 3329 /******************** Bit definition for ADC_SR register ********************/
hudakz 0:2cf53c219693 3330 #define ADC_SR_AWD_Pos (0U)
hudakz 0:2cf53c219693 3331 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3332 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
hudakz 0:2cf53c219693 3333 #define ADC_SR_EOS_Pos (1U)
hudakz 0:2cf53c219693 3334 #define ADC_SR_EOS_Msk (0x1U << ADC_SR_EOS_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3335 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
hudakz 0:2cf53c219693 3336 #define ADC_SR_JEOS_Pos (2U)
hudakz 0:2cf53c219693 3337 #define ADC_SR_JEOS_Msk (0x1U << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3338 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
hudakz 0:2cf53c219693 3339 #define ADC_SR_JSTRT_Pos (3U)
hudakz 0:2cf53c219693 3340 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3341 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
hudakz 0:2cf53c219693 3342 #define ADC_SR_STRT_Pos (4U)
hudakz 0:2cf53c219693 3343 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3344 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
hudakz 0:2cf53c219693 3345
hudakz 0:2cf53c219693 3346 /* Legacy defines */
hudakz 0:2cf53c219693 3347 #define ADC_SR_EOC (ADC_SR_EOS)
hudakz 0:2cf53c219693 3348 #define ADC_SR_JEOC (ADC_SR_JEOS)
hudakz 0:2cf53c219693 3349
hudakz 0:2cf53c219693 3350 /******************* Bit definition for ADC_CR1 register ********************/
hudakz 0:2cf53c219693 3351 #define ADC_CR1_AWDCH_Pos (0U)
hudakz 0:2cf53c219693 3352 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
hudakz 0:2cf53c219693 3353 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
hudakz 0:2cf53c219693 3354 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3355 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3356 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3357 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3358 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3359
hudakz 0:2cf53c219693 3360 #define ADC_CR1_EOSIE_Pos (5U)
hudakz 0:2cf53c219693 3361 #define ADC_CR1_EOSIE_Msk (0x1U << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3362 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
hudakz 0:2cf53c219693 3363 #define ADC_CR1_AWDIE_Pos (6U)
hudakz 0:2cf53c219693 3364 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3365 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
hudakz 0:2cf53c219693 3366 #define ADC_CR1_JEOSIE_Pos (7U)
hudakz 0:2cf53c219693 3367 #define ADC_CR1_JEOSIE_Msk (0x1U << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3368 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
hudakz 0:2cf53c219693 3369 #define ADC_CR1_SCAN_Pos (8U)
hudakz 0:2cf53c219693 3370 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3371 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
hudakz 0:2cf53c219693 3372 #define ADC_CR1_AWDSGL_Pos (9U)
hudakz 0:2cf53c219693 3373 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3374 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
hudakz 0:2cf53c219693 3375 #define ADC_CR1_JAUTO_Pos (10U)
hudakz 0:2cf53c219693 3376 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3377 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
hudakz 0:2cf53c219693 3378 #define ADC_CR1_DISCEN_Pos (11U)
hudakz 0:2cf53c219693 3379 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3380 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
hudakz 0:2cf53c219693 3381 #define ADC_CR1_JDISCEN_Pos (12U)
hudakz 0:2cf53c219693 3382 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3383 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
hudakz 0:2cf53c219693 3384
hudakz 0:2cf53c219693 3385 #define ADC_CR1_DISCNUM_Pos (13U)
hudakz 0:2cf53c219693 3386 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
hudakz 0:2cf53c219693 3387 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
hudakz 0:2cf53c219693 3388 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3389 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3390 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3391
hudakz 0:2cf53c219693 3392 #define ADC_CR1_DUALMOD_Pos (16U)
hudakz 0:2cf53c219693 3393 #define ADC_CR1_DUALMOD_Msk (0xFU << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
hudakz 0:2cf53c219693 3394 #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
hudakz 0:2cf53c219693 3395 #define ADC_CR1_DUALMOD_0 (0x1U << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3396 #define ADC_CR1_DUALMOD_1 (0x2U << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3397 #define ADC_CR1_DUALMOD_2 (0x4U << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3398 #define ADC_CR1_DUALMOD_3 (0x8U << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3399
hudakz 0:2cf53c219693 3400 #define ADC_CR1_JAWDEN_Pos (22U)
hudakz 0:2cf53c219693 3401 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3402 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
hudakz 0:2cf53c219693 3403 #define ADC_CR1_AWDEN_Pos (23U)
hudakz 0:2cf53c219693 3404 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3405 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
hudakz 0:2cf53c219693 3406
hudakz 0:2cf53c219693 3407 /* Legacy defines */
hudakz 0:2cf53c219693 3408 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
hudakz 0:2cf53c219693 3409 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
hudakz 0:2cf53c219693 3410
hudakz 0:2cf53c219693 3411 /******************* Bit definition for ADC_CR2 register ********************/
hudakz 0:2cf53c219693 3412 #define ADC_CR2_ADON_Pos (0U)
hudakz 0:2cf53c219693 3413 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3414 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
hudakz 0:2cf53c219693 3415 #define ADC_CR2_CONT_Pos (1U)
hudakz 0:2cf53c219693 3416 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3417 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
hudakz 0:2cf53c219693 3418 #define ADC_CR2_CAL_Pos (2U)
hudakz 0:2cf53c219693 3419 #define ADC_CR2_CAL_Msk (0x1U << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3420 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
hudakz 0:2cf53c219693 3421 #define ADC_CR2_RSTCAL_Pos (3U)
hudakz 0:2cf53c219693 3422 #define ADC_CR2_RSTCAL_Msk (0x1U << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3423 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
hudakz 0:2cf53c219693 3424 #define ADC_CR2_DMA_Pos (8U)
hudakz 0:2cf53c219693 3425 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3426 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
hudakz 0:2cf53c219693 3427 #define ADC_CR2_ALIGN_Pos (11U)
hudakz 0:2cf53c219693 3428 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3429 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
hudakz 0:2cf53c219693 3430
hudakz 0:2cf53c219693 3431 #define ADC_CR2_JEXTSEL_Pos (12U)
hudakz 0:2cf53c219693 3432 #define ADC_CR2_JEXTSEL_Msk (0x7U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
hudakz 0:2cf53c219693 3433 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
hudakz 0:2cf53c219693 3434 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3435 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3436 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3437
hudakz 0:2cf53c219693 3438 #define ADC_CR2_JEXTTRIG_Pos (15U)
hudakz 0:2cf53c219693 3439 #define ADC_CR2_JEXTTRIG_Msk (0x1U << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3440 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
hudakz 0:2cf53c219693 3441
hudakz 0:2cf53c219693 3442 #define ADC_CR2_EXTSEL_Pos (17U)
hudakz 0:2cf53c219693 3443 #define ADC_CR2_EXTSEL_Msk (0x7U << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
hudakz 0:2cf53c219693 3444 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
hudakz 0:2cf53c219693 3445 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3446 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3447 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3448
hudakz 0:2cf53c219693 3449 #define ADC_CR2_EXTTRIG_Pos (20U)
hudakz 0:2cf53c219693 3450 #define ADC_CR2_EXTTRIG_Msk (0x1U << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3451 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
hudakz 0:2cf53c219693 3452 #define ADC_CR2_JSWSTART_Pos (21U)
hudakz 0:2cf53c219693 3453 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3454 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
hudakz 0:2cf53c219693 3455 #define ADC_CR2_SWSTART_Pos (22U)
hudakz 0:2cf53c219693 3456 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3457 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
hudakz 0:2cf53c219693 3458 #define ADC_CR2_TSVREFE_Pos (23U)
hudakz 0:2cf53c219693 3459 #define ADC_CR2_TSVREFE_Msk (0x1U << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3460 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
hudakz 0:2cf53c219693 3461
hudakz 0:2cf53c219693 3462 /****************** Bit definition for ADC_SMPR1 register *******************/
hudakz 0:2cf53c219693 3463 #define ADC_SMPR1_SMP10_Pos (0U)
hudakz 0:2cf53c219693 3464 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
hudakz 0:2cf53c219693 3465 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
hudakz 0:2cf53c219693 3466 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3467 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3468 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3469
hudakz 0:2cf53c219693 3470 #define ADC_SMPR1_SMP11_Pos (3U)
hudakz 0:2cf53c219693 3471 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
hudakz 0:2cf53c219693 3472 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
hudakz 0:2cf53c219693 3473 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3474 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3475 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3476
hudakz 0:2cf53c219693 3477 #define ADC_SMPR1_SMP12_Pos (6U)
hudakz 0:2cf53c219693 3478 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
hudakz 0:2cf53c219693 3479 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
hudakz 0:2cf53c219693 3480 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3481 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3482 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3483
hudakz 0:2cf53c219693 3484 #define ADC_SMPR1_SMP13_Pos (9U)
hudakz 0:2cf53c219693 3485 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
hudakz 0:2cf53c219693 3486 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
hudakz 0:2cf53c219693 3487 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3488 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3489 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3490
hudakz 0:2cf53c219693 3491 #define ADC_SMPR1_SMP14_Pos (12U)
hudakz 0:2cf53c219693 3492 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
hudakz 0:2cf53c219693 3493 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
hudakz 0:2cf53c219693 3494 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3495 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3496 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3497
hudakz 0:2cf53c219693 3498 #define ADC_SMPR1_SMP15_Pos (15U)
hudakz 0:2cf53c219693 3499 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
hudakz 0:2cf53c219693 3500 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
hudakz 0:2cf53c219693 3501 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3502 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3503 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3504
hudakz 0:2cf53c219693 3505 #define ADC_SMPR1_SMP16_Pos (18U)
hudakz 0:2cf53c219693 3506 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
hudakz 0:2cf53c219693 3507 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
hudakz 0:2cf53c219693 3508 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3509 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3510 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3511
hudakz 0:2cf53c219693 3512 #define ADC_SMPR1_SMP17_Pos (21U)
hudakz 0:2cf53c219693 3513 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
hudakz 0:2cf53c219693 3514 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
hudakz 0:2cf53c219693 3515 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3516 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3517 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3518
hudakz 0:2cf53c219693 3519 /****************** Bit definition for ADC_SMPR2 register *******************/
hudakz 0:2cf53c219693 3520 #define ADC_SMPR2_SMP0_Pos (0U)
hudakz 0:2cf53c219693 3521 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
hudakz 0:2cf53c219693 3522 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
hudakz 0:2cf53c219693 3523 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3524 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3525 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3526
hudakz 0:2cf53c219693 3527 #define ADC_SMPR2_SMP1_Pos (3U)
hudakz 0:2cf53c219693 3528 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
hudakz 0:2cf53c219693 3529 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
hudakz 0:2cf53c219693 3530 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3531 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3532 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3533
hudakz 0:2cf53c219693 3534 #define ADC_SMPR2_SMP2_Pos (6U)
hudakz 0:2cf53c219693 3535 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
hudakz 0:2cf53c219693 3536 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
hudakz 0:2cf53c219693 3537 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3538 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3539 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3540
hudakz 0:2cf53c219693 3541 #define ADC_SMPR2_SMP3_Pos (9U)
hudakz 0:2cf53c219693 3542 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
hudakz 0:2cf53c219693 3543 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
hudakz 0:2cf53c219693 3544 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3545 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3546 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3547
hudakz 0:2cf53c219693 3548 #define ADC_SMPR2_SMP4_Pos (12U)
hudakz 0:2cf53c219693 3549 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
hudakz 0:2cf53c219693 3550 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
hudakz 0:2cf53c219693 3551 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3552 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3553 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3554
hudakz 0:2cf53c219693 3555 #define ADC_SMPR2_SMP5_Pos (15U)
hudakz 0:2cf53c219693 3556 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
hudakz 0:2cf53c219693 3557 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
hudakz 0:2cf53c219693 3558 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3559 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3560 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3561
hudakz 0:2cf53c219693 3562 #define ADC_SMPR2_SMP6_Pos (18U)
hudakz 0:2cf53c219693 3563 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
hudakz 0:2cf53c219693 3564 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
hudakz 0:2cf53c219693 3565 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3566 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3567 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3568
hudakz 0:2cf53c219693 3569 #define ADC_SMPR2_SMP7_Pos (21U)
hudakz 0:2cf53c219693 3570 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
hudakz 0:2cf53c219693 3571 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
hudakz 0:2cf53c219693 3572 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3573 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3574 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3575
hudakz 0:2cf53c219693 3576 #define ADC_SMPR2_SMP8_Pos (24U)
hudakz 0:2cf53c219693 3577 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
hudakz 0:2cf53c219693 3578 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
hudakz 0:2cf53c219693 3579 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 3580 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 3581 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 3582
hudakz 0:2cf53c219693 3583 #define ADC_SMPR2_SMP9_Pos (27U)
hudakz 0:2cf53c219693 3584 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
hudakz 0:2cf53c219693 3585 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
hudakz 0:2cf53c219693 3586 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 3587 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 3588 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 3589
hudakz 0:2cf53c219693 3590 /****************** Bit definition for ADC_JOFR1 register *******************/
hudakz 0:2cf53c219693 3591 #define ADC_JOFR1_JOFFSET1_Pos (0U)
hudakz 0:2cf53c219693 3592 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 3593 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
hudakz 0:2cf53c219693 3594
hudakz 0:2cf53c219693 3595 /****************** Bit definition for ADC_JOFR2 register *******************/
hudakz 0:2cf53c219693 3596 #define ADC_JOFR2_JOFFSET2_Pos (0U)
hudakz 0:2cf53c219693 3597 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 3598 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
hudakz 0:2cf53c219693 3599
hudakz 0:2cf53c219693 3600 /****************** Bit definition for ADC_JOFR3 register *******************/
hudakz 0:2cf53c219693 3601 #define ADC_JOFR3_JOFFSET3_Pos (0U)
hudakz 0:2cf53c219693 3602 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 3603 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
hudakz 0:2cf53c219693 3604
hudakz 0:2cf53c219693 3605 /****************** Bit definition for ADC_JOFR4 register *******************/
hudakz 0:2cf53c219693 3606 #define ADC_JOFR4_JOFFSET4_Pos (0U)
hudakz 0:2cf53c219693 3607 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 3608 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
hudakz 0:2cf53c219693 3609
hudakz 0:2cf53c219693 3610 /******************* Bit definition for ADC_HTR register ********************/
hudakz 0:2cf53c219693 3611 #define ADC_HTR_HT_Pos (0U)
hudakz 0:2cf53c219693 3612 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 3613 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
hudakz 0:2cf53c219693 3614
hudakz 0:2cf53c219693 3615 /******************* Bit definition for ADC_LTR register ********************/
hudakz 0:2cf53c219693 3616 #define ADC_LTR_LT_Pos (0U)
hudakz 0:2cf53c219693 3617 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 3618 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
hudakz 0:2cf53c219693 3619
hudakz 0:2cf53c219693 3620 /******************* Bit definition for ADC_SQR1 register *******************/
hudakz 0:2cf53c219693 3621 #define ADC_SQR1_SQ13_Pos (0U)
hudakz 0:2cf53c219693 3622 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
hudakz 0:2cf53c219693 3623 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
hudakz 0:2cf53c219693 3624 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3625 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3626 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3627 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3628 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3629
hudakz 0:2cf53c219693 3630 #define ADC_SQR1_SQ14_Pos (5U)
hudakz 0:2cf53c219693 3631 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
hudakz 0:2cf53c219693 3632 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
hudakz 0:2cf53c219693 3633 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3634 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3635 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3636 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3637 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3638
hudakz 0:2cf53c219693 3639 #define ADC_SQR1_SQ15_Pos (10U)
hudakz 0:2cf53c219693 3640 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 3641 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
hudakz 0:2cf53c219693 3642 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3643 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3644 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3645 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3646 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3647
hudakz 0:2cf53c219693 3648 #define ADC_SQR1_SQ16_Pos (15U)
hudakz 0:2cf53c219693 3649 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
hudakz 0:2cf53c219693 3650 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
hudakz 0:2cf53c219693 3651 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3652 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3653 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3654 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3655 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3656
hudakz 0:2cf53c219693 3657 #define ADC_SQR1_L_Pos (20U)
hudakz 0:2cf53c219693 3658 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
hudakz 0:2cf53c219693 3659 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
hudakz 0:2cf53c219693 3660 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3661 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3662 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3663 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3664
hudakz 0:2cf53c219693 3665 /******************* Bit definition for ADC_SQR2 register *******************/
hudakz 0:2cf53c219693 3666 #define ADC_SQR2_SQ7_Pos (0U)
hudakz 0:2cf53c219693 3667 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
hudakz 0:2cf53c219693 3668 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
hudakz 0:2cf53c219693 3669 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3670 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3671 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3672 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3673 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3674
hudakz 0:2cf53c219693 3675 #define ADC_SQR2_SQ8_Pos (5U)
hudakz 0:2cf53c219693 3676 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
hudakz 0:2cf53c219693 3677 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
hudakz 0:2cf53c219693 3678 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3679 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3680 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3681 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3682 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3683
hudakz 0:2cf53c219693 3684 #define ADC_SQR2_SQ9_Pos (10U)
hudakz 0:2cf53c219693 3685 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 3686 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
hudakz 0:2cf53c219693 3687 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3688 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3689 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3690 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3691 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3692
hudakz 0:2cf53c219693 3693 #define ADC_SQR2_SQ10_Pos (15U)
hudakz 0:2cf53c219693 3694 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
hudakz 0:2cf53c219693 3695 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
hudakz 0:2cf53c219693 3696 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3697 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3698 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3699 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3700 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3701
hudakz 0:2cf53c219693 3702 #define ADC_SQR2_SQ11_Pos (20U)
hudakz 0:2cf53c219693 3703 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
hudakz 0:2cf53c219693 3704 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
hudakz 0:2cf53c219693 3705 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3706 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3707 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3708 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3709 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 3710
hudakz 0:2cf53c219693 3711 #define ADC_SQR2_SQ12_Pos (25U)
hudakz 0:2cf53c219693 3712 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
hudakz 0:2cf53c219693 3713 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
hudakz 0:2cf53c219693 3714 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 3715 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 3716 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 3717 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 3718 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 3719
hudakz 0:2cf53c219693 3720 /******************* Bit definition for ADC_SQR3 register *******************/
hudakz 0:2cf53c219693 3721 #define ADC_SQR3_SQ1_Pos (0U)
hudakz 0:2cf53c219693 3722 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
hudakz 0:2cf53c219693 3723 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
hudakz 0:2cf53c219693 3724 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3725 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3726 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3727 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3728 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3729
hudakz 0:2cf53c219693 3730 #define ADC_SQR3_SQ2_Pos (5U)
hudakz 0:2cf53c219693 3731 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
hudakz 0:2cf53c219693 3732 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
hudakz 0:2cf53c219693 3733 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3734 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3735 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3736 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3737 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3738
hudakz 0:2cf53c219693 3739 #define ADC_SQR3_SQ3_Pos (10U)
hudakz 0:2cf53c219693 3740 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 3741 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
hudakz 0:2cf53c219693 3742 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3743 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3744 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3745 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3746 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3747
hudakz 0:2cf53c219693 3748 #define ADC_SQR3_SQ4_Pos (15U)
hudakz 0:2cf53c219693 3749 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
hudakz 0:2cf53c219693 3750 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
hudakz 0:2cf53c219693 3751 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3752 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3753 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3754 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3755 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3756
hudakz 0:2cf53c219693 3757 #define ADC_SQR3_SQ5_Pos (20U)
hudakz 0:2cf53c219693 3758 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
hudakz 0:2cf53c219693 3759 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
hudakz 0:2cf53c219693 3760 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3761 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3762 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 3763 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 3764 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 3765
hudakz 0:2cf53c219693 3766 #define ADC_SQR3_SQ6_Pos (25U)
hudakz 0:2cf53c219693 3767 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
hudakz 0:2cf53c219693 3768 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
hudakz 0:2cf53c219693 3769 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 3770 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 3771 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 3772 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 3773 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 3774
hudakz 0:2cf53c219693 3775 /******************* Bit definition for ADC_JSQR register *******************/
hudakz 0:2cf53c219693 3776 #define ADC_JSQR_JSQ1_Pos (0U)
hudakz 0:2cf53c219693 3777 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
hudakz 0:2cf53c219693 3778 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
hudakz 0:2cf53c219693 3779 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3780 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3781 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3782 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3783 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3784
hudakz 0:2cf53c219693 3785 #define ADC_JSQR_JSQ2_Pos (5U)
hudakz 0:2cf53c219693 3786 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
hudakz 0:2cf53c219693 3787 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
hudakz 0:2cf53c219693 3788 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3789 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3790 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3791 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3792 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3793
hudakz 0:2cf53c219693 3794 #define ADC_JSQR_JSQ3_Pos (10U)
hudakz 0:2cf53c219693 3795 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 3796 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
hudakz 0:2cf53c219693 3797 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3798 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3799 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3800 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3801 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3802
hudakz 0:2cf53c219693 3803 #define ADC_JSQR_JSQ4_Pos (15U)
hudakz 0:2cf53c219693 3804 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
hudakz 0:2cf53c219693 3805 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
hudakz 0:2cf53c219693 3806 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3807 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 3808 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 3809 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 3810 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 3811
hudakz 0:2cf53c219693 3812 #define ADC_JSQR_JL_Pos (20U)
hudakz 0:2cf53c219693 3813 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
hudakz 0:2cf53c219693 3814 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
hudakz 0:2cf53c219693 3815 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 3816 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 3817
hudakz 0:2cf53c219693 3818 /******************* Bit definition for ADC_JDR1 register *******************/
hudakz 0:2cf53c219693 3819 #define ADC_JDR1_JDATA_Pos (0U)
hudakz 0:2cf53c219693 3820 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 3821 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
hudakz 0:2cf53c219693 3822
hudakz 0:2cf53c219693 3823 /******************* Bit definition for ADC_JDR2 register *******************/
hudakz 0:2cf53c219693 3824 #define ADC_JDR2_JDATA_Pos (0U)
hudakz 0:2cf53c219693 3825 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 3826 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
hudakz 0:2cf53c219693 3827
hudakz 0:2cf53c219693 3828 /******************* Bit definition for ADC_JDR3 register *******************/
hudakz 0:2cf53c219693 3829 #define ADC_JDR3_JDATA_Pos (0U)
hudakz 0:2cf53c219693 3830 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 3831 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
hudakz 0:2cf53c219693 3832
hudakz 0:2cf53c219693 3833 /******************* Bit definition for ADC_JDR4 register *******************/
hudakz 0:2cf53c219693 3834 #define ADC_JDR4_JDATA_Pos (0U)
hudakz 0:2cf53c219693 3835 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 3836 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
hudakz 0:2cf53c219693 3837
hudakz 0:2cf53c219693 3838 /******************** Bit definition for ADC_DR register ********************/
hudakz 0:2cf53c219693 3839 #define ADC_DR_DATA_Pos (0U)
hudakz 0:2cf53c219693 3840 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 3841 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
hudakz 0:2cf53c219693 3842 #define ADC_DR_ADC2DATA_Pos (16U)
hudakz 0:2cf53c219693 3843 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
hudakz 0:2cf53c219693 3844 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
hudakz 0:2cf53c219693 3845
hudakz 0:2cf53c219693 3846
hudakz 0:2cf53c219693 3847 /*****************************************************************************/
hudakz 0:2cf53c219693 3848 /* */
hudakz 0:2cf53c219693 3849 /* Timers (TIM) */
hudakz 0:2cf53c219693 3850 /* */
hudakz 0:2cf53c219693 3851 /*****************************************************************************/
hudakz 0:2cf53c219693 3852 /******************* Bit definition for TIM_CR1 register *******************/
hudakz 0:2cf53c219693 3853 #define TIM_CR1_CEN_Pos (0U)
hudakz 0:2cf53c219693 3854 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3855 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
hudakz 0:2cf53c219693 3856 #define TIM_CR1_UDIS_Pos (1U)
hudakz 0:2cf53c219693 3857 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3858 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
hudakz 0:2cf53c219693 3859 #define TIM_CR1_URS_Pos (2U)
hudakz 0:2cf53c219693 3860 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3861 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
hudakz 0:2cf53c219693 3862 #define TIM_CR1_OPM_Pos (3U)
hudakz 0:2cf53c219693 3863 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3864 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
hudakz 0:2cf53c219693 3865 #define TIM_CR1_DIR_Pos (4U)
hudakz 0:2cf53c219693 3866 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3867 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
hudakz 0:2cf53c219693 3868
hudakz 0:2cf53c219693 3869 #define TIM_CR1_CMS_Pos (5U)
hudakz 0:2cf53c219693 3870 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
hudakz 0:2cf53c219693 3871 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
hudakz 0:2cf53c219693 3872 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3873 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3874
hudakz 0:2cf53c219693 3875 #define TIM_CR1_ARPE_Pos (7U)
hudakz 0:2cf53c219693 3876 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3877 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
hudakz 0:2cf53c219693 3878
hudakz 0:2cf53c219693 3879 #define TIM_CR1_CKD_Pos (8U)
hudakz 0:2cf53c219693 3880 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 3881 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
hudakz 0:2cf53c219693 3882 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3883 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3884
hudakz 0:2cf53c219693 3885 /******************* Bit definition for TIM_CR2 register *******************/
hudakz 0:2cf53c219693 3886 #define TIM_CR2_CCPC_Pos (0U)
hudakz 0:2cf53c219693 3887 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3888 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
hudakz 0:2cf53c219693 3889 #define TIM_CR2_CCUS_Pos (2U)
hudakz 0:2cf53c219693 3890 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3891 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
hudakz 0:2cf53c219693 3892 #define TIM_CR2_CCDS_Pos (3U)
hudakz 0:2cf53c219693 3893 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3894 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
hudakz 0:2cf53c219693 3895
hudakz 0:2cf53c219693 3896 #define TIM_CR2_MMS_Pos (4U)
hudakz 0:2cf53c219693 3897 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
hudakz 0:2cf53c219693 3898 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
hudakz 0:2cf53c219693 3899 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3900 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3901 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3902
hudakz 0:2cf53c219693 3903 #define TIM_CR2_TI1S_Pos (7U)
hudakz 0:2cf53c219693 3904 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3905 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
hudakz 0:2cf53c219693 3906 #define TIM_CR2_OIS1_Pos (8U)
hudakz 0:2cf53c219693 3907 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3908 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
hudakz 0:2cf53c219693 3909 #define TIM_CR2_OIS1N_Pos (9U)
hudakz 0:2cf53c219693 3910 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3911 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
hudakz 0:2cf53c219693 3912 #define TIM_CR2_OIS2_Pos (10U)
hudakz 0:2cf53c219693 3913 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3914 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
hudakz 0:2cf53c219693 3915 #define TIM_CR2_OIS2N_Pos (11U)
hudakz 0:2cf53c219693 3916 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3917 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
hudakz 0:2cf53c219693 3918 #define TIM_CR2_OIS3_Pos (12U)
hudakz 0:2cf53c219693 3919 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3920 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
hudakz 0:2cf53c219693 3921 #define TIM_CR2_OIS3N_Pos (13U)
hudakz 0:2cf53c219693 3922 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3923 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
hudakz 0:2cf53c219693 3924 #define TIM_CR2_OIS4_Pos (14U)
hudakz 0:2cf53c219693 3925 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3926 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
hudakz 0:2cf53c219693 3927
hudakz 0:2cf53c219693 3928 /******************* Bit definition for TIM_SMCR register ******************/
hudakz 0:2cf53c219693 3929 #define TIM_SMCR_SMS_Pos (0U)
hudakz 0:2cf53c219693 3930 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
hudakz 0:2cf53c219693 3931 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
hudakz 0:2cf53c219693 3932 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3933 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3934 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3935
hudakz 0:2cf53c219693 3936 #define TIM_SMCR_TS_Pos (4U)
hudakz 0:2cf53c219693 3937 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
hudakz 0:2cf53c219693 3938 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
hudakz 0:2cf53c219693 3939 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3940 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3941 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3942
hudakz 0:2cf53c219693 3943 #define TIM_SMCR_MSM_Pos (7U)
hudakz 0:2cf53c219693 3944 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3945 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
hudakz 0:2cf53c219693 3946
hudakz 0:2cf53c219693 3947 #define TIM_SMCR_ETF_Pos (8U)
hudakz 0:2cf53c219693 3948 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
hudakz 0:2cf53c219693 3949 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
hudakz 0:2cf53c219693 3950 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3951 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3952 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 3953 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 3954
hudakz 0:2cf53c219693 3955 #define TIM_SMCR_ETPS_Pos (12U)
hudakz 0:2cf53c219693 3956 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 3957 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
hudakz 0:2cf53c219693 3958 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 3959 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 3960
hudakz 0:2cf53c219693 3961 #define TIM_SMCR_ECE_Pos (14U)
hudakz 0:2cf53c219693 3962 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 3963 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
hudakz 0:2cf53c219693 3964 #define TIM_SMCR_ETP_Pos (15U)
hudakz 0:2cf53c219693 3965 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 3966 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
hudakz 0:2cf53c219693 3967
hudakz 0:2cf53c219693 3968 /******************* Bit definition for TIM_DIER register ******************/
hudakz 0:2cf53c219693 3969 #define TIM_DIER_UIE_Pos (0U)
hudakz 0:2cf53c219693 3970 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 3971 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
hudakz 0:2cf53c219693 3972 #define TIM_DIER_CC1IE_Pos (1U)
hudakz 0:2cf53c219693 3973 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 3974 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
hudakz 0:2cf53c219693 3975 #define TIM_DIER_CC2IE_Pos (2U)
hudakz 0:2cf53c219693 3976 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 3977 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
hudakz 0:2cf53c219693 3978 #define TIM_DIER_CC3IE_Pos (3U)
hudakz 0:2cf53c219693 3979 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 3980 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
hudakz 0:2cf53c219693 3981 #define TIM_DIER_CC4IE_Pos (4U)
hudakz 0:2cf53c219693 3982 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 3983 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
hudakz 0:2cf53c219693 3984 #define TIM_DIER_COMIE_Pos (5U)
hudakz 0:2cf53c219693 3985 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 3986 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
hudakz 0:2cf53c219693 3987 #define TIM_DIER_TIE_Pos (6U)
hudakz 0:2cf53c219693 3988 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 3989 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
hudakz 0:2cf53c219693 3990 #define TIM_DIER_BIE_Pos (7U)
hudakz 0:2cf53c219693 3991 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 3992 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
hudakz 0:2cf53c219693 3993 #define TIM_DIER_UDE_Pos (8U)
hudakz 0:2cf53c219693 3994 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 3995 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
hudakz 0:2cf53c219693 3996 #define TIM_DIER_CC1DE_Pos (9U)
hudakz 0:2cf53c219693 3997 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 3998 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
hudakz 0:2cf53c219693 3999 #define TIM_DIER_CC2DE_Pos (10U)
hudakz 0:2cf53c219693 4000 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4001 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
hudakz 0:2cf53c219693 4002 #define TIM_DIER_CC3DE_Pos (11U)
hudakz 0:2cf53c219693 4003 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4004 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
hudakz 0:2cf53c219693 4005 #define TIM_DIER_CC4DE_Pos (12U)
hudakz 0:2cf53c219693 4006 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4007 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
hudakz 0:2cf53c219693 4008 #define TIM_DIER_COMDE_Pos (13U)
hudakz 0:2cf53c219693 4009 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4010 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
hudakz 0:2cf53c219693 4011 #define TIM_DIER_TDE_Pos (14U)
hudakz 0:2cf53c219693 4012 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4013 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
hudakz 0:2cf53c219693 4014
hudakz 0:2cf53c219693 4015 /******************** Bit definition for TIM_SR register *******************/
hudakz 0:2cf53c219693 4016 #define TIM_SR_UIF_Pos (0U)
hudakz 0:2cf53c219693 4017 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4018 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
hudakz 0:2cf53c219693 4019 #define TIM_SR_CC1IF_Pos (1U)
hudakz 0:2cf53c219693 4020 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4021 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
hudakz 0:2cf53c219693 4022 #define TIM_SR_CC2IF_Pos (2U)
hudakz 0:2cf53c219693 4023 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4024 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
hudakz 0:2cf53c219693 4025 #define TIM_SR_CC3IF_Pos (3U)
hudakz 0:2cf53c219693 4026 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4027 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
hudakz 0:2cf53c219693 4028 #define TIM_SR_CC4IF_Pos (4U)
hudakz 0:2cf53c219693 4029 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4030 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
hudakz 0:2cf53c219693 4031 #define TIM_SR_COMIF_Pos (5U)
hudakz 0:2cf53c219693 4032 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4033 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
hudakz 0:2cf53c219693 4034 #define TIM_SR_TIF_Pos (6U)
hudakz 0:2cf53c219693 4035 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4036 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
hudakz 0:2cf53c219693 4037 #define TIM_SR_BIF_Pos (7U)
hudakz 0:2cf53c219693 4038 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4039 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
hudakz 0:2cf53c219693 4040 #define TIM_SR_CC1OF_Pos (9U)
hudakz 0:2cf53c219693 4041 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4042 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
hudakz 0:2cf53c219693 4043 #define TIM_SR_CC2OF_Pos (10U)
hudakz 0:2cf53c219693 4044 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4045 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
hudakz 0:2cf53c219693 4046 #define TIM_SR_CC3OF_Pos (11U)
hudakz 0:2cf53c219693 4047 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4048 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
hudakz 0:2cf53c219693 4049 #define TIM_SR_CC4OF_Pos (12U)
hudakz 0:2cf53c219693 4050 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4051 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
hudakz 0:2cf53c219693 4052
hudakz 0:2cf53c219693 4053 /******************* Bit definition for TIM_EGR register *******************/
hudakz 0:2cf53c219693 4054 #define TIM_EGR_UG_Pos (0U)
hudakz 0:2cf53c219693 4055 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4056 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
hudakz 0:2cf53c219693 4057 #define TIM_EGR_CC1G_Pos (1U)
hudakz 0:2cf53c219693 4058 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4059 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
hudakz 0:2cf53c219693 4060 #define TIM_EGR_CC2G_Pos (2U)
hudakz 0:2cf53c219693 4061 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4062 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
hudakz 0:2cf53c219693 4063 #define TIM_EGR_CC3G_Pos (3U)
hudakz 0:2cf53c219693 4064 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4065 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
hudakz 0:2cf53c219693 4066 #define TIM_EGR_CC4G_Pos (4U)
hudakz 0:2cf53c219693 4067 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4068 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
hudakz 0:2cf53c219693 4069 #define TIM_EGR_COMG_Pos (5U)
hudakz 0:2cf53c219693 4070 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4071 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
hudakz 0:2cf53c219693 4072 #define TIM_EGR_TG_Pos (6U)
hudakz 0:2cf53c219693 4073 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4074 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
hudakz 0:2cf53c219693 4075 #define TIM_EGR_BG_Pos (7U)
hudakz 0:2cf53c219693 4076 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4077 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
hudakz 0:2cf53c219693 4078
hudakz 0:2cf53c219693 4079 /****************** Bit definition for TIM_CCMR1 register ******************/
hudakz 0:2cf53c219693 4080 #define TIM_CCMR1_CC1S_Pos (0U)
hudakz 0:2cf53c219693 4081 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 4082 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
hudakz 0:2cf53c219693 4083 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4084 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4085
hudakz 0:2cf53c219693 4086 #define TIM_CCMR1_OC1FE_Pos (2U)
hudakz 0:2cf53c219693 4087 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4088 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
hudakz 0:2cf53c219693 4089 #define TIM_CCMR1_OC1PE_Pos (3U)
hudakz 0:2cf53c219693 4090 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4091 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
hudakz 0:2cf53c219693 4092
hudakz 0:2cf53c219693 4093 #define TIM_CCMR1_OC1M_Pos (4U)
hudakz 0:2cf53c219693 4094 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
hudakz 0:2cf53c219693 4095 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
hudakz 0:2cf53c219693 4096 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4097 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4098 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4099
hudakz 0:2cf53c219693 4100 #define TIM_CCMR1_OC1CE_Pos (7U)
hudakz 0:2cf53c219693 4101 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4102 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
hudakz 0:2cf53c219693 4103
hudakz 0:2cf53c219693 4104 #define TIM_CCMR1_CC2S_Pos (8U)
hudakz 0:2cf53c219693 4105 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 4106 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
hudakz 0:2cf53c219693 4107 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4108 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4109
hudakz 0:2cf53c219693 4110 #define TIM_CCMR1_OC2FE_Pos (10U)
hudakz 0:2cf53c219693 4111 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4112 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
hudakz 0:2cf53c219693 4113 #define TIM_CCMR1_OC2PE_Pos (11U)
hudakz 0:2cf53c219693 4114 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4115 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
hudakz 0:2cf53c219693 4116
hudakz 0:2cf53c219693 4117 #define TIM_CCMR1_OC2M_Pos (12U)
hudakz 0:2cf53c219693 4118 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
hudakz 0:2cf53c219693 4119 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
hudakz 0:2cf53c219693 4120 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4121 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4122 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4123
hudakz 0:2cf53c219693 4124 #define TIM_CCMR1_OC2CE_Pos (15U)
hudakz 0:2cf53c219693 4125 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4126 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
hudakz 0:2cf53c219693 4127
hudakz 0:2cf53c219693 4128 /*---------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 4129
hudakz 0:2cf53c219693 4130 #define TIM_CCMR1_IC1PSC_Pos (2U)
hudakz 0:2cf53c219693 4131 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
hudakz 0:2cf53c219693 4132 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
hudakz 0:2cf53c219693 4133 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4134 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4135
hudakz 0:2cf53c219693 4136 #define TIM_CCMR1_IC1F_Pos (4U)
hudakz 0:2cf53c219693 4137 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 4138 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
hudakz 0:2cf53c219693 4139 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4140 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4141 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4142 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4143
hudakz 0:2cf53c219693 4144 #define TIM_CCMR1_IC2PSC_Pos (10U)
hudakz 0:2cf53c219693 4145 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
hudakz 0:2cf53c219693 4146 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
hudakz 0:2cf53c219693 4147 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4148 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4149
hudakz 0:2cf53c219693 4150 #define TIM_CCMR1_IC2F_Pos (12U)
hudakz 0:2cf53c219693 4151 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
hudakz 0:2cf53c219693 4152 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
hudakz 0:2cf53c219693 4153 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4154 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4155 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4156 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4157
hudakz 0:2cf53c219693 4158 /****************** Bit definition for TIM_CCMR2 register ******************/
hudakz 0:2cf53c219693 4159 #define TIM_CCMR2_CC3S_Pos (0U)
hudakz 0:2cf53c219693 4160 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 4161 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
hudakz 0:2cf53c219693 4162 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4163 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4164
hudakz 0:2cf53c219693 4165 #define TIM_CCMR2_OC3FE_Pos (2U)
hudakz 0:2cf53c219693 4166 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4167 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
hudakz 0:2cf53c219693 4168 #define TIM_CCMR2_OC3PE_Pos (3U)
hudakz 0:2cf53c219693 4169 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4170 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
hudakz 0:2cf53c219693 4171
hudakz 0:2cf53c219693 4172 #define TIM_CCMR2_OC3M_Pos (4U)
hudakz 0:2cf53c219693 4173 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
hudakz 0:2cf53c219693 4174 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
hudakz 0:2cf53c219693 4175 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4176 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4177 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4178
hudakz 0:2cf53c219693 4179 #define TIM_CCMR2_OC3CE_Pos (7U)
hudakz 0:2cf53c219693 4180 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4181 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
hudakz 0:2cf53c219693 4182
hudakz 0:2cf53c219693 4183 #define TIM_CCMR2_CC4S_Pos (8U)
hudakz 0:2cf53c219693 4184 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 4185 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
hudakz 0:2cf53c219693 4186 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4187 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4188
hudakz 0:2cf53c219693 4189 #define TIM_CCMR2_OC4FE_Pos (10U)
hudakz 0:2cf53c219693 4190 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4191 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
hudakz 0:2cf53c219693 4192 #define TIM_CCMR2_OC4PE_Pos (11U)
hudakz 0:2cf53c219693 4193 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4194 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
hudakz 0:2cf53c219693 4195
hudakz 0:2cf53c219693 4196 #define TIM_CCMR2_OC4M_Pos (12U)
hudakz 0:2cf53c219693 4197 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
hudakz 0:2cf53c219693 4198 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
hudakz 0:2cf53c219693 4199 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4200 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4201 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4202
hudakz 0:2cf53c219693 4203 #define TIM_CCMR2_OC4CE_Pos (15U)
hudakz 0:2cf53c219693 4204 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4205 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
hudakz 0:2cf53c219693 4206
hudakz 0:2cf53c219693 4207 /*---------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 4208
hudakz 0:2cf53c219693 4209 #define TIM_CCMR2_IC3PSC_Pos (2U)
hudakz 0:2cf53c219693 4210 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
hudakz 0:2cf53c219693 4211 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
hudakz 0:2cf53c219693 4212 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4213 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4214
hudakz 0:2cf53c219693 4215 #define TIM_CCMR2_IC3F_Pos (4U)
hudakz 0:2cf53c219693 4216 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 4217 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
hudakz 0:2cf53c219693 4218 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4219 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4220 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4221 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4222
hudakz 0:2cf53c219693 4223 #define TIM_CCMR2_IC4PSC_Pos (10U)
hudakz 0:2cf53c219693 4224 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
hudakz 0:2cf53c219693 4225 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
hudakz 0:2cf53c219693 4226 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4227 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4228
hudakz 0:2cf53c219693 4229 #define TIM_CCMR2_IC4F_Pos (12U)
hudakz 0:2cf53c219693 4230 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
hudakz 0:2cf53c219693 4231 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
hudakz 0:2cf53c219693 4232 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4233 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4234 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4235 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4236
hudakz 0:2cf53c219693 4237 /******************* Bit definition for TIM_CCER register ******************/
hudakz 0:2cf53c219693 4238 #define TIM_CCER_CC1E_Pos (0U)
hudakz 0:2cf53c219693 4239 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4240 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
hudakz 0:2cf53c219693 4241 #define TIM_CCER_CC1P_Pos (1U)
hudakz 0:2cf53c219693 4242 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4243 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
hudakz 0:2cf53c219693 4244 #define TIM_CCER_CC1NE_Pos (2U)
hudakz 0:2cf53c219693 4245 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4246 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
hudakz 0:2cf53c219693 4247 #define TIM_CCER_CC1NP_Pos (3U)
hudakz 0:2cf53c219693 4248 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4249 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
hudakz 0:2cf53c219693 4250 #define TIM_CCER_CC2E_Pos (4U)
hudakz 0:2cf53c219693 4251 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4252 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
hudakz 0:2cf53c219693 4253 #define TIM_CCER_CC2P_Pos (5U)
hudakz 0:2cf53c219693 4254 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4255 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
hudakz 0:2cf53c219693 4256 #define TIM_CCER_CC2NE_Pos (6U)
hudakz 0:2cf53c219693 4257 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4258 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
hudakz 0:2cf53c219693 4259 #define TIM_CCER_CC2NP_Pos (7U)
hudakz 0:2cf53c219693 4260 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4261 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
hudakz 0:2cf53c219693 4262 #define TIM_CCER_CC3E_Pos (8U)
hudakz 0:2cf53c219693 4263 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4264 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
hudakz 0:2cf53c219693 4265 #define TIM_CCER_CC3P_Pos (9U)
hudakz 0:2cf53c219693 4266 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4267 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
hudakz 0:2cf53c219693 4268 #define TIM_CCER_CC3NE_Pos (10U)
hudakz 0:2cf53c219693 4269 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4270 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
hudakz 0:2cf53c219693 4271 #define TIM_CCER_CC3NP_Pos (11U)
hudakz 0:2cf53c219693 4272 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4273 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
hudakz 0:2cf53c219693 4274 #define TIM_CCER_CC4E_Pos (12U)
hudakz 0:2cf53c219693 4275 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4276 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
hudakz 0:2cf53c219693 4277 #define TIM_CCER_CC4P_Pos (13U)
hudakz 0:2cf53c219693 4278 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4279 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
hudakz 0:2cf53c219693 4280
hudakz 0:2cf53c219693 4281 /******************* Bit definition for TIM_CNT register *******************/
hudakz 0:2cf53c219693 4282 #define TIM_CNT_CNT_Pos (0U)
hudakz 0:2cf53c219693 4283 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4284 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
hudakz 0:2cf53c219693 4285
hudakz 0:2cf53c219693 4286 /******************* Bit definition for TIM_PSC register *******************/
hudakz 0:2cf53c219693 4287 #define TIM_PSC_PSC_Pos (0U)
hudakz 0:2cf53c219693 4288 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4289 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
hudakz 0:2cf53c219693 4290
hudakz 0:2cf53c219693 4291 /******************* Bit definition for TIM_ARR register *******************/
hudakz 0:2cf53c219693 4292 #define TIM_ARR_ARR_Pos (0U)
hudakz 0:2cf53c219693 4293 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4294 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
hudakz 0:2cf53c219693 4295
hudakz 0:2cf53c219693 4296 /******************* Bit definition for TIM_RCR register *******************/
hudakz 0:2cf53c219693 4297 #define TIM_RCR_REP_Pos (0U)
hudakz 0:2cf53c219693 4298 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 4299 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
hudakz 0:2cf53c219693 4300
hudakz 0:2cf53c219693 4301 /******************* Bit definition for TIM_CCR1 register ******************/
hudakz 0:2cf53c219693 4302 #define TIM_CCR1_CCR1_Pos (0U)
hudakz 0:2cf53c219693 4303 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4304 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
hudakz 0:2cf53c219693 4305
hudakz 0:2cf53c219693 4306 /******************* Bit definition for TIM_CCR2 register ******************/
hudakz 0:2cf53c219693 4307 #define TIM_CCR2_CCR2_Pos (0U)
hudakz 0:2cf53c219693 4308 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4309 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
hudakz 0:2cf53c219693 4310
hudakz 0:2cf53c219693 4311 /******************* Bit definition for TIM_CCR3 register ******************/
hudakz 0:2cf53c219693 4312 #define TIM_CCR3_CCR3_Pos (0U)
hudakz 0:2cf53c219693 4313 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4314 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
hudakz 0:2cf53c219693 4315
hudakz 0:2cf53c219693 4316 /******************* Bit definition for TIM_CCR4 register ******************/
hudakz 0:2cf53c219693 4317 #define TIM_CCR4_CCR4_Pos (0U)
hudakz 0:2cf53c219693 4318 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4319 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
hudakz 0:2cf53c219693 4320
hudakz 0:2cf53c219693 4321 /******************* Bit definition for TIM_BDTR register ******************/
hudakz 0:2cf53c219693 4322 #define TIM_BDTR_DTG_Pos (0U)
hudakz 0:2cf53c219693 4323 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 4324 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
hudakz 0:2cf53c219693 4325 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4326 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4327 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4328 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4329 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4330 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4331 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4332 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4333
hudakz 0:2cf53c219693 4334 #define TIM_BDTR_LOCK_Pos (8U)
hudakz 0:2cf53c219693 4335 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
hudakz 0:2cf53c219693 4336 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
hudakz 0:2cf53c219693 4337 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4338 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4339
hudakz 0:2cf53c219693 4340 #define TIM_BDTR_OSSI_Pos (10U)
hudakz 0:2cf53c219693 4341 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4342 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
hudakz 0:2cf53c219693 4343 #define TIM_BDTR_OSSR_Pos (11U)
hudakz 0:2cf53c219693 4344 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4345 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
hudakz 0:2cf53c219693 4346 #define TIM_BDTR_BKE_Pos (12U)
hudakz 0:2cf53c219693 4347 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4348 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
hudakz 0:2cf53c219693 4349 #define TIM_BDTR_BKP_Pos (13U)
hudakz 0:2cf53c219693 4350 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4351 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
hudakz 0:2cf53c219693 4352 #define TIM_BDTR_AOE_Pos (14U)
hudakz 0:2cf53c219693 4353 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4354 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
hudakz 0:2cf53c219693 4355 #define TIM_BDTR_MOE_Pos (15U)
hudakz 0:2cf53c219693 4356 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4357 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
hudakz 0:2cf53c219693 4358
hudakz 0:2cf53c219693 4359 /******************* Bit definition for TIM_DCR register *******************/
hudakz 0:2cf53c219693 4360 #define TIM_DCR_DBA_Pos (0U)
hudakz 0:2cf53c219693 4361 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
hudakz 0:2cf53c219693 4362 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
hudakz 0:2cf53c219693 4363 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4364 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4365 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4366 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4367 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4368
hudakz 0:2cf53c219693 4369 #define TIM_DCR_DBL_Pos (8U)
hudakz 0:2cf53c219693 4370 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
hudakz 0:2cf53c219693 4371 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
hudakz 0:2cf53c219693 4372 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4373 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4374 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4375 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4376 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4377
hudakz 0:2cf53c219693 4378 /******************* Bit definition for TIM_DMAR register ******************/
hudakz 0:2cf53c219693 4379 #define TIM_DMAR_DMAB_Pos (0U)
hudakz 0:2cf53c219693 4380 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4381 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
hudakz 0:2cf53c219693 4382
hudakz 0:2cf53c219693 4383 /******************************************************************************/
hudakz 0:2cf53c219693 4384 /* */
hudakz 0:2cf53c219693 4385 /* Real-Time Clock */
hudakz 0:2cf53c219693 4386 /* */
hudakz 0:2cf53c219693 4387 /******************************************************************************/
hudakz 0:2cf53c219693 4388
hudakz 0:2cf53c219693 4389 /******************* Bit definition for RTC_CRH register ********************/
hudakz 0:2cf53c219693 4390 #define RTC_CRH_SECIE_Pos (0U)
hudakz 0:2cf53c219693 4391 #define RTC_CRH_SECIE_Msk (0x1U << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4392 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
hudakz 0:2cf53c219693 4393 #define RTC_CRH_ALRIE_Pos (1U)
hudakz 0:2cf53c219693 4394 #define RTC_CRH_ALRIE_Msk (0x1U << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4395 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
hudakz 0:2cf53c219693 4396 #define RTC_CRH_OWIE_Pos (2U)
hudakz 0:2cf53c219693 4397 #define RTC_CRH_OWIE_Msk (0x1U << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4398 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
hudakz 0:2cf53c219693 4399
hudakz 0:2cf53c219693 4400 /******************* Bit definition for RTC_CRL register ********************/
hudakz 0:2cf53c219693 4401 #define RTC_CRL_SECF_Pos (0U)
hudakz 0:2cf53c219693 4402 #define RTC_CRL_SECF_Msk (0x1U << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4403 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
hudakz 0:2cf53c219693 4404 #define RTC_CRL_ALRF_Pos (1U)
hudakz 0:2cf53c219693 4405 #define RTC_CRL_ALRF_Msk (0x1U << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4406 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
hudakz 0:2cf53c219693 4407 #define RTC_CRL_OWF_Pos (2U)
hudakz 0:2cf53c219693 4408 #define RTC_CRL_OWF_Msk (0x1U << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4409 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
hudakz 0:2cf53c219693 4410 #define RTC_CRL_RSF_Pos (3U)
hudakz 0:2cf53c219693 4411 #define RTC_CRL_RSF_Msk (0x1U << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4412 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
hudakz 0:2cf53c219693 4413 #define RTC_CRL_CNF_Pos (4U)
hudakz 0:2cf53c219693 4414 #define RTC_CRL_CNF_Msk (0x1U << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4415 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
hudakz 0:2cf53c219693 4416 #define RTC_CRL_RTOFF_Pos (5U)
hudakz 0:2cf53c219693 4417 #define RTC_CRL_RTOFF_Msk (0x1U << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4418 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
hudakz 0:2cf53c219693 4419
hudakz 0:2cf53c219693 4420 /******************* Bit definition for RTC_PRLH register *******************/
hudakz 0:2cf53c219693 4421 #define RTC_PRLH_PRL_Pos (0U)
hudakz 0:2cf53c219693 4422 #define RTC_PRLH_PRL_Msk (0xFU << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 4423 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
hudakz 0:2cf53c219693 4424
hudakz 0:2cf53c219693 4425 /******************* Bit definition for RTC_PRLL register *******************/
hudakz 0:2cf53c219693 4426 #define RTC_PRLL_PRL_Pos (0U)
hudakz 0:2cf53c219693 4427 #define RTC_PRLL_PRL_Msk (0xFFFFU << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4428 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
hudakz 0:2cf53c219693 4429
hudakz 0:2cf53c219693 4430 /******************* Bit definition for RTC_DIVH register *******************/
hudakz 0:2cf53c219693 4431 #define RTC_DIVH_RTC_DIV_Pos (0U)
hudakz 0:2cf53c219693 4432 #define RTC_DIVH_RTC_DIV_Msk (0xFU << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 4433 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
hudakz 0:2cf53c219693 4434
hudakz 0:2cf53c219693 4435 /******************* Bit definition for RTC_DIVL register *******************/
hudakz 0:2cf53c219693 4436 #define RTC_DIVL_RTC_DIV_Pos (0U)
hudakz 0:2cf53c219693 4437 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFU << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4438 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
hudakz 0:2cf53c219693 4439
hudakz 0:2cf53c219693 4440 /******************* Bit definition for RTC_CNTH register *******************/
hudakz 0:2cf53c219693 4441 #define RTC_CNTH_RTC_CNT_Pos (0U)
hudakz 0:2cf53c219693 4442 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFU << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4443 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
hudakz 0:2cf53c219693 4444
hudakz 0:2cf53c219693 4445 /******************* Bit definition for RTC_CNTL register *******************/
hudakz 0:2cf53c219693 4446 #define RTC_CNTL_RTC_CNT_Pos (0U)
hudakz 0:2cf53c219693 4447 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFU << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4448 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
hudakz 0:2cf53c219693 4449
hudakz 0:2cf53c219693 4450 /******************* Bit definition for RTC_ALRH register *******************/
hudakz 0:2cf53c219693 4451 #define RTC_ALRH_RTC_ALR_Pos (0U)
hudakz 0:2cf53c219693 4452 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFU << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4453 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
hudakz 0:2cf53c219693 4454
hudakz 0:2cf53c219693 4455 /******************* Bit definition for RTC_ALRL register *******************/
hudakz 0:2cf53c219693 4456 #define RTC_ALRL_RTC_ALR_Pos (0U)
hudakz 0:2cf53c219693 4457 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFU << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4458 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
hudakz 0:2cf53c219693 4459
hudakz 0:2cf53c219693 4460 /******************************************************************************/
hudakz 0:2cf53c219693 4461 /* */
hudakz 0:2cf53c219693 4462 /* Independent WATCHDOG (IWDG) */
hudakz 0:2cf53c219693 4463 /* */
hudakz 0:2cf53c219693 4464 /******************************************************************************/
hudakz 0:2cf53c219693 4465
hudakz 0:2cf53c219693 4466 /******************* Bit definition for IWDG_KR register ********************/
hudakz 0:2cf53c219693 4467 #define IWDG_KR_KEY_Pos (0U)
hudakz 0:2cf53c219693 4468 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 4469 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
hudakz 0:2cf53c219693 4470
hudakz 0:2cf53c219693 4471 /******************* Bit definition for IWDG_PR register ********************/
hudakz 0:2cf53c219693 4472 #define IWDG_PR_PR_Pos (0U)
hudakz 0:2cf53c219693 4473 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
hudakz 0:2cf53c219693 4474 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
hudakz 0:2cf53c219693 4475 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4476 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4477 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4478
hudakz 0:2cf53c219693 4479 /******************* Bit definition for IWDG_RLR register *******************/
hudakz 0:2cf53c219693 4480 #define IWDG_RLR_RL_Pos (0U)
hudakz 0:2cf53c219693 4481 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 4482 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
hudakz 0:2cf53c219693 4483
hudakz 0:2cf53c219693 4484 /******************* Bit definition for IWDG_SR register ********************/
hudakz 0:2cf53c219693 4485 #define IWDG_SR_PVU_Pos (0U)
hudakz 0:2cf53c219693 4486 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4487 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
hudakz 0:2cf53c219693 4488 #define IWDG_SR_RVU_Pos (1U)
hudakz 0:2cf53c219693 4489 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4490 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
hudakz 0:2cf53c219693 4491
hudakz 0:2cf53c219693 4492 /******************************************************************************/
hudakz 0:2cf53c219693 4493 /* */
hudakz 0:2cf53c219693 4494 /* Window WATCHDOG (WWDG) */
hudakz 0:2cf53c219693 4495 /* */
hudakz 0:2cf53c219693 4496 /******************************************************************************/
hudakz 0:2cf53c219693 4497
hudakz 0:2cf53c219693 4498 /******************* Bit definition for WWDG_CR register ********************/
hudakz 0:2cf53c219693 4499 #define WWDG_CR_T_Pos (0U)
hudakz 0:2cf53c219693 4500 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
hudakz 0:2cf53c219693 4501 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
hudakz 0:2cf53c219693 4502 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4503 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4504 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4505 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4506 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4507 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4508 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4509
hudakz 0:2cf53c219693 4510 /* Legacy defines */
hudakz 0:2cf53c219693 4511 #define WWDG_CR_T0 WWDG_CR_T_0
hudakz 0:2cf53c219693 4512 #define WWDG_CR_T1 WWDG_CR_T_1
hudakz 0:2cf53c219693 4513 #define WWDG_CR_T2 WWDG_CR_T_2
hudakz 0:2cf53c219693 4514 #define WWDG_CR_T3 WWDG_CR_T_3
hudakz 0:2cf53c219693 4515 #define WWDG_CR_T4 WWDG_CR_T_4
hudakz 0:2cf53c219693 4516 #define WWDG_CR_T5 WWDG_CR_T_5
hudakz 0:2cf53c219693 4517 #define WWDG_CR_T6 WWDG_CR_T_6
hudakz 0:2cf53c219693 4518
hudakz 0:2cf53c219693 4519 #define WWDG_CR_WDGA_Pos (7U)
hudakz 0:2cf53c219693 4520 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4521 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
hudakz 0:2cf53c219693 4522
hudakz 0:2cf53c219693 4523 /******************* Bit definition for WWDG_CFR register *******************/
hudakz 0:2cf53c219693 4524 #define WWDG_CFR_W_Pos (0U)
hudakz 0:2cf53c219693 4525 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
hudakz 0:2cf53c219693 4526 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
hudakz 0:2cf53c219693 4527 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4528 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4529 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4530 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4531 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4532 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4533 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4534
hudakz 0:2cf53c219693 4535 /* Legacy defines */
hudakz 0:2cf53c219693 4536 #define WWDG_CFR_W0 WWDG_CFR_W_0
hudakz 0:2cf53c219693 4537 #define WWDG_CFR_W1 WWDG_CFR_W_1
hudakz 0:2cf53c219693 4538 #define WWDG_CFR_W2 WWDG_CFR_W_2
hudakz 0:2cf53c219693 4539 #define WWDG_CFR_W3 WWDG_CFR_W_3
hudakz 0:2cf53c219693 4540 #define WWDG_CFR_W4 WWDG_CFR_W_4
hudakz 0:2cf53c219693 4541 #define WWDG_CFR_W5 WWDG_CFR_W_5
hudakz 0:2cf53c219693 4542 #define WWDG_CFR_W6 WWDG_CFR_W_6
hudakz 0:2cf53c219693 4543
hudakz 0:2cf53c219693 4544 #define WWDG_CFR_WDGTB_Pos (7U)
hudakz 0:2cf53c219693 4545 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
hudakz 0:2cf53c219693 4546 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
hudakz 0:2cf53c219693 4547 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4548 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4549
hudakz 0:2cf53c219693 4550 /* Legacy defines */
hudakz 0:2cf53c219693 4551 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
hudakz 0:2cf53c219693 4552 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
hudakz 0:2cf53c219693 4553
hudakz 0:2cf53c219693 4554 #define WWDG_CFR_EWI_Pos (9U)
hudakz 0:2cf53c219693 4555 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4556 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
hudakz 0:2cf53c219693 4557
hudakz 0:2cf53c219693 4558 /******************* Bit definition for WWDG_SR register ********************/
hudakz 0:2cf53c219693 4559 #define WWDG_SR_EWIF_Pos (0U)
hudakz 0:2cf53c219693 4560 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4561 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
hudakz 0:2cf53c219693 4562
hudakz 0:2cf53c219693 4563
hudakz 0:2cf53c219693 4564 /******************************************************************************/
hudakz 0:2cf53c219693 4565 /* */
hudakz 0:2cf53c219693 4566 /* SD host Interface */
hudakz 0:2cf53c219693 4567 /* */
hudakz 0:2cf53c219693 4568 /******************************************************************************/
hudakz 0:2cf53c219693 4569
hudakz 0:2cf53c219693 4570 /****************** Bit definition for SDIO_POWER register ******************/
hudakz 0:2cf53c219693 4571 #define SDIO_POWER_PWRCTRL_Pos (0U)
hudakz 0:2cf53c219693 4572 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 4573 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!< PWRCTRL[1:0] bits (Power supply control bits) */
hudakz 0:2cf53c219693 4574 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
hudakz 0:2cf53c219693 4575 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
hudakz 0:2cf53c219693 4576
hudakz 0:2cf53c219693 4577 /****************** Bit definition for SDIO_CLKCR register ******************/
hudakz 0:2cf53c219693 4578 #define SDIO_CLKCR_CLKDIV_Pos (0U)
hudakz 0:2cf53c219693 4579 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 4580 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!< Clock divide factor */
hudakz 0:2cf53c219693 4581 #define SDIO_CLKCR_CLKEN_Pos (8U)
hudakz 0:2cf53c219693 4582 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4583 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!< Clock enable bit */
hudakz 0:2cf53c219693 4584 #define SDIO_CLKCR_PWRSAV_Pos (9U)
hudakz 0:2cf53c219693 4585 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4586 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!< Power saving configuration bit */
hudakz 0:2cf53c219693 4587 #define SDIO_CLKCR_BYPASS_Pos (10U)
hudakz 0:2cf53c219693 4588 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4589 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!< Clock divider bypass enable bit */
hudakz 0:2cf53c219693 4590
hudakz 0:2cf53c219693 4591 #define SDIO_CLKCR_WIDBUS_Pos (11U)
hudakz 0:2cf53c219693 4592 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
hudakz 0:2cf53c219693 4593 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
hudakz 0:2cf53c219693 4594 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
hudakz 0:2cf53c219693 4595 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
hudakz 0:2cf53c219693 4596
hudakz 0:2cf53c219693 4597 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
hudakz 0:2cf53c219693 4598 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4599 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!< SDIO_CK dephasing selection bit */
hudakz 0:2cf53c219693 4600 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
hudakz 0:2cf53c219693 4601 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4602 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!< HW Flow Control enable */
hudakz 0:2cf53c219693 4603
hudakz 0:2cf53c219693 4604 /******************* Bit definition for SDIO_ARG register *******************/
hudakz 0:2cf53c219693 4605 #define SDIO_ARG_CMDARG_Pos (0U)
hudakz 0:2cf53c219693 4606 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4607 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!< Command argument */
hudakz 0:2cf53c219693 4608
hudakz 0:2cf53c219693 4609 /******************* Bit definition for SDIO_CMD register *******************/
hudakz 0:2cf53c219693 4610 #define SDIO_CMD_CMDINDEX_Pos (0U)
hudakz 0:2cf53c219693 4611 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
hudakz 0:2cf53c219693 4612 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!< Command Index */
hudakz 0:2cf53c219693 4613
hudakz 0:2cf53c219693 4614 #define SDIO_CMD_WAITRESP_Pos (6U)
hudakz 0:2cf53c219693 4615 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
hudakz 0:2cf53c219693 4616 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!< WAITRESP[1:0] bits (Wait for response bits) */
hudakz 0:2cf53c219693 4617 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
hudakz 0:2cf53c219693 4618 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
hudakz 0:2cf53c219693 4619
hudakz 0:2cf53c219693 4620 #define SDIO_CMD_WAITINT_Pos (8U)
hudakz 0:2cf53c219693 4621 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4622 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!< CPSM Waits for Interrupt Request */
hudakz 0:2cf53c219693 4623 #define SDIO_CMD_WAITPEND_Pos (9U)
hudakz 0:2cf53c219693 4624 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4625 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
hudakz 0:2cf53c219693 4626 #define SDIO_CMD_CPSMEN_Pos (10U)
hudakz 0:2cf53c219693 4627 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4628 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!< Command path state machine (CPSM) Enable bit */
hudakz 0:2cf53c219693 4629 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
hudakz 0:2cf53c219693 4630 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4631 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!< SD I/O suspend command */
hudakz 0:2cf53c219693 4632 #define SDIO_CMD_ENCMDCOMPL_Pos (12U)
hudakz 0:2cf53c219693 4633 #define SDIO_CMD_ENCMDCOMPL_Msk (0x1U << SDIO_CMD_ENCMDCOMPL_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4634 #define SDIO_CMD_ENCMDCOMPL SDIO_CMD_ENCMDCOMPL_Msk /*!< Enable CMD completion */
hudakz 0:2cf53c219693 4635 #define SDIO_CMD_NIEN_Pos (13U)
hudakz 0:2cf53c219693 4636 #define SDIO_CMD_NIEN_Msk (0x1U << SDIO_CMD_NIEN_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4637 #define SDIO_CMD_NIEN SDIO_CMD_NIEN_Msk /*!< Not Interrupt Enable */
hudakz 0:2cf53c219693 4638 #define SDIO_CMD_CEATACMD_Pos (14U)
hudakz 0:2cf53c219693 4639 #define SDIO_CMD_CEATACMD_Msk (0x1U << SDIO_CMD_CEATACMD_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4640 #define SDIO_CMD_CEATACMD SDIO_CMD_CEATACMD_Msk /*!< CE-ATA command */
hudakz 0:2cf53c219693 4641
hudakz 0:2cf53c219693 4642 /***************** Bit definition for SDIO_RESPCMD register *****************/
hudakz 0:2cf53c219693 4643 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
hudakz 0:2cf53c219693 4644 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
hudakz 0:2cf53c219693 4645 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!< Response command index */
hudakz 0:2cf53c219693 4646
hudakz 0:2cf53c219693 4647 /****************** Bit definition for SDIO_RESP0 register ******************/
hudakz 0:2cf53c219693 4648 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
hudakz 0:2cf53c219693 4649 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4650 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!< Card Status */
hudakz 0:2cf53c219693 4651
hudakz 0:2cf53c219693 4652 /****************** Bit definition for SDIO_RESP1 register ******************/
hudakz 0:2cf53c219693 4653 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
hudakz 0:2cf53c219693 4654 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4655 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!< Card Status */
hudakz 0:2cf53c219693 4656
hudakz 0:2cf53c219693 4657 /****************** Bit definition for SDIO_RESP2 register ******************/
hudakz 0:2cf53c219693 4658 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
hudakz 0:2cf53c219693 4659 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4660 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!< Card Status */
hudakz 0:2cf53c219693 4661
hudakz 0:2cf53c219693 4662 /****************** Bit definition for SDIO_RESP3 register ******************/
hudakz 0:2cf53c219693 4663 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
hudakz 0:2cf53c219693 4664 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4665 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!< Card Status */
hudakz 0:2cf53c219693 4666
hudakz 0:2cf53c219693 4667 /****************** Bit definition for SDIO_RESP4 register ******************/
hudakz 0:2cf53c219693 4668 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
hudakz 0:2cf53c219693 4669 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4670 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!< Card Status */
hudakz 0:2cf53c219693 4671
hudakz 0:2cf53c219693 4672 /****************** Bit definition for SDIO_DTIMER register *****************/
hudakz 0:2cf53c219693 4673 #define SDIO_DTIMER_DATATIME_Pos (0U)
hudakz 0:2cf53c219693 4674 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4675 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!< Data timeout period. */
hudakz 0:2cf53c219693 4676
hudakz 0:2cf53c219693 4677 /****************** Bit definition for SDIO_DLEN register *******************/
hudakz 0:2cf53c219693 4678 #define SDIO_DLEN_DATALENGTH_Pos (0U)
hudakz 0:2cf53c219693 4679 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
hudakz 0:2cf53c219693 4680 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!< Data length value */
hudakz 0:2cf53c219693 4681
hudakz 0:2cf53c219693 4682 /****************** Bit definition for SDIO_DCTRL register ******************/
hudakz 0:2cf53c219693 4683 #define SDIO_DCTRL_DTEN_Pos (0U)
hudakz 0:2cf53c219693 4684 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4685 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!< Data transfer enabled bit */
hudakz 0:2cf53c219693 4686 #define SDIO_DCTRL_DTDIR_Pos (1U)
hudakz 0:2cf53c219693 4687 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4688 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!< Data transfer direction selection */
hudakz 0:2cf53c219693 4689 #define SDIO_DCTRL_DTMODE_Pos (2U)
hudakz 0:2cf53c219693 4690 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4691 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!< Data transfer mode selection */
hudakz 0:2cf53c219693 4692 #define SDIO_DCTRL_DMAEN_Pos (3U)
hudakz 0:2cf53c219693 4693 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4694 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!< DMA enabled bit */
hudakz 0:2cf53c219693 4695
hudakz 0:2cf53c219693 4696 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
hudakz 0:2cf53c219693 4697 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
hudakz 0:2cf53c219693 4698 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!< DBLOCKSIZE[3:0] bits (Data block size) */
hudakz 0:2cf53c219693 4699 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
hudakz 0:2cf53c219693 4700 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
hudakz 0:2cf53c219693 4701 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
hudakz 0:2cf53c219693 4702 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
hudakz 0:2cf53c219693 4703
hudakz 0:2cf53c219693 4704 #define SDIO_DCTRL_RWSTART_Pos (8U)
hudakz 0:2cf53c219693 4705 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4706 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!< Read wait start */
hudakz 0:2cf53c219693 4707 #define SDIO_DCTRL_RWSTOP_Pos (9U)
hudakz 0:2cf53c219693 4708 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4709 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!< Read wait stop */
hudakz 0:2cf53c219693 4710 #define SDIO_DCTRL_RWMOD_Pos (10U)
hudakz 0:2cf53c219693 4711 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4712 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!< Read wait mode */
hudakz 0:2cf53c219693 4713 #define SDIO_DCTRL_SDIOEN_Pos (11U)
hudakz 0:2cf53c219693 4714 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4715 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!< SD I/O enable functions */
hudakz 0:2cf53c219693 4716
hudakz 0:2cf53c219693 4717 /****************** Bit definition for SDIO_DCOUNT register *****************/
hudakz 0:2cf53c219693 4718 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
hudakz 0:2cf53c219693 4719 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
hudakz 0:2cf53c219693 4720 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!< Data count value */
hudakz 0:2cf53c219693 4721
hudakz 0:2cf53c219693 4722 /****************** Bit definition for SDIO_STA register ********************/
hudakz 0:2cf53c219693 4723 #define SDIO_STA_CCRCFAIL_Pos (0U)
hudakz 0:2cf53c219693 4724 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4725 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!< Command response received (CRC check failed) */
hudakz 0:2cf53c219693 4726 #define SDIO_STA_DCRCFAIL_Pos (1U)
hudakz 0:2cf53c219693 4727 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4728 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!< Data block sent/received (CRC check failed) */
hudakz 0:2cf53c219693 4729 #define SDIO_STA_CTIMEOUT_Pos (2U)
hudakz 0:2cf53c219693 4730 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4731 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!< Command response timeout */
hudakz 0:2cf53c219693 4732 #define SDIO_STA_DTIMEOUT_Pos (3U)
hudakz 0:2cf53c219693 4733 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4734 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!< Data timeout */
hudakz 0:2cf53c219693 4735 #define SDIO_STA_TXUNDERR_Pos (4U)
hudakz 0:2cf53c219693 4736 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4737 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!< Transmit FIFO underrun error */
hudakz 0:2cf53c219693 4738 #define SDIO_STA_RXOVERR_Pos (5U)
hudakz 0:2cf53c219693 4739 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4740 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!< Received FIFO overrun error */
hudakz 0:2cf53c219693 4741 #define SDIO_STA_CMDREND_Pos (6U)
hudakz 0:2cf53c219693 4742 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4743 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!< Command response received (CRC check passed) */
hudakz 0:2cf53c219693 4744 #define SDIO_STA_CMDSENT_Pos (7U)
hudakz 0:2cf53c219693 4745 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4746 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!< Command sent (no response required) */
hudakz 0:2cf53c219693 4747 #define SDIO_STA_DATAEND_Pos (8U)
hudakz 0:2cf53c219693 4748 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4749 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!< Data end (data counter, SDIDCOUNT, is zero) */
hudakz 0:2cf53c219693 4750 #define SDIO_STA_STBITERR_Pos (9U)
hudakz 0:2cf53c219693 4751 #define SDIO_STA_STBITERR_Msk (0x1U << SDIO_STA_STBITERR_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4752 #define SDIO_STA_STBITERR SDIO_STA_STBITERR_Msk /*!< Start bit not detected on all data signals in wide bus mode */
hudakz 0:2cf53c219693 4753 #define SDIO_STA_DBCKEND_Pos (10U)
hudakz 0:2cf53c219693 4754 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4755 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!< Data block sent/received (CRC check passed) */
hudakz 0:2cf53c219693 4756 #define SDIO_STA_CMDACT_Pos (11U)
hudakz 0:2cf53c219693 4757 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4758 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!< Command transfer in progress */
hudakz 0:2cf53c219693 4759 #define SDIO_STA_TXACT_Pos (12U)
hudakz 0:2cf53c219693 4760 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4761 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!< Data transmit in progress */
hudakz 0:2cf53c219693 4762 #define SDIO_STA_RXACT_Pos (13U)
hudakz 0:2cf53c219693 4763 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4764 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!< Data receive in progress */
hudakz 0:2cf53c219693 4765 #define SDIO_STA_TXFIFOHE_Pos (14U)
hudakz 0:2cf53c219693 4766 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4767 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
hudakz 0:2cf53c219693 4768 #define SDIO_STA_RXFIFOHF_Pos (15U)
hudakz 0:2cf53c219693 4769 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4770 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
hudakz 0:2cf53c219693 4771 #define SDIO_STA_TXFIFOF_Pos (16U)
hudakz 0:2cf53c219693 4772 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 4773 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!< Transmit FIFO full */
hudakz 0:2cf53c219693 4774 #define SDIO_STA_RXFIFOF_Pos (17U)
hudakz 0:2cf53c219693 4775 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 4776 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!< Receive FIFO full */
hudakz 0:2cf53c219693 4777 #define SDIO_STA_TXFIFOE_Pos (18U)
hudakz 0:2cf53c219693 4778 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 4779 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!< Transmit FIFO empty */
hudakz 0:2cf53c219693 4780 #define SDIO_STA_RXFIFOE_Pos (19U)
hudakz 0:2cf53c219693 4781 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 4782 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!< Receive FIFO empty */
hudakz 0:2cf53c219693 4783 #define SDIO_STA_TXDAVL_Pos (20U)
hudakz 0:2cf53c219693 4784 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 4785 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!< Data available in transmit FIFO */
hudakz 0:2cf53c219693 4786 #define SDIO_STA_RXDAVL_Pos (21U)
hudakz 0:2cf53c219693 4787 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 4788 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!< Data available in receive FIFO */
hudakz 0:2cf53c219693 4789 #define SDIO_STA_SDIOIT_Pos (22U)
hudakz 0:2cf53c219693 4790 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 4791 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!< SDIO interrupt received */
hudakz 0:2cf53c219693 4792 #define SDIO_STA_CEATAEND_Pos (23U)
hudakz 0:2cf53c219693 4793 #define SDIO_STA_CEATAEND_Msk (0x1U << SDIO_STA_CEATAEND_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 4794 #define SDIO_STA_CEATAEND SDIO_STA_CEATAEND_Msk /*!< CE-ATA command completion signal received for CMD61 */
hudakz 0:2cf53c219693 4795
hudakz 0:2cf53c219693 4796 /******************* Bit definition for SDIO_ICR register *******************/
hudakz 0:2cf53c219693 4797 #define SDIO_ICR_CCRCFAILC_Pos (0U)
hudakz 0:2cf53c219693 4798 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4799 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!< CCRCFAIL flag clear bit */
hudakz 0:2cf53c219693 4800 #define SDIO_ICR_DCRCFAILC_Pos (1U)
hudakz 0:2cf53c219693 4801 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4802 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!< DCRCFAIL flag clear bit */
hudakz 0:2cf53c219693 4803 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
hudakz 0:2cf53c219693 4804 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4805 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!< CTIMEOUT flag clear bit */
hudakz 0:2cf53c219693 4806 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
hudakz 0:2cf53c219693 4807 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4808 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!< DTIMEOUT flag clear bit */
hudakz 0:2cf53c219693 4809 #define SDIO_ICR_TXUNDERRC_Pos (4U)
hudakz 0:2cf53c219693 4810 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4811 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!< TXUNDERR flag clear bit */
hudakz 0:2cf53c219693 4812 #define SDIO_ICR_RXOVERRC_Pos (5U)
hudakz 0:2cf53c219693 4813 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4814 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!< RXOVERR flag clear bit */
hudakz 0:2cf53c219693 4815 #define SDIO_ICR_CMDRENDC_Pos (6U)
hudakz 0:2cf53c219693 4816 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4817 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!< CMDREND flag clear bit */
hudakz 0:2cf53c219693 4818 #define SDIO_ICR_CMDSENTC_Pos (7U)
hudakz 0:2cf53c219693 4819 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4820 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!< CMDSENT flag clear bit */
hudakz 0:2cf53c219693 4821 #define SDIO_ICR_DATAENDC_Pos (8U)
hudakz 0:2cf53c219693 4822 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4823 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!< DATAEND flag clear bit */
hudakz 0:2cf53c219693 4824 #define SDIO_ICR_STBITERRC_Pos (9U)
hudakz 0:2cf53c219693 4825 #define SDIO_ICR_STBITERRC_Msk (0x1U << SDIO_ICR_STBITERRC_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4826 #define SDIO_ICR_STBITERRC SDIO_ICR_STBITERRC_Msk /*!< STBITERR flag clear bit */
hudakz 0:2cf53c219693 4827 #define SDIO_ICR_DBCKENDC_Pos (10U)
hudakz 0:2cf53c219693 4828 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4829 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!< DBCKEND flag clear bit */
hudakz 0:2cf53c219693 4830 #define SDIO_ICR_SDIOITC_Pos (22U)
hudakz 0:2cf53c219693 4831 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 4832 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!< SDIOIT flag clear bit */
hudakz 0:2cf53c219693 4833 #define SDIO_ICR_CEATAENDC_Pos (23U)
hudakz 0:2cf53c219693 4834 #define SDIO_ICR_CEATAENDC_Msk (0x1U << SDIO_ICR_CEATAENDC_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 4835 #define SDIO_ICR_CEATAENDC SDIO_ICR_CEATAENDC_Msk /*!< CEATAEND flag clear bit */
hudakz 0:2cf53c219693 4836
hudakz 0:2cf53c219693 4837 /****************** Bit definition for SDIO_MASK register *******************/
hudakz 0:2cf53c219693 4838 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
hudakz 0:2cf53c219693 4839 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 4840 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!< Command CRC Fail Interrupt Enable */
hudakz 0:2cf53c219693 4841 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
hudakz 0:2cf53c219693 4842 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 4843 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!< Data CRC Fail Interrupt Enable */
hudakz 0:2cf53c219693 4844 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
hudakz 0:2cf53c219693 4845 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 4846 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!< Command TimeOut Interrupt Enable */
hudakz 0:2cf53c219693 4847 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
hudakz 0:2cf53c219693 4848 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 4849 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!< Data TimeOut Interrupt Enable */
hudakz 0:2cf53c219693 4850 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
hudakz 0:2cf53c219693 4851 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 4852 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!< Tx FIFO UnderRun Error Interrupt Enable */
hudakz 0:2cf53c219693 4853 #define SDIO_MASK_RXOVERRIE_Pos (5U)
hudakz 0:2cf53c219693 4854 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 4855 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!< Rx FIFO OverRun Error Interrupt Enable */
hudakz 0:2cf53c219693 4856 #define SDIO_MASK_CMDRENDIE_Pos (6U)
hudakz 0:2cf53c219693 4857 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4858 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!< Command Response Received Interrupt Enable */
hudakz 0:2cf53c219693 4859 #define SDIO_MASK_CMDSENTIE_Pos (7U)
hudakz 0:2cf53c219693 4860 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4861 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!< Command Sent Interrupt Enable */
hudakz 0:2cf53c219693 4862 #define SDIO_MASK_DATAENDIE_Pos (8U)
hudakz 0:2cf53c219693 4863 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4864 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!< Data End Interrupt Enable */
hudakz 0:2cf53c219693 4865 #define SDIO_MASK_STBITERRIE_Pos (9U)
hudakz 0:2cf53c219693 4866 #define SDIO_MASK_STBITERRIE_Msk (0x1U << SDIO_MASK_STBITERRIE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 4867 #define SDIO_MASK_STBITERRIE SDIO_MASK_STBITERRIE_Msk /*!< Start Bit Error Interrupt Enable */
hudakz 0:2cf53c219693 4868 #define SDIO_MASK_DBCKENDIE_Pos (10U)
hudakz 0:2cf53c219693 4869 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 4870 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!< Data Block End Interrupt Enable */
hudakz 0:2cf53c219693 4871 #define SDIO_MASK_CMDACTIE_Pos (11U)
hudakz 0:2cf53c219693 4872 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4873 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!< Command Acting Interrupt Enable */
hudakz 0:2cf53c219693 4874 #define SDIO_MASK_TXACTIE_Pos (12U)
hudakz 0:2cf53c219693 4875 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 4876 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!< Data Transmit Acting Interrupt Enable */
hudakz 0:2cf53c219693 4877 #define SDIO_MASK_RXACTIE_Pos (13U)
hudakz 0:2cf53c219693 4878 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 4879 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!< Data receive acting interrupt enabled */
hudakz 0:2cf53c219693 4880 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
hudakz 0:2cf53c219693 4881 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4882 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!< Tx FIFO Half Empty interrupt Enable */
hudakz 0:2cf53c219693 4883 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
hudakz 0:2cf53c219693 4884 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4885 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!< Rx FIFO Half Full interrupt Enable */
hudakz 0:2cf53c219693 4886 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
hudakz 0:2cf53c219693 4887 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 4888 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!< Tx FIFO Full interrupt Enable */
hudakz 0:2cf53c219693 4889 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
hudakz 0:2cf53c219693 4890 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 4891 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!< Rx FIFO Full interrupt Enable */
hudakz 0:2cf53c219693 4892 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
hudakz 0:2cf53c219693 4893 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 4894 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!< Tx FIFO Empty interrupt Enable */
hudakz 0:2cf53c219693 4895 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
hudakz 0:2cf53c219693 4896 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 4897 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!< Rx FIFO Empty interrupt Enable */
hudakz 0:2cf53c219693 4898 #define SDIO_MASK_TXDAVLIE_Pos (20U)
hudakz 0:2cf53c219693 4899 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 4900 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!< Data available in Tx FIFO interrupt Enable */
hudakz 0:2cf53c219693 4901 #define SDIO_MASK_RXDAVLIE_Pos (21U)
hudakz 0:2cf53c219693 4902 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 4903 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!< Data available in Rx FIFO interrupt Enable */
hudakz 0:2cf53c219693 4904 #define SDIO_MASK_SDIOITIE_Pos (22U)
hudakz 0:2cf53c219693 4905 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 4906 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!< SDIO Mode Interrupt Received interrupt Enable */
hudakz 0:2cf53c219693 4907 #define SDIO_MASK_CEATAENDIE_Pos (23U)
hudakz 0:2cf53c219693 4908 #define SDIO_MASK_CEATAENDIE_Msk (0x1U << SDIO_MASK_CEATAENDIE_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 4909 #define SDIO_MASK_CEATAENDIE SDIO_MASK_CEATAENDIE_Msk /*!< CE-ATA command completion signal received Interrupt Enable */
hudakz 0:2cf53c219693 4910
hudakz 0:2cf53c219693 4911 /***************** Bit definition for SDIO_FIFOCNT register *****************/
hudakz 0:2cf53c219693 4912 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
hudakz 0:2cf53c219693 4913 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
hudakz 0:2cf53c219693 4914 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!< Remaining number of words to be written to or read from the FIFO */
hudakz 0:2cf53c219693 4915
hudakz 0:2cf53c219693 4916 /****************** Bit definition for SDIO_FIFO register *******************/
hudakz 0:2cf53c219693 4917 #define SDIO_FIFO_FIFODATA_Pos (0U)
hudakz 0:2cf53c219693 4918 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 4919 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!< Receive and transmit FIFO data */
hudakz 0:2cf53c219693 4920
hudakz 0:2cf53c219693 4921 /******************************************************************************/
hudakz 0:2cf53c219693 4922 /* */
hudakz 0:2cf53c219693 4923 /* USB Device FS */
hudakz 0:2cf53c219693 4924 /* */
hudakz 0:2cf53c219693 4925 /******************************************************************************/
hudakz 0:2cf53c219693 4926
hudakz 0:2cf53c219693 4927 /*!< Endpoint-specific registers */
hudakz 0:2cf53c219693 4928 #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
hudakz 0:2cf53c219693 4929 #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
hudakz 0:2cf53c219693 4930 #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
hudakz 0:2cf53c219693 4931 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
hudakz 0:2cf53c219693 4932 #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
hudakz 0:2cf53c219693 4933 #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
hudakz 0:2cf53c219693 4934 #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
hudakz 0:2cf53c219693 4935 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
hudakz 0:2cf53c219693 4936
hudakz 0:2cf53c219693 4937 /* bit positions */
hudakz 0:2cf53c219693 4938 #define USB_EP_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 4939 #define USB_EP_CTR_RX_Msk (0x1U << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 4940 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
hudakz 0:2cf53c219693 4941 #define USB_EP_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 4942 #define USB_EP_DTOG_RX_Msk (0x1U << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 4943 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
hudakz 0:2cf53c219693 4944 #define USB_EPRX_STAT_Pos (12U)
hudakz 0:2cf53c219693 4945 #define USB_EPRX_STAT_Msk (0x3U << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 4946 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
hudakz 0:2cf53c219693 4947 #define USB_EP_SETUP_Pos (11U)
hudakz 0:2cf53c219693 4948 #define USB_EP_SETUP_Msk (0x1U << USB_EP_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 4949 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
hudakz 0:2cf53c219693 4950 #define USB_EP_T_FIELD_Pos (9U)
hudakz 0:2cf53c219693 4951 #define USB_EP_T_FIELD_Msk (0x3U << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 4952 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
hudakz 0:2cf53c219693 4953 #define USB_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 4954 #define USB_EP_KIND_Msk (0x1U << USB_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 4955 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
hudakz 0:2cf53c219693 4956 #define USB_EP_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 4957 #define USB_EP_CTR_TX_Msk (0x1U << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 4958 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
hudakz 0:2cf53c219693 4959 #define USB_EP_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 4960 #define USB_EP_DTOG_TX_Msk (0x1U << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 4961 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
hudakz 0:2cf53c219693 4962 #define USB_EPTX_STAT_Pos (4U)
hudakz 0:2cf53c219693 4963 #define USB_EPTX_STAT_Msk (0x3U << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 4964 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
hudakz 0:2cf53c219693 4965 #define USB_EPADDR_FIELD_Pos (0U)
hudakz 0:2cf53c219693 4966 #define USB_EPADDR_FIELD_Msk (0xFU << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 4967 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
hudakz 0:2cf53c219693 4968
hudakz 0:2cf53c219693 4969 /* EndPoint REGister MASK (no toggle fields) */
hudakz 0:2cf53c219693 4970 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
hudakz 0:2cf53c219693 4971 /*!< EP_TYPE[1:0] EndPoint TYPE */
hudakz 0:2cf53c219693 4972 #define USB_EP_TYPE_MASK_Pos (9U)
hudakz 0:2cf53c219693 4973 #define USB_EP_TYPE_MASK_Msk (0x3U << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 4974 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
hudakz 0:2cf53c219693 4975 #define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
hudakz 0:2cf53c219693 4976 #define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
hudakz 0:2cf53c219693 4977 #define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
hudakz 0:2cf53c219693 4978 #define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
hudakz 0:2cf53c219693 4979 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
hudakz 0:2cf53c219693 4980
hudakz 0:2cf53c219693 4981 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
hudakz 0:2cf53c219693 4982 /*!< STAT_TX[1:0] STATus for TX transfer */
hudakz 0:2cf53c219693 4983 #define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
hudakz 0:2cf53c219693 4984 #define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
hudakz 0:2cf53c219693 4985 #define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
hudakz 0:2cf53c219693 4986 #define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
hudakz 0:2cf53c219693 4987 #define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
hudakz 0:2cf53c219693 4988 #define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
hudakz 0:2cf53c219693 4989 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
hudakz 0:2cf53c219693 4990 /*!< STAT_RX[1:0] STATus for RX transfer */
hudakz 0:2cf53c219693 4991 #define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
hudakz 0:2cf53c219693 4992 #define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
hudakz 0:2cf53c219693 4993 #define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
hudakz 0:2cf53c219693 4994 #define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
hudakz 0:2cf53c219693 4995 #define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
hudakz 0:2cf53c219693 4996 #define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
hudakz 0:2cf53c219693 4997 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
hudakz 0:2cf53c219693 4998
hudakz 0:2cf53c219693 4999 /******************* Bit definition for USB_EP0R register *******************/
hudakz 0:2cf53c219693 5000 #define USB_EP0R_EA_Pos (0U)
hudakz 0:2cf53c219693 5001 #define USB_EP0R_EA_Msk (0xFU << USB_EP0R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5002 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5003
hudakz 0:2cf53c219693 5004 #define USB_EP0R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5005 #define USB_EP0R_STAT_TX_Msk (0x3U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5006 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5007 #define USB_EP0R_STAT_TX_0 (0x1U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5008 #define USB_EP0R_STAT_TX_1 (0x2U << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5009
hudakz 0:2cf53c219693 5010 #define USB_EP0R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5011 #define USB_EP0R_DTOG_TX_Msk (0x1U << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5012 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5013 #define USB_EP0R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5014 #define USB_EP0R_CTR_TX_Msk (0x1U << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5015 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5016 #define USB_EP0R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5017 #define USB_EP0R_EP_KIND_Msk (0x1U << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5018 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5019
hudakz 0:2cf53c219693 5020 #define USB_EP0R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5021 #define USB_EP0R_EP_TYPE_Msk (0x3U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5022 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5023 #define USB_EP0R_EP_TYPE_0 (0x1U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5024 #define USB_EP0R_EP_TYPE_1 (0x2U << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5025
hudakz 0:2cf53c219693 5026 #define USB_EP0R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5027 #define USB_EP0R_SETUP_Msk (0x1U << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5028 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5029
hudakz 0:2cf53c219693 5030 #define USB_EP0R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5031 #define USB_EP0R_STAT_RX_Msk (0x3U << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5032 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5033 #define USB_EP0R_STAT_RX_0 (0x1U << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5034 #define USB_EP0R_STAT_RX_1 (0x2U << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5035
hudakz 0:2cf53c219693 5036 #define USB_EP0R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5037 #define USB_EP0R_DTOG_RX_Msk (0x1U << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5038 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5039 #define USB_EP0R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5040 #define USB_EP0R_CTR_RX_Msk (0x1U << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5041 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5042
hudakz 0:2cf53c219693 5043 /******************* Bit definition for USB_EP1R register *******************/
hudakz 0:2cf53c219693 5044 #define USB_EP1R_EA_Pos (0U)
hudakz 0:2cf53c219693 5045 #define USB_EP1R_EA_Msk (0xFU << USB_EP1R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5046 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5047
hudakz 0:2cf53c219693 5048 #define USB_EP1R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5049 #define USB_EP1R_STAT_TX_Msk (0x3U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5050 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5051 #define USB_EP1R_STAT_TX_0 (0x1U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5052 #define USB_EP1R_STAT_TX_1 (0x2U << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5053
hudakz 0:2cf53c219693 5054 #define USB_EP1R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5055 #define USB_EP1R_DTOG_TX_Msk (0x1U << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5056 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5057 #define USB_EP1R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5058 #define USB_EP1R_CTR_TX_Msk (0x1U << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5059 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5060 #define USB_EP1R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5061 #define USB_EP1R_EP_KIND_Msk (0x1U << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5062 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5063
hudakz 0:2cf53c219693 5064 #define USB_EP1R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5065 #define USB_EP1R_EP_TYPE_Msk (0x3U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5066 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5067 #define USB_EP1R_EP_TYPE_0 (0x1U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5068 #define USB_EP1R_EP_TYPE_1 (0x2U << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5069
hudakz 0:2cf53c219693 5070 #define USB_EP1R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5071 #define USB_EP1R_SETUP_Msk (0x1U << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5072 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5073
hudakz 0:2cf53c219693 5074 #define USB_EP1R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5075 #define USB_EP1R_STAT_RX_Msk (0x3U << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5076 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5077 #define USB_EP1R_STAT_RX_0 (0x1U << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5078 #define USB_EP1R_STAT_RX_1 (0x2U << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5079
hudakz 0:2cf53c219693 5080 #define USB_EP1R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5081 #define USB_EP1R_DTOG_RX_Msk (0x1U << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5082 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5083 #define USB_EP1R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5084 #define USB_EP1R_CTR_RX_Msk (0x1U << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5085 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5086
hudakz 0:2cf53c219693 5087 /******************* Bit definition for USB_EP2R register *******************/
hudakz 0:2cf53c219693 5088 #define USB_EP2R_EA_Pos (0U)
hudakz 0:2cf53c219693 5089 #define USB_EP2R_EA_Msk (0xFU << USB_EP2R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5090 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5091
hudakz 0:2cf53c219693 5092 #define USB_EP2R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5093 #define USB_EP2R_STAT_TX_Msk (0x3U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5094 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5095 #define USB_EP2R_STAT_TX_0 (0x1U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5096 #define USB_EP2R_STAT_TX_1 (0x2U << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5097
hudakz 0:2cf53c219693 5098 #define USB_EP2R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5099 #define USB_EP2R_DTOG_TX_Msk (0x1U << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5100 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5101 #define USB_EP2R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5102 #define USB_EP2R_CTR_TX_Msk (0x1U << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5103 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5104 #define USB_EP2R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5105 #define USB_EP2R_EP_KIND_Msk (0x1U << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5106 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5107
hudakz 0:2cf53c219693 5108 #define USB_EP2R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5109 #define USB_EP2R_EP_TYPE_Msk (0x3U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5110 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5111 #define USB_EP2R_EP_TYPE_0 (0x1U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5112 #define USB_EP2R_EP_TYPE_1 (0x2U << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5113
hudakz 0:2cf53c219693 5114 #define USB_EP2R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5115 #define USB_EP2R_SETUP_Msk (0x1U << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5116 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5117
hudakz 0:2cf53c219693 5118 #define USB_EP2R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5119 #define USB_EP2R_STAT_RX_Msk (0x3U << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5120 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5121 #define USB_EP2R_STAT_RX_0 (0x1U << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5122 #define USB_EP2R_STAT_RX_1 (0x2U << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5123
hudakz 0:2cf53c219693 5124 #define USB_EP2R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5125 #define USB_EP2R_DTOG_RX_Msk (0x1U << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5126 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5127 #define USB_EP2R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5128 #define USB_EP2R_CTR_RX_Msk (0x1U << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5129 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5130
hudakz 0:2cf53c219693 5131 /******************* Bit definition for USB_EP3R register *******************/
hudakz 0:2cf53c219693 5132 #define USB_EP3R_EA_Pos (0U)
hudakz 0:2cf53c219693 5133 #define USB_EP3R_EA_Msk (0xFU << USB_EP3R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5134 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5135
hudakz 0:2cf53c219693 5136 #define USB_EP3R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5137 #define USB_EP3R_STAT_TX_Msk (0x3U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5138 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5139 #define USB_EP3R_STAT_TX_0 (0x1U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5140 #define USB_EP3R_STAT_TX_1 (0x2U << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5141
hudakz 0:2cf53c219693 5142 #define USB_EP3R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5143 #define USB_EP3R_DTOG_TX_Msk (0x1U << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5144 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5145 #define USB_EP3R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5146 #define USB_EP3R_CTR_TX_Msk (0x1U << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5147 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5148 #define USB_EP3R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5149 #define USB_EP3R_EP_KIND_Msk (0x1U << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5150 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5151
hudakz 0:2cf53c219693 5152 #define USB_EP3R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5153 #define USB_EP3R_EP_TYPE_Msk (0x3U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5154 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5155 #define USB_EP3R_EP_TYPE_0 (0x1U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5156 #define USB_EP3R_EP_TYPE_1 (0x2U << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5157
hudakz 0:2cf53c219693 5158 #define USB_EP3R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5159 #define USB_EP3R_SETUP_Msk (0x1U << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5160 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5161
hudakz 0:2cf53c219693 5162 #define USB_EP3R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5163 #define USB_EP3R_STAT_RX_Msk (0x3U << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5164 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5165 #define USB_EP3R_STAT_RX_0 (0x1U << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5166 #define USB_EP3R_STAT_RX_1 (0x2U << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5167
hudakz 0:2cf53c219693 5168 #define USB_EP3R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5169 #define USB_EP3R_DTOG_RX_Msk (0x1U << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5170 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5171 #define USB_EP3R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5172 #define USB_EP3R_CTR_RX_Msk (0x1U << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5173 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5174
hudakz 0:2cf53c219693 5175 /******************* Bit definition for USB_EP4R register *******************/
hudakz 0:2cf53c219693 5176 #define USB_EP4R_EA_Pos (0U)
hudakz 0:2cf53c219693 5177 #define USB_EP4R_EA_Msk (0xFU << USB_EP4R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5178 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5179
hudakz 0:2cf53c219693 5180 #define USB_EP4R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5181 #define USB_EP4R_STAT_TX_Msk (0x3U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5182 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5183 #define USB_EP4R_STAT_TX_0 (0x1U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5184 #define USB_EP4R_STAT_TX_1 (0x2U << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5185
hudakz 0:2cf53c219693 5186 #define USB_EP4R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5187 #define USB_EP4R_DTOG_TX_Msk (0x1U << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5188 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5189 #define USB_EP4R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5190 #define USB_EP4R_CTR_TX_Msk (0x1U << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5191 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5192 #define USB_EP4R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5193 #define USB_EP4R_EP_KIND_Msk (0x1U << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5194 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5195
hudakz 0:2cf53c219693 5196 #define USB_EP4R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5197 #define USB_EP4R_EP_TYPE_Msk (0x3U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5198 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5199 #define USB_EP4R_EP_TYPE_0 (0x1U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5200 #define USB_EP4R_EP_TYPE_1 (0x2U << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5201
hudakz 0:2cf53c219693 5202 #define USB_EP4R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5203 #define USB_EP4R_SETUP_Msk (0x1U << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5204 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5205
hudakz 0:2cf53c219693 5206 #define USB_EP4R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5207 #define USB_EP4R_STAT_RX_Msk (0x3U << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5208 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5209 #define USB_EP4R_STAT_RX_0 (0x1U << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5210 #define USB_EP4R_STAT_RX_1 (0x2U << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5211
hudakz 0:2cf53c219693 5212 #define USB_EP4R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5213 #define USB_EP4R_DTOG_RX_Msk (0x1U << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5214 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5215 #define USB_EP4R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5216 #define USB_EP4R_CTR_RX_Msk (0x1U << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5217 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5218
hudakz 0:2cf53c219693 5219 /******************* Bit definition for USB_EP5R register *******************/
hudakz 0:2cf53c219693 5220 #define USB_EP5R_EA_Pos (0U)
hudakz 0:2cf53c219693 5221 #define USB_EP5R_EA_Msk (0xFU << USB_EP5R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5222 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5223
hudakz 0:2cf53c219693 5224 #define USB_EP5R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5225 #define USB_EP5R_STAT_TX_Msk (0x3U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5226 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5227 #define USB_EP5R_STAT_TX_0 (0x1U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5228 #define USB_EP5R_STAT_TX_1 (0x2U << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5229
hudakz 0:2cf53c219693 5230 #define USB_EP5R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5231 #define USB_EP5R_DTOG_TX_Msk (0x1U << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5232 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5233 #define USB_EP5R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5234 #define USB_EP5R_CTR_TX_Msk (0x1U << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5235 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5236 #define USB_EP5R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5237 #define USB_EP5R_EP_KIND_Msk (0x1U << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5238 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5239
hudakz 0:2cf53c219693 5240 #define USB_EP5R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5241 #define USB_EP5R_EP_TYPE_Msk (0x3U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5242 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5243 #define USB_EP5R_EP_TYPE_0 (0x1U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5244 #define USB_EP5R_EP_TYPE_1 (0x2U << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5245
hudakz 0:2cf53c219693 5246 #define USB_EP5R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5247 #define USB_EP5R_SETUP_Msk (0x1U << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5248 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5249
hudakz 0:2cf53c219693 5250 #define USB_EP5R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5251 #define USB_EP5R_STAT_RX_Msk (0x3U << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5252 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5253 #define USB_EP5R_STAT_RX_0 (0x1U << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5254 #define USB_EP5R_STAT_RX_1 (0x2U << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5255
hudakz 0:2cf53c219693 5256 #define USB_EP5R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5257 #define USB_EP5R_DTOG_RX_Msk (0x1U << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5258 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5259 #define USB_EP5R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5260 #define USB_EP5R_CTR_RX_Msk (0x1U << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5261 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5262
hudakz 0:2cf53c219693 5263 /******************* Bit definition for USB_EP6R register *******************/
hudakz 0:2cf53c219693 5264 #define USB_EP6R_EA_Pos (0U)
hudakz 0:2cf53c219693 5265 #define USB_EP6R_EA_Msk (0xFU << USB_EP6R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5266 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5267
hudakz 0:2cf53c219693 5268 #define USB_EP6R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5269 #define USB_EP6R_STAT_TX_Msk (0x3U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5270 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5271 #define USB_EP6R_STAT_TX_0 (0x1U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5272 #define USB_EP6R_STAT_TX_1 (0x2U << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5273
hudakz 0:2cf53c219693 5274 #define USB_EP6R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5275 #define USB_EP6R_DTOG_TX_Msk (0x1U << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5276 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5277 #define USB_EP6R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5278 #define USB_EP6R_CTR_TX_Msk (0x1U << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5279 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5280 #define USB_EP6R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5281 #define USB_EP6R_EP_KIND_Msk (0x1U << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5282 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5283
hudakz 0:2cf53c219693 5284 #define USB_EP6R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5285 #define USB_EP6R_EP_TYPE_Msk (0x3U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5286 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5287 #define USB_EP6R_EP_TYPE_0 (0x1U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5288 #define USB_EP6R_EP_TYPE_1 (0x2U << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5289
hudakz 0:2cf53c219693 5290 #define USB_EP6R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5291 #define USB_EP6R_SETUP_Msk (0x1U << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5292 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5293
hudakz 0:2cf53c219693 5294 #define USB_EP6R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5295 #define USB_EP6R_STAT_RX_Msk (0x3U << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5296 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5297 #define USB_EP6R_STAT_RX_0 (0x1U << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5298 #define USB_EP6R_STAT_RX_1 (0x2U << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5299
hudakz 0:2cf53c219693 5300 #define USB_EP6R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5301 #define USB_EP6R_DTOG_RX_Msk (0x1U << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5302 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5303 #define USB_EP6R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5304 #define USB_EP6R_CTR_RX_Msk (0x1U << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5305 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5306
hudakz 0:2cf53c219693 5307 /******************* Bit definition for USB_EP7R register *******************/
hudakz 0:2cf53c219693 5308 #define USB_EP7R_EA_Pos (0U)
hudakz 0:2cf53c219693 5309 #define USB_EP7R_EA_Msk (0xFU << USB_EP7R_EA_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5310 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
hudakz 0:2cf53c219693 5311
hudakz 0:2cf53c219693 5312 #define USB_EP7R_STAT_TX_Pos (4U)
hudakz 0:2cf53c219693 5313 #define USB_EP7R_STAT_TX_Msk (0x3U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
hudakz 0:2cf53c219693 5314 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
hudakz 0:2cf53c219693 5315 #define USB_EP7R_STAT_TX_0 (0x1U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5316 #define USB_EP7R_STAT_TX_1 (0x2U << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5317
hudakz 0:2cf53c219693 5318 #define USB_EP7R_DTOG_TX_Pos (6U)
hudakz 0:2cf53c219693 5319 #define USB_EP7R_DTOG_TX_Msk (0x1U << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5320 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
hudakz 0:2cf53c219693 5321 #define USB_EP7R_CTR_TX_Pos (7U)
hudakz 0:2cf53c219693 5322 #define USB_EP7R_CTR_TX_Msk (0x1U << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5323 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
hudakz 0:2cf53c219693 5324 #define USB_EP7R_EP_KIND_Pos (8U)
hudakz 0:2cf53c219693 5325 #define USB_EP7R_EP_KIND_Msk (0x1U << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5326 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
hudakz 0:2cf53c219693 5327
hudakz 0:2cf53c219693 5328 #define USB_EP7R_EP_TYPE_Pos (9U)
hudakz 0:2cf53c219693 5329 #define USB_EP7R_EP_TYPE_Msk (0x3U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
hudakz 0:2cf53c219693 5330 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
hudakz 0:2cf53c219693 5331 #define USB_EP7R_EP_TYPE_0 (0x1U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5332 #define USB_EP7R_EP_TYPE_1 (0x2U << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5333
hudakz 0:2cf53c219693 5334 #define USB_EP7R_SETUP_Pos (11U)
hudakz 0:2cf53c219693 5335 #define USB_EP7R_SETUP_Msk (0x1U << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5336 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
hudakz 0:2cf53c219693 5337
hudakz 0:2cf53c219693 5338 #define USB_EP7R_STAT_RX_Pos (12U)
hudakz 0:2cf53c219693 5339 #define USB_EP7R_STAT_RX_Msk (0x3U << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 5340 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
hudakz 0:2cf53c219693 5341 #define USB_EP7R_STAT_RX_0 (0x1U << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5342 #define USB_EP7R_STAT_RX_1 (0x2U << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5343
hudakz 0:2cf53c219693 5344 #define USB_EP7R_DTOG_RX_Pos (14U)
hudakz 0:2cf53c219693 5345 #define USB_EP7R_DTOG_RX_Msk (0x1U << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5346 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
hudakz 0:2cf53c219693 5347 #define USB_EP7R_CTR_RX_Pos (15U)
hudakz 0:2cf53c219693 5348 #define USB_EP7R_CTR_RX_Msk (0x1U << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5349 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
hudakz 0:2cf53c219693 5350
hudakz 0:2cf53c219693 5351 /*!< Common registers */
hudakz 0:2cf53c219693 5352 /******************* Bit definition for USB_CNTR register *******************/
hudakz 0:2cf53c219693 5353 #define USB_CNTR_FRES_Pos (0U)
hudakz 0:2cf53c219693 5354 #define USB_CNTR_FRES_Msk (0x1U << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 5355 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
hudakz 0:2cf53c219693 5356 #define USB_CNTR_PDWN_Pos (1U)
hudakz 0:2cf53c219693 5357 #define USB_CNTR_PDWN_Msk (0x1U << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 5358 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
hudakz 0:2cf53c219693 5359 #define USB_CNTR_LP_MODE_Pos (2U)
hudakz 0:2cf53c219693 5360 #define USB_CNTR_LP_MODE_Msk (0x1U << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 5361 #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
hudakz 0:2cf53c219693 5362 #define USB_CNTR_FSUSP_Pos (3U)
hudakz 0:2cf53c219693 5363 #define USB_CNTR_FSUSP_Msk (0x1U << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 5364 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
hudakz 0:2cf53c219693 5365 #define USB_CNTR_RESUME_Pos (4U)
hudakz 0:2cf53c219693 5366 #define USB_CNTR_RESUME_Msk (0x1U << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5367 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
hudakz 0:2cf53c219693 5368 #define USB_CNTR_ESOFM_Pos (8U)
hudakz 0:2cf53c219693 5369 #define USB_CNTR_ESOFM_Msk (0x1U << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5370 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
hudakz 0:2cf53c219693 5371 #define USB_CNTR_SOFM_Pos (9U)
hudakz 0:2cf53c219693 5372 #define USB_CNTR_SOFM_Msk (0x1U << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5373 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
hudakz 0:2cf53c219693 5374 #define USB_CNTR_RESETM_Pos (10U)
hudakz 0:2cf53c219693 5375 #define USB_CNTR_RESETM_Msk (0x1U << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5376 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
hudakz 0:2cf53c219693 5377 #define USB_CNTR_SUSPM_Pos (11U)
hudakz 0:2cf53c219693 5378 #define USB_CNTR_SUSPM_Msk (0x1U << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5379 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
hudakz 0:2cf53c219693 5380 #define USB_CNTR_WKUPM_Pos (12U)
hudakz 0:2cf53c219693 5381 #define USB_CNTR_WKUPM_Msk (0x1U << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5382 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
hudakz 0:2cf53c219693 5383 #define USB_CNTR_ERRM_Pos (13U)
hudakz 0:2cf53c219693 5384 #define USB_CNTR_ERRM_Msk (0x1U << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5385 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
hudakz 0:2cf53c219693 5386 #define USB_CNTR_PMAOVRM_Pos (14U)
hudakz 0:2cf53c219693 5387 #define USB_CNTR_PMAOVRM_Msk (0x1U << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5388 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
hudakz 0:2cf53c219693 5389 #define USB_CNTR_CTRM_Pos (15U)
hudakz 0:2cf53c219693 5390 #define USB_CNTR_CTRM_Msk (0x1U << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5391 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
hudakz 0:2cf53c219693 5392
hudakz 0:2cf53c219693 5393 /******************* Bit definition for USB_ISTR register *******************/
hudakz 0:2cf53c219693 5394 #define USB_ISTR_EP_ID_Pos (0U)
hudakz 0:2cf53c219693 5395 #define USB_ISTR_EP_ID_Msk (0xFU << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 5396 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
hudakz 0:2cf53c219693 5397 #define USB_ISTR_DIR_Pos (4U)
hudakz 0:2cf53c219693 5398 #define USB_ISTR_DIR_Msk (0x1U << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5399 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
hudakz 0:2cf53c219693 5400 #define USB_ISTR_ESOF_Pos (8U)
hudakz 0:2cf53c219693 5401 #define USB_ISTR_ESOF_Msk (0x1U << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 5402 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
hudakz 0:2cf53c219693 5403 #define USB_ISTR_SOF_Pos (9U)
hudakz 0:2cf53c219693 5404 #define USB_ISTR_SOF_Msk (0x1U << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 5405 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
hudakz 0:2cf53c219693 5406 #define USB_ISTR_RESET_Pos (10U)
hudakz 0:2cf53c219693 5407 #define USB_ISTR_RESET_Msk (0x1U << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5408 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
hudakz 0:2cf53c219693 5409 #define USB_ISTR_SUSP_Pos (11U)
hudakz 0:2cf53c219693 5410 #define USB_ISTR_SUSP_Msk (0x1U << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5411 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
hudakz 0:2cf53c219693 5412 #define USB_ISTR_WKUP_Pos (12U)
hudakz 0:2cf53c219693 5413 #define USB_ISTR_WKUP_Msk (0x1U << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5414 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
hudakz 0:2cf53c219693 5415 #define USB_ISTR_ERR_Pos (13U)
hudakz 0:2cf53c219693 5416 #define USB_ISTR_ERR_Msk (0x1U << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5417 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
hudakz 0:2cf53c219693 5418 #define USB_ISTR_PMAOVR_Pos (14U)
hudakz 0:2cf53c219693 5419 #define USB_ISTR_PMAOVR_Msk (0x1U << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5420 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
hudakz 0:2cf53c219693 5421 #define USB_ISTR_CTR_Pos (15U)
hudakz 0:2cf53c219693 5422 #define USB_ISTR_CTR_Msk (0x1U << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5423 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
hudakz 0:2cf53c219693 5424
hudakz 0:2cf53c219693 5425 /******************* Bit definition for USB_FNR register ********************/
hudakz 0:2cf53c219693 5426 #define USB_FNR_FN_Pos (0U)
hudakz 0:2cf53c219693 5427 #define USB_FNR_FN_Msk (0x7FFU << USB_FNR_FN_Pos) /*!< 0x000007FF */
hudakz 0:2cf53c219693 5428 #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
hudakz 0:2cf53c219693 5429 #define USB_FNR_LSOF_Pos (11U)
hudakz 0:2cf53c219693 5430 #define USB_FNR_LSOF_Msk (0x3U << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
hudakz 0:2cf53c219693 5431 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
hudakz 0:2cf53c219693 5432 #define USB_FNR_LCK_Pos (13U)
hudakz 0:2cf53c219693 5433 #define USB_FNR_LCK_Msk (0x1U << USB_FNR_LCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5434 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
hudakz 0:2cf53c219693 5435 #define USB_FNR_RXDM_Pos (14U)
hudakz 0:2cf53c219693 5436 #define USB_FNR_RXDM_Msk (0x1U << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5437 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
hudakz 0:2cf53c219693 5438 #define USB_FNR_RXDP_Pos (15U)
hudakz 0:2cf53c219693 5439 #define USB_FNR_RXDP_Msk (0x1U << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5440 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
hudakz 0:2cf53c219693 5441
hudakz 0:2cf53c219693 5442 /****************** Bit definition for USB_DADDR register *******************/
hudakz 0:2cf53c219693 5443 #define USB_DADDR_ADD_Pos (0U)
hudakz 0:2cf53c219693 5444 #define USB_DADDR_ADD_Msk (0x7FU << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
hudakz 0:2cf53c219693 5445 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
hudakz 0:2cf53c219693 5446 #define USB_DADDR_ADD0_Pos (0U)
hudakz 0:2cf53c219693 5447 #define USB_DADDR_ADD0_Msk (0x1U << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 5448 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
hudakz 0:2cf53c219693 5449 #define USB_DADDR_ADD1_Pos (1U)
hudakz 0:2cf53c219693 5450 #define USB_DADDR_ADD1_Msk (0x1U << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 5451 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
hudakz 0:2cf53c219693 5452 #define USB_DADDR_ADD2_Pos (2U)
hudakz 0:2cf53c219693 5453 #define USB_DADDR_ADD2_Msk (0x1U << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 5454 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
hudakz 0:2cf53c219693 5455 #define USB_DADDR_ADD3_Pos (3U)
hudakz 0:2cf53c219693 5456 #define USB_DADDR_ADD3_Msk (0x1U << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 5457 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
hudakz 0:2cf53c219693 5458 #define USB_DADDR_ADD4_Pos (4U)
hudakz 0:2cf53c219693 5459 #define USB_DADDR_ADD4_Msk (0x1U << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 5460 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
hudakz 0:2cf53c219693 5461 #define USB_DADDR_ADD5_Pos (5U)
hudakz 0:2cf53c219693 5462 #define USB_DADDR_ADD5_Msk (0x1U << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 5463 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
hudakz 0:2cf53c219693 5464 #define USB_DADDR_ADD6_Pos (6U)
hudakz 0:2cf53c219693 5465 #define USB_DADDR_ADD6_Msk (0x1U << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 5466 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
hudakz 0:2cf53c219693 5467
hudakz 0:2cf53c219693 5468 #define USB_DADDR_EF_Pos (7U)
hudakz 0:2cf53c219693 5469 #define USB_DADDR_EF_Msk (0x1U << USB_DADDR_EF_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 5470 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
hudakz 0:2cf53c219693 5471
hudakz 0:2cf53c219693 5472 /****************** Bit definition for USB_BTABLE register ******************/
hudakz 0:2cf53c219693 5473 #define USB_BTABLE_BTABLE_Pos (3U)
hudakz 0:2cf53c219693 5474 #define USB_BTABLE_BTABLE_Msk (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
hudakz 0:2cf53c219693 5475 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
hudakz 0:2cf53c219693 5476
hudakz 0:2cf53c219693 5477 /*!< Buffer descriptor table */
hudakz 0:2cf53c219693 5478 /***************** Bit definition for USB_ADDR0_TX register *****************/
hudakz 0:2cf53c219693 5479 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
hudakz 0:2cf53c219693 5480 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5481 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
hudakz 0:2cf53c219693 5482
hudakz 0:2cf53c219693 5483 /***************** Bit definition for USB_ADDR1_TX register *****************/
hudakz 0:2cf53c219693 5484 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
hudakz 0:2cf53c219693 5485 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5486 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
hudakz 0:2cf53c219693 5487
hudakz 0:2cf53c219693 5488 /***************** Bit definition for USB_ADDR2_TX register *****************/
hudakz 0:2cf53c219693 5489 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
hudakz 0:2cf53c219693 5490 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5491 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
hudakz 0:2cf53c219693 5492
hudakz 0:2cf53c219693 5493 /***************** Bit definition for USB_ADDR3_TX register *****************/
hudakz 0:2cf53c219693 5494 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
hudakz 0:2cf53c219693 5495 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5496 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
hudakz 0:2cf53c219693 5497
hudakz 0:2cf53c219693 5498 /***************** Bit definition for USB_ADDR4_TX register *****************/
hudakz 0:2cf53c219693 5499 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
hudakz 0:2cf53c219693 5500 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5501 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
hudakz 0:2cf53c219693 5502
hudakz 0:2cf53c219693 5503 /***************** Bit definition for USB_ADDR5_TX register *****************/
hudakz 0:2cf53c219693 5504 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
hudakz 0:2cf53c219693 5505 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5506 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
hudakz 0:2cf53c219693 5507
hudakz 0:2cf53c219693 5508 /***************** Bit definition for USB_ADDR6_TX register *****************/
hudakz 0:2cf53c219693 5509 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
hudakz 0:2cf53c219693 5510 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5511 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
hudakz 0:2cf53c219693 5512
hudakz 0:2cf53c219693 5513 /***************** Bit definition for USB_ADDR7_TX register *****************/
hudakz 0:2cf53c219693 5514 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
hudakz 0:2cf53c219693 5515 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5516 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
hudakz 0:2cf53c219693 5517
hudakz 0:2cf53c219693 5518 /*----------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 5519
hudakz 0:2cf53c219693 5520 /***************** Bit definition for USB_COUNT0_TX register ****************/
hudakz 0:2cf53c219693 5521 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
hudakz 0:2cf53c219693 5522 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5523 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
hudakz 0:2cf53c219693 5524
hudakz 0:2cf53c219693 5525 /***************** Bit definition for USB_COUNT1_TX register ****************/
hudakz 0:2cf53c219693 5526 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
hudakz 0:2cf53c219693 5527 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5528 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
hudakz 0:2cf53c219693 5529
hudakz 0:2cf53c219693 5530 /***************** Bit definition for USB_COUNT2_TX register ****************/
hudakz 0:2cf53c219693 5531 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
hudakz 0:2cf53c219693 5532 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5533 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
hudakz 0:2cf53c219693 5534
hudakz 0:2cf53c219693 5535 /***************** Bit definition for USB_COUNT3_TX register ****************/
hudakz 0:2cf53c219693 5536 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
hudakz 0:2cf53c219693 5537 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5538 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
hudakz 0:2cf53c219693 5539
hudakz 0:2cf53c219693 5540 /***************** Bit definition for USB_COUNT4_TX register ****************/
hudakz 0:2cf53c219693 5541 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
hudakz 0:2cf53c219693 5542 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5543 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
hudakz 0:2cf53c219693 5544
hudakz 0:2cf53c219693 5545 /***************** Bit definition for USB_COUNT5_TX register ****************/
hudakz 0:2cf53c219693 5546 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
hudakz 0:2cf53c219693 5547 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5548 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
hudakz 0:2cf53c219693 5549
hudakz 0:2cf53c219693 5550 /***************** Bit definition for USB_COUNT6_TX register ****************/
hudakz 0:2cf53c219693 5551 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
hudakz 0:2cf53c219693 5552 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5553 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
hudakz 0:2cf53c219693 5554
hudakz 0:2cf53c219693 5555 /***************** Bit definition for USB_COUNT7_TX register ****************/
hudakz 0:2cf53c219693 5556 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
hudakz 0:2cf53c219693 5557 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5558 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
hudakz 0:2cf53c219693 5559
hudakz 0:2cf53c219693 5560 /*----------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 5561
hudakz 0:2cf53c219693 5562 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
hudakz 0:2cf53c219693 5563 #define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
hudakz 0:2cf53c219693 5564
hudakz 0:2cf53c219693 5565 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
hudakz 0:2cf53c219693 5566 #define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
hudakz 0:2cf53c219693 5567
hudakz 0:2cf53c219693 5568 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
hudakz 0:2cf53c219693 5569 #define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
hudakz 0:2cf53c219693 5570
hudakz 0:2cf53c219693 5571 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
hudakz 0:2cf53c219693 5572 #define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
hudakz 0:2cf53c219693 5573
hudakz 0:2cf53c219693 5574 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
hudakz 0:2cf53c219693 5575 #define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
hudakz 0:2cf53c219693 5576
hudakz 0:2cf53c219693 5577 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
hudakz 0:2cf53c219693 5578 #define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
hudakz 0:2cf53c219693 5579
hudakz 0:2cf53c219693 5580 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
hudakz 0:2cf53c219693 5581 #define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
hudakz 0:2cf53c219693 5582
hudakz 0:2cf53c219693 5583 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
hudakz 0:2cf53c219693 5584 #define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
hudakz 0:2cf53c219693 5585
hudakz 0:2cf53c219693 5586 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
hudakz 0:2cf53c219693 5587 #define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
hudakz 0:2cf53c219693 5588
hudakz 0:2cf53c219693 5589 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
hudakz 0:2cf53c219693 5590 #define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
hudakz 0:2cf53c219693 5591
hudakz 0:2cf53c219693 5592 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
hudakz 0:2cf53c219693 5593 #define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
hudakz 0:2cf53c219693 5594
hudakz 0:2cf53c219693 5595 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
hudakz 0:2cf53c219693 5596 #define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
hudakz 0:2cf53c219693 5597
hudakz 0:2cf53c219693 5598 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
hudakz 0:2cf53c219693 5599 #define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
hudakz 0:2cf53c219693 5600
hudakz 0:2cf53c219693 5601 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
hudakz 0:2cf53c219693 5602 #define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
hudakz 0:2cf53c219693 5603
hudakz 0:2cf53c219693 5604 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
hudakz 0:2cf53c219693 5605 #define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
hudakz 0:2cf53c219693 5606
hudakz 0:2cf53c219693 5607 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
hudakz 0:2cf53c219693 5608 #define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
hudakz 0:2cf53c219693 5609
hudakz 0:2cf53c219693 5610 /*----------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 5611
hudakz 0:2cf53c219693 5612 /***************** Bit definition for USB_ADDR0_RX register *****************/
hudakz 0:2cf53c219693 5613 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
hudakz 0:2cf53c219693 5614 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5615 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
hudakz 0:2cf53c219693 5616
hudakz 0:2cf53c219693 5617 /***************** Bit definition for USB_ADDR1_RX register *****************/
hudakz 0:2cf53c219693 5618 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
hudakz 0:2cf53c219693 5619 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5620 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
hudakz 0:2cf53c219693 5621
hudakz 0:2cf53c219693 5622 /***************** Bit definition for USB_ADDR2_RX register *****************/
hudakz 0:2cf53c219693 5623 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
hudakz 0:2cf53c219693 5624 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5625 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
hudakz 0:2cf53c219693 5626
hudakz 0:2cf53c219693 5627 /***************** Bit definition for USB_ADDR3_RX register *****************/
hudakz 0:2cf53c219693 5628 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
hudakz 0:2cf53c219693 5629 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5630 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
hudakz 0:2cf53c219693 5631
hudakz 0:2cf53c219693 5632 /***************** Bit definition for USB_ADDR4_RX register *****************/
hudakz 0:2cf53c219693 5633 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
hudakz 0:2cf53c219693 5634 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5635 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
hudakz 0:2cf53c219693 5636
hudakz 0:2cf53c219693 5637 /***************** Bit definition for USB_ADDR5_RX register *****************/
hudakz 0:2cf53c219693 5638 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
hudakz 0:2cf53c219693 5639 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5640 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
hudakz 0:2cf53c219693 5641
hudakz 0:2cf53c219693 5642 /***************** Bit definition for USB_ADDR6_RX register *****************/
hudakz 0:2cf53c219693 5643 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
hudakz 0:2cf53c219693 5644 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5645 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
hudakz 0:2cf53c219693 5646
hudakz 0:2cf53c219693 5647 /***************** Bit definition for USB_ADDR7_RX register *****************/
hudakz 0:2cf53c219693 5648 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
hudakz 0:2cf53c219693 5649 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
hudakz 0:2cf53c219693 5650 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
hudakz 0:2cf53c219693 5651
hudakz 0:2cf53c219693 5652 /*----------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 5653
hudakz 0:2cf53c219693 5654 /***************** Bit definition for USB_COUNT0_RX register ****************/
hudakz 0:2cf53c219693 5655 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
hudakz 0:2cf53c219693 5656 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5657 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5658
hudakz 0:2cf53c219693 5659 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5660 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5661 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5662 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5663 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5664 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5665 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5666 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5667
hudakz 0:2cf53c219693 5668 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5669 #define USB_COUNT0_RX_BLSIZE_Msk (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5670 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5671
hudakz 0:2cf53c219693 5672 /***************** Bit definition for USB_COUNT1_RX register ****************/
hudakz 0:2cf53c219693 5673 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
hudakz 0:2cf53c219693 5674 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5675 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5676
hudakz 0:2cf53c219693 5677 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5678 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5679 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5680 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5681 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5682 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5683 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5684 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5685
hudakz 0:2cf53c219693 5686 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5687 #define USB_COUNT1_RX_BLSIZE_Msk (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5688 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5689
hudakz 0:2cf53c219693 5690 /***************** Bit definition for USB_COUNT2_RX register ****************/
hudakz 0:2cf53c219693 5691 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
hudakz 0:2cf53c219693 5692 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5693 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5694
hudakz 0:2cf53c219693 5695 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5696 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5697 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5698 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5699 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5700 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5701 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5702 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5703
hudakz 0:2cf53c219693 5704 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5705 #define USB_COUNT2_RX_BLSIZE_Msk (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5706 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5707
hudakz 0:2cf53c219693 5708 /***************** Bit definition for USB_COUNT3_RX register ****************/
hudakz 0:2cf53c219693 5709 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
hudakz 0:2cf53c219693 5710 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5711 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5712
hudakz 0:2cf53c219693 5713 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5714 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5715 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5716 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5717 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5718 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5719 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5720 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5721
hudakz 0:2cf53c219693 5722 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5723 #define USB_COUNT3_RX_BLSIZE_Msk (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5724 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5725
hudakz 0:2cf53c219693 5726 /***************** Bit definition for USB_COUNT4_RX register ****************/
hudakz 0:2cf53c219693 5727 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
hudakz 0:2cf53c219693 5728 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5729 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5730
hudakz 0:2cf53c219693 5731 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5732 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5733 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5734 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5735 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5736 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5737 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5738 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5739
hudakz 0:2cf53c219693 5740 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5741 #define USB_COUNT4_RX_BLSIZE_Msk (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5742 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5743
hudakz 0:2cf53c219693 5744 /***************** Bit definition for USB_COUNT5_RX register ****************/
hudakz 0:2cf53c219693 5745 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
hudakz 0:2cf53c219693 5746 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5747 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5748
hudakz 0:2cf53c219693 5749 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5750 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5751 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5752 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5753 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5754 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5755 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5756 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5757
hudakz 0:2cf53c219693 5758 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5759 #define USB_COUNT5_RX_BLSIZE_Msk (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5760 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5761
hudakz 0:2cf53c219693 5762 /***************** Bit definition for USB_COUNT6_RX register ****************/
hudakz 0:2cf53c219693 5763 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
hudakz 0:2cf53c219693 5764 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5765 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5766
hudakz 0:2cf53c219693 5767 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5768 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5769 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5770 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5771 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5772 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5773 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5774 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5775
hudakz 0:2cf53c219693 5776 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5777 #define USB_COUNT6_RX_BLSIZE_Msk (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5778 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5779
hudakz 0:2cf53c219693 5780 /***************** Bit definition for USB_COUNT7_RX register ****************/
hudakz 0:2cf53c219693 5781 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
hudakz 0:2cf53c219693 5782 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 5783 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
hudakz 0:2cf53c219693 5784
hudakz 0:2cf53c219693 5785 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
hudakz 0:2cf53c219693 5786 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
hudakz 0:2cf53c219693 5787 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
hudakz 0:2cf53c219693 5788 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 5789 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 5790 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 5791 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 5792 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 5793
hudakz 0:2cf53c219693 5794 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
hudakz 0:2cf53c219693 5795 #define USB_COUNT7_RX_BLSIZE_Msk (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 5796 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
hudakz 0:2cf53c219693 5797
hudakz 0:2cf53c219693 5798 /*----------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 5799
hudakz 0:2cf53c219693 5800 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
hudakz 0:2cf53c219693 5801 #define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5802
hudakz 0:2cf53c219693 5803 #define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5804 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5805 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5806 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5807 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5808 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5809
hudakz 0:2cf53c219693 5810 #define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5811
hudakz 0:2cf53c219693 5812 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
hudakz 0:2cf53c219693 5813 #define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5814
hudakz 0:2cf53c219693 5815 #define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5816 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5817 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5818 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5819 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5820 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5821
hudakz 0:2cf53c219693 5822 #define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5823
hudakz 0:2cf53c219693 5824 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
hudakz 0:2cf53c219693 5825 #define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5826
hudakz 0:2cf53c219693 5827 #define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5828 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5829 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5830 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5831 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5832 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5833
hudakz 0:2cf53c219693 5834 #define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5835
hudakz 0:2cf53c219693 5836 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
hudakz 0:2cf53c219693 5837 #define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5838
hudakz 0:2cf53c219693 5839 #define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5840 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
hudakz 0:2cf53c219693 5841 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5842 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5843 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5844 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5845
hudakz 0:2cf53c219693 5846 #define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5847
hudakz 0:2cf53c219693 5848 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
hudakz 0:2cf53c219693 5849 #define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5850
hudakz 0:2cf53c219693 5851 #define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5852 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5853 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5854 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5855 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5856 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5857
hudakz 0:2cf53c219693 5858 #define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5859
hudakz 0:2cf53c219693 5860 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
hudakz 0:2cf53c219693 5861 #define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5862
hudakz 0:2cf53c219693 5863 #define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5864 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
hudakz 0:2cf53c219693 5865 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5866 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5867 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5868 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5869
hudakz 0:2cf53c219693 5870 #define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5871
hudakz 0:2cf53c219693 5872 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
hudakz 0:2cf53c219693 5873 #define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5874
hudakz 0:2cf53c219693 5875 #define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5876 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5877 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5878 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5879 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5880 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5881
hudakz 0:2cf53c219693 5882 #define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5883
hudakz 0:2cf53c219693 5884 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
hudakz 0:2cf53c219693 5885 #define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5886
hudakz 0:2cf53c219693 5887 #define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5888 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
hudakz 0:2cf53c219693 5889 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5890 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5891 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5892 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5893
hudakz 0:2cf53c219693 5894 #define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5895
hudakz 0:2cf53c219693 5896 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
hudakz 0:2cf53c219693 5897 #define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5898
hudakz 0:2cf53c219693 5899 #define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5900 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5901 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5902 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5903 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5904 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5905
hudakz 0:2cf53c219693 5906 #define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5907
hudakz 0:2cf53c219693 5908 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
hudakz 0:2cf53c219693 5909 #define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5910
hudakz 0:2cf53c219693 5911 #define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5912 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
hudakz 0:2cf53c219693 5913 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5914 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5915 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5916 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5917
hudakz 0:2cf53c219693 5918 #define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5919
hudakz 0:2cf53c219693 5920 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
hudakz 0:2cf53c219693 5921 #define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5922
hudakz 0:2cf53c219693 5923 #define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5924 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5925 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5926 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5927 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5928 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5929
hudakz 0:2cf53c219693 5930 #define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5931
hudakz 0:2cf53c219693 5932 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
hudakz 0:2cf53c219693 5933 #define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5934
hudakz 0:2cf53c219693 5935 #define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5936 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
hudakz 0:2cf53c219693 5937 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5938 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5939 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5940 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5941
hudakz 0:2cf53c219693 5942 #define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5943
hudakz 0:2cf53c219693 5944 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
hudakz 0:2cf53c219693 5945 #define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5946
hudakz 0:2cf53c219693 5947 #define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5948 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5949 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5950 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5951 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5952 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5953
hudakz 0:2cf53c219693 5954 #define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5955
hudakz 0:2cf53c219693 5956 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
hudakz 0:2cf53c219693 5957 #define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5958
hudakz 0:2cf53c219693 5959 #define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5960 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
hudakz 0:2cf53c219693 5961 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5962 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5963 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5964 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5965
hudakz 0:2cf53c219693 5966 #define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5967
hudakz 0:2cf53c219693 5968 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
hudakz 0:2cf53c219693 5969 #define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
hudakz 0:2cf53c219693 5970
hudakz 0:2cf53c219693 5971 #define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
hudakz 0:2cf53c219693 5972 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
hudakz 0:2cf53c219693 5973 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
hudakz 0:2cf53c219693 5974 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5975 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5976 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5977
hudakz 0:2cf53c219693 5978 #define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
hudakz 0:2cf53c219693 5979
hudakz 0:2cf53c219693 5980 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
hudakz 0:2cf53c219693 5981 #define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
hudakz 0:2cf53c219693 5982
hudakz 0:2cf53c219693 5983 #define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
hudakz 0:2cf53c219693 5984 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
hudakz 0:2cf53c219693 5985 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
hudakz 0:2cf53c219693 5986 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
hudakz 0:2cf53c219693 5987 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
hudakz 0:2cf53c219693 5988 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
hudakz 0:2cf53c219693 5989
hudakz 0:2cf53c219693 5990 #define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
hudakz 0:2cf53c219693 5991
hudakz 0:2cf53c219693 5992 /******************************************************************************/
hudakz 0:2cf53c219693 5993 /* */
hudakz 0:2cf53c219693 5994 /* Controller Area Network */
hudakz 0:2cf53c219693 5995 /* */
hudakz 0:2cf53c219693 5996 /******************************************************************************/
hudakz 0:2cf53c219693 5997
hudakz 0:2cf53c219693 5998 /*!< CAN control and status registers */
hudakz 0:2cf53c219693 5999 /******************* Bit definition for CAN_MCR register ********************/
hudakz 0:2cf53c219693 6000 #define CAN_MCR_INRQ_Pos (0U)
hudakz 0:2cf53c219693 6001 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6002 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
hudakz 0:2cf53c219693 6003 #define CAN_MCR_SLEEP_Pos (1U)
hudakz 0:2cf53c219693 6004 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6005 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
hudakz 0:2cf53c219693 6006 #define CAN_MCR_TXFP_Pos (2U)
hudakz 0:2cf53c219693 6007 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6008 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
hudakz 0:2cf53c219693 6009 #define CAN_MCR_RFLM_Pos (3U)
hudakz 0:2cf53c219693 6010 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6011 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
hudakz 0:2cf53c219693 6012 #define CAN_MCR_NART_Pos (4U)
hudakz 0:2cf53c219693 6013 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6014 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
hudakz 0:2cf53c219693 6015 #define CAN_MCR_AWUM_Pos (5U)
hudakz 0:2cf53c219693 6016 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6017 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
hudakz 0:2cf53c219693 6018 #define CAN_MCR_ABOM_Pos (6U)
hudakz 0:2cf53c219693 6019 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6020 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
hudakz 0:2cf53c219693 6021 #define CAN_MCR_TTCM_Pos (7U)
hudakz 0:2cf53c219693 6022 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6023 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
hudakz 0:2cf53c219693 6024 #define CAN_MCR_RESET_Pos (15U)
hudakz 0:2cf53c219693 6025 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 6026 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
hudakz 0:2cf53c219693 6027 #define CAN_MCR_DBF_Pos (16U)
hudakz 0:2cf53c219693 6028 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 6029 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
hudakz 0:2cf53c219693 6030
hudakz 0:2cf53c219693 6031 /******************* Bit definition for CAN_MSR register ********************/
hudakz 0:2cf53c219693 6032 #define CAN_MSR_INAK_Pos (0U)
hudakz 0:2cf53c219693 6033 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6034 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
hudakz 0:2cf53c219693 6035 #define CAN_MSR_SLAK_Pos (1U)
hudakz 0:2cf53c219693 6036 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6037 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
hudakz 0:2cf53c219693 6038 #define CAN_MSR_ERRI_Pos (2U)
hudakz 0:2cf53c219693 6039 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6040 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
hudakz 0:2cf53c219693 6041 #define CAN_MSR_WKUI_Pos (3U)
hudakz 0:2cf53c219693 6042 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6043 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
hudakz 0:2cf53c219693 6044 #define CAN_MSR_SLAKI_Pos (4U)
hudakz 0:2cf53c219693 6045 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6046 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
hudakz 0:2cf53c219693 6047 #define CAN_MSR_TXM_Pos (8U)
hudakz 0:2cf53c219693 6048 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6049 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
hudakz 0:2cf53c219693 6050 #define CAN_MSR_RXM_Pos (9U)
hudakz 0:2cf53c219693 6051 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6052 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
hudakz 0:2cf53c219693 6053 #define CAN_MSR_SAMP_Pos (10U)
hudakz 0:2cf53c219693 6054 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6055 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
hudakz 0:2cf53c219693 6056 #define CAN_MSR_RX_Pos (11U)
hudakz 0:2cf53c219693 6057 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6058 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
hudakz 0:2cf53c219693 6059
hudakz 0:2cf53c219693 6060 /******************* Bit definition for CAN_TSR register ********************/
hudakz 0:2cf53c219693 6061 #define CAN_TSR_RQCP0_Pos (0U)
hudakz 0:2cf53c219693 6062 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6063 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
hudakz 0:2cf53c219693 6064 #define CAN_TSR_TXOK0_Pos (1U)
hudakz 0:2cf53c219693 6065 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6066 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
hudakz 0:2cf53c219693 6067 #define CAN_TSR_ALST0_Pos (2U)
hudakz 0:2cf53c219693 6068 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6069 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
hudakz 0:2cf53c219693 6070 #define CAN_TSR_TERR0_Pos (3U)
hudakz 0:2cf53c219693 6071 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6072 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
hudakz 0:2cf53c219693 6073 #define CAN_TSR_ABRQ0_Pos (7U)
hudakz 0:2cf53c219693 6074 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6075 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
hudakz 0:2cf53c219693 6076 #define CAN_TSR_RQCP1_Pos (8U)
hudakz 0:2cf53c219693 6077 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6078 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
hudakz 0:2cf53c219693 6079 #define CAN_TSR_TXOK1_Pos (9U)
hudakz 0:2cf53c219693 6080 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6081 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
hudakz 0:2cf53c219693 6082 #define CAN_TSR_ALST1_Pos (10U)
hudakz 0:2cf53c219693 6083 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6084 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
hudakz 0:2cf53c219693 6085 #define CAN_TSR_TERR1_Pos (11U)
hudakz 0:2cf53c219693 6086 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6087 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
hudakz 0:2cf53c219693 6088 #define CAN_TSR_ABRQ1_Pos (15U)
hudakz 0:2cf53c219693 6089 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 6090 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
hudakz 0:2cf53c219693 6091 #define CAN_TSR_RQCP2_Pos (16U)
hudakz 0:2cf53c219693 6092 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 6093 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
hudakz 0:2cf53c219693 6094 #define CAN_TSR_TXOK2_Pos (17U)
hudakz 0:2cf53c219693 6095 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 6096 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
hudakz 0:2cf53c219693 6097 #define CAN_TSR_ALST2_Pos (18U)
hudakz 0:2cf53c219693 6098 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 6099 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
hudakz 0:2cf53c219693 6100 #define CAN_TSR_TERR2_Pos (19U)
hudakz 0:2cf53c219693 6101 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 6102 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
hudakz 0:2cf53c219693 6103 #define CAN_TSR_ABRQ2_Pos (23U)
hudakz 0:2cf53c219693 6104 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 6105 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
hudakz 0:2cf53c219693 6106 #define CAN_TSR_CODE_Pos (24U)
hudakz 0:2cf53c219693 6107 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
hudakz 0:2cf53c219693 6108 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
hudakz 0:2cf53c219693 6109
hudakz 0:2cf53c219693 6110 #define CAN_TSR_TME_Pos (26U)
hudakz 0:2cf53c219693 6111 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
hudakz 0:2cf53c219693 6112 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
hudakz 0:2cf53c219693 6113 #define CAN_TSR_TME0_Pos (26U)
hudakz 0:2cf53c219693 6114 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 6115 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
hudakz 0:2cf53c219693 6116 #define CAN_TSR_TME1_Pos (27U)
hudakz 0:2cf53c219693 6117 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 6118 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
hudakz 0:2cf53c219693 6119 #define CAN_TSR_TME2_Pos (28U)
hudakz 0:2cf53c219693 6120 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 6121 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
hudakz 0:2cf53c219693 6122
hudakz 0:2cf53c219693 6123 #define CAN_TSR_LOW_Pos (29U)
hudakz 0:2cf53c219693 6124 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
hudakz 0:2cf53c219693 6125 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
hudakz 0:2cf53c219693 6126 #define CAN_TSR_LOW0_Pos (29U)
hudakz 0:2cf53c219693 6127 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 6128 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
hudakz 0:2cf53c219693 6129 #define CAN_TSR_LOW1_Pos (30U)
hudakz 0:2cf53c219693 6130 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 6131 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
hudakz 0:2cf53c219693 6132 #define CAN_TSR_LOW2_Pos (31U)
hudakz 0:2cf53c219693 6133 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 6134 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
hudakz 0:2cf53c219693 6135
hudakz 0:2cf53c219693 6136 /******************* Bit definition for CAN_RF0R register *******************/
hudakz 0:2cf53c219693 6137 #define CAN_RF0R_FMP0_Pos (0U)
hudakz 0:2cf53c219693 6138 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 6139 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
hudakz 0:2cf53c219693 6140 #define CAN_RF0R_FULL0_Pos (3U)
hudakz 0:2cf53c219693 6141 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6142 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
hudakz 0:2cf53c219693 6143 #define CAN_RF0R_FOVR0_Pos (4U)
hudakz 0:2cf53c219693 6144 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6145 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
hudakz 0:2cf53c219693 6146 #define CAN_RF0R_RFOM0_Pos (5U)
hudakz 0:2cf53c219693 6147 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6148 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
hudakz 0:2cf53c219693 6149
hudakz 0:2cf53c219693 6150 /******************* Bit definition for CAN_RF1R register *******************/
hudakz 0:2cf53c219693 6151 #define CAN_RF1R_FMP1_Pos (0U)
hudakz 0:2cf53c219693 6152 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
hudakz 0:2cf53c219693 6153 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
hudakz 0:2cf53c219693 6154 #define CAN_RF1R_FULL1_Pos (3U)
hudakz 0:2cf53c219693 6155 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6156 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
hudakz 0:2cf53c219693 6157 #define CAN_RF1R_FOVR1_Pos (4U)
hudakz 0:2cf53c219693 6158 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6159 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
hudakz 0:2cf53c219693 6160 #define CAN_RF1R_RFOM1_Pos (5U)
hudakz 0:2cf53c219693 6161 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6162 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
hudakz 0:2cf53c219693 6163
hudakz 0:2cf53c219693 6164 /******************** Bit definition for CAN_IER register *******************/
hudakz 0:2cf53c219693 6165 #define CAN_IER_TMEIE_Pos (0U)
hudakz 0:2cf53c219693 6166 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6167 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
hudakz 0:2cf53c219693 6168 #define CAN_IER_FMPIE0_Pos (1U)
hudakz 0:2cf53c219693 6169 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6170 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
hudakz 0:2cf53c219693 6171 #define CAN_IER_FFIE0_Pos (2U)
hudakz 0:2cf53c219693 6172 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6173 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
hudakz 0:2cf53c219693 6174 #define CAN_IER_FOVIE0_Pos (3U)
hudakz 0:2cf53c219693 6175 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6176 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
hudakz 0:2cf53c219693 6177 #define CAN_IER_FMPIE1_Pos (4U)
hudakz 0:2cf53c219693 6178 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6179 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
hudakz 0:2cf53c219693 6180 #define CAN_IER_FFIE1_Pos (5U)
hudakz 0:2cf53c219693 6181 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6182 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
hudakz 0:2cf53c219693 6183 #define CAN_IER_FOVIE1_Pos (6U)
hudakz 0:2cf53c219693 6184 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6185 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
hudakz 0:2cf53c219693 6186 #define CAN_IER_EWGIE_Pos (8U)
hudakz 0:2cf53c219693 6187 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6188 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
hudakz 0:2cf53c219693 6189 #define CAN_IER_EPVIE_Pos (9U)
hudakz 0:2cf53c219693 6190 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6191 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
hudakz 0:2cf53c219693 6192 #define CAN_IER_BOFIE_Pos (10U)
hudakz 0:2cf53c219693 6193 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6194 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
hudakz 0:2cf53c219693 6195 #define CAN_IER_LECIE_Pos (11U)
hudakz 0:2cf53c219693 6196 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6197 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
hudakz 0:2cf53c219693 6198 #define CAN_IER_ERRIE_Pos (15U)
hudakz 0:2cf53c219693 6199 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 6200 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
hudakz 0:2cf53c219693 6201 #define CAN_IER_WKUIE_Pos (16U)
hudakz 0:2cf53c219693 6202 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 6203 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
hudakz 0:2cf53c219693 6204 #define CAN_IER_SLKIE_Pos (17U)
hudakz 0:2cf53c219693 6205 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 6206 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
hudakz 0:2cf53c219693 6207
hudakz 0:2cf53c219693 6208 /******************** Bit definition for CAN_ESR register *******************/
hudakz 0:2cf53c219693 6209 #define CAN_ESR_EWGF_Pos (0U)
hudakz 0:2cf53c219693 6210 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6211 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
hudakz 0:2cf53c219693 6212 #define CAN_ESR_EPVF_Pos (1U)
hudakz 0:2cf53c219693 6213 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6214 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
hudakz 0:2cf53c219693 6215 #define CAN_ESR_BOFF_Pos (2U)
hudakz 0:2cf53c219693 6216 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6217 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
hudakz 0:2cf53c219693 6218
hudakz 0:2cf53c219693 6219 #define CAN_ESR_LEC_Pos (4U)
hudakz 0:2cf53c219693 6220 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
hudakz 0:2cf53c219693 6221 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
hudakz 0:2cf53c219693 6222 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6223 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6224 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6225
hudakz 0:2cf53c219693 6226 #define CAN_ESR_TEC_Pos (16U)
hudakz 0:2cf53c219693 6227 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6228 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
hudakz 0:2cf53c219693 6229 #define CAN_ESR_REC_Pos (24U)
hudakz 0:2cf53c219693 6230 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6231 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
hudakz 0:2cf53c219693 6232
hudakz 0:2cf53c219693 6233 /******************* Bit definition for CAN_BTR register ********************/
hudakz 0:2cf53c219693 6234 #define CAN_BTR_BRP_Pos (0U)
hudakz 0:2cf53c219693 6235 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
hudakz 0:2cf53c219693 6236 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
hudakz 0:2cf53c219693 6237 #define CAN_BTR_TS1_Pos (16U)
hudakz 0:2cf53c219693 6238 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
hudakz 0:2cf53c219693 6239 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
hudakz 0:2cf53c219693 6240 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 6241 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 6242 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 6243 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 6244 #define CAN_BTR_TS2_Pos (20U)
hudakz 0:2cf53c219693 6245 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
hudakz 0:2cf53c219693 6246 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
hudakz 0:2cf53c219693 6247 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 6248 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 6249 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 6250 #define CAN_BTR_SJW_Pos (24U)
hudakz 0:2cf53c219693 6251 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
hudakz 0:2cf53c219693 6252 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
hudakz 0:2cf53c219693 6253 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 6254 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 6255 #define CAN_BTR_LBKM_Pos (30U)
hudakz 0:2cf53c219693 6256 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 6257 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
hudakz 0:2cf53c219693 6258 #define CAN_BTR_SILM_Pos (31U)
hudakz 0:2cf53c219693 6259 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 6260 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
hudakz 0:2cf53c219693 6261
hudakz 0:2cf53c219693 6262 /*!< Mailbox registers */
hudakz 0:2cf53c219693 6263 /****************** Bit definition for CAN_TI0R register ********************/
hudakz 0:2cf53c219693 6264 #define CAN_TI0R_TXRQ_Pos (0U)
hudakz 0:2cf53c219693 6265 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6266 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
hudakz 0:2cf53c219693 6267 #define CAN_TI0R_RTR_Pos (1U)
hudakz 0:2cf53c219693 6268 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6269 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
hudakz 0:2cf53c219693 6270 #define CAN_TI0R_IDE_Pos (2U)
hudakz 0:2cf53c219693 6271 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6272 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
hudakz 0:2cf53c219693 6273 #define CAN_TI0R_EXID_Pos (3U)
hudakz 0:2cf53c219693 6274 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
hudakz 0:2cf53c219693 6275 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
hudakz 0:2cf53c219693 6276 #define CAN_TI0R_STID_Pos (21U)
hudakz 0:2cf53c219693 6277 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
hudakz 0:2cf53c219693 6278 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
hudakz 0:2cf53c219693 6279
hudakz 0:2cf53c219693 6280 /****************** Bit definition for CAN_TDT0R register *******************/
hudakz 0:2cf53c219693 6281 #define CAN_TDT0R_DLC_Pos (0U)
hudakz 0:2cf53c219693 6282 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 6283 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
hudakz 0:2cf53c219693 6284 #define CAN_TDT0R_TGT_Pos (8U)
hudakz 0:2cf53c219693 6285 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6286 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
hudakz 0:2cf53c219693 6287 #define CAN_TDT0R_TIME_Pos (16U)
hudakz 0:2cf53c219693 6288 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
hudakz 0:2cf53c219693 6289 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
hudakz 0:2cf53c219693 6290
hudakz 0:2cf53c219693 6291 /****************** Bit definition for CAN_TDL0R register *******************/
hudakz 0:2cf53c219693 6292 #define CAN_TDL0R_DATA0_Pos (0U)
hudakz 0:2cf53c219693 6293 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6294 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
hudakz 0:2cf53c219693 6295 #define CAN_TDL0R_DATA1_Pos (8U)
hudakz 0:2cf53c219693 6296 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6297 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
hudakz 0:2cf53c219693 6298 #define CAN_TDL0R_DATA2_Pos (16U)
hudakz 0:2cf53c219693 6299 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6300 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
hudakz 0:2cf53c219693 6301 #define CAN_TDL0R_DATA3_Pos (24U)
hudakz 0:2cf53c219693 6302 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6303 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
hudakz 0:2cf53c219693 6304
hudakz 0:2cf53c219693 6305 /****************** Bit definition for CAN_TDH0R register *******************/
hudakz 0:2cf53c219693 6306 #define CAN_TDH0R_DATA4_Pos (0U)
hudakz 0:2cf53c219693 6307 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6308 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
hudakz 0:2cf53c219693 6309 #define CAN_TDH0R_DATA5_Pos (8U)
hudakz 0:2cf53c219693 6310 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6311 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
hudakz 0:2cf53c219693 6312 #define CAN_TDH0R_DATA6_Pos (16U)
hudakz 0:2cf53c219693 6313 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6314 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
hudakz 0:2cf53c219693 6315 #define CAN_TDH0R_DATA7_Pos (24U)
hudakz 0:2cf53c219693 6316 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6317 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
hudakz 0:2cf53c219693 6318
hudakz 0:2cf53c219693 6319 /******************* Bit definition for CAN_TI1R register *******************/
hudakz 0:2cf53c219693 6320 #define CAN_TI1R_TXRQ_Pos (0U)
hudakz 0:2cf53c219693 6321 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6322 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
hudakz 0:2cf53c219693 6323 #define CAN_TI1R_RTR_Pos (1U)
hudakz 0:2cf53c219693 6324 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6325 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
hudakz 0:2cf53c219693 6326 #define CAN_TI1R_IDE_Pos (2U)
hudakz 0:2cf53c219693 6327 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6328 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
hudakz 0:2cf53c219693 6329 #define CAN_TI1R_EXID_Pos (3U)
hudakz 0:2cf53c219693 6330 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
hudakz 0:2cf53c219693 6331 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
hudakz 0:2cf53c219693 6332 #define CAN_TI1R_STID_Pos (21U)
hudakz 0:2cf53c219693 6333 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
hudakz 0:2cf53c219693 6334 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
hudakz 0:2cf53c219693 6335
hudakz 0:2cf53c219693 6336 /******************* Bit definition for CAN_TDT1R register ******************/
hudakz 0:2cf53c219693 6337 #define CAN_TDT1R_DLC_Pos (0U)
hudakz 0:2cf53c219693 6338 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 6339 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
hudakz 0:2cf53c219693 6340 #define CAN_TDT1R_TGT_Pos (8U)
hudakz 0:2cf53c219693 6341 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6342 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
hudakz 0:2cf53c219693 6343 #define CAN_TDT1R_TIME_Pos (16U)
hudakz 0:2cf53c219693 6344 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
hudakz 0:2cf53c219693 6345 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
hudakz 0:2cf53c219693 6346
hudakz 0:2cf53c219693 6347 /******************* Bit definition for CAN_TDL1R register ******************/
hudakz 0:2cf53c219693 6348 #define CAN_TDL1R_DATA0_Pos (0U)
hudakz 0:2cf53c219693 6349 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6350 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
hudakz 0:2cf53c219693 6351 #define CAN_TDL1R_DATA1_Pos (8U)
hudakz 0:2cf53c219693 6352 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6353 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
hudakz 0:2cf53c219693 6354 #define CAN_TDL1R_DATA2_Pos (16U)
hudakz 0:2cf53c219693 6355 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6356 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
hudakz 0:2cf53c219693 6357 #define CAN_TDL1R_DATA3_Pos (24U)
hudakz 0:2cf53c219693 6358 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6359 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
hudakz 0:2cf53c219693 6360
hudakz 0:2cf53c219693 6361 /******************* Bit definition for CAN_TDH1R register ******************/
hudakz 0:2cf53c219693 6362 #define CAN_TDH1R_DATA4_Pos (0U)
hudakz 0:2cf53c219693 6363 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6364 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
hudakz 0:2cf53c219693 6365 #define CAN_TDH1R_DATA5_Pos (8U)
hudakz 0:2cf53c219693 6366 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6367 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
hudakz 0:2cf53c219693 6368 #define CAN_TDH1R_DATA6_Pos (16U)
hudakz 0:2cf53c219693 6369 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6370 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
hudakz 0:2cf53c219693 6371 #define CAN_TDH1R_DATA7_Pos (24U)
hudakz 0:2cf53c219693 6372 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6373 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
hudakz 0:2cf53c219693 6374
hudakz 0:2cf53c219693 6375 /******************* Bit definition for CAN_TI2R register *******************/
hudakz 0:2cf53c219693 6376 #define CAN_TI2R_TXRQ_Pos (0U)
hudakz 0:2cf53c219693 6377 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6378 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
hudakz 0:2cf53c219693 6379 #define CAN_TI2R_RTR_Pos (1U)
hudakz 0:2cf53c219693 6380 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6381 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
hudakz 0:2cf53c219693 6382 #define CAN_TI2R_IDE_Pos (2U)
hudakz 0:2cf53c219693 6383 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6384 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
hudakz 0:2cf53c219693 6385 #define CAN_TI2R_EXID_Pos (3U)
hudakz 0:2cf53c219693 6386 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
hudakz 0:2cf53c219693 6387 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
hudakz 0:2cf53c219693 6388 #define CAN_TI2R_STID_Pos (21U)
hudakz 0:2cf53c219693 6389 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
hudakz 0:2cf53c219693 6390 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
hudakz 0:2cf53c219693 6391
hudakz 0:2cf53c219693 6392 /******************* Bit definition for CAN_TDT2R register ******************/
hudakz 0:2cf53c219693 6393 #define CAN_TDT2R_DLC_Pos (0U)
hudakz 0:2cf53c219693 6394 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 6395 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
hudakz 0:2cf53c219693 6396 #define CAN_TDT2R_TGT_Pos (8U)
hudakz 0:2cf53c219693 6397 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6398 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
hudakz 0:2cf53c219693 6399 #define CAN_TDT2R_TIME_Pos (16U)
hudakz 0:2cf53c219693 6400 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
hudakz 0:2cf53c219693 6401 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
hudakz 0:2cf53c219693 6402
hudakz 0:2cf53c219693 6403 /******************* Bit definition for CAN_TDL2R register ******************/
hudakz 0:2cf53c219693 6404 #define CAN_TDL2R_DATA0_Pos (0U)
hudakz 0:2cf53c219693 6405 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6406 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
hudakz 0:2cf53c219693 6407 #define CAN_TDL2R_DATA1_Pos (8U)
hudakz 0:2cf53c219693 6408 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6409 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
hudakz 0:2cf53c219693 6410 #define CAN_TDL2R_DATA2_Pos (16U)
hudakz 0:2cf53c219693 6411 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6412 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
hudakz 0:2cf53c219693 6413 #define CAN_TDL2R_DATA3_Pos (24U)
hudakz 0:2cf53c219693 6414 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6415 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
hudakz 0:2cf53c219693 6416
hudakz 0:2cf53c219693 6417 /******************* Bit definition for CAN_TDH2R register ******************/
hudakz 0:2cf53c219693 6418 #define CAN_TDH2R_DATA4_Pos (0U)
hudakz 0:2cf53c219693 6419 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6420 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
hudakz 0:2cf53c219693 6421 #define CAN_TDH2R_DATA5_Pos (8U)
hudakz 0:2cf53c219693 6422 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6423 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
hudakz 0:2cf53c219693 6424 #define CAN_TDH2R_DATA6_Pos (16U)
hudakz 0:2cf53c219693 6425 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6426 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
hudakz 0:2cf53c219693 6427 #define CAN_TDH2R_DATA7_Pos (24U)
hudakz 0:2cf53c219693 6428 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6429 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
hudakz 0:2cf53c219693 6430
hudakz 0:2cf53c219693 6431 /******************* Bit definition for CAN_RI0R register *******************/
hudakz 0:2cf53c219693 6432 #define CAN_RI0R_RTR_Pos (1U)
hudakz 0:2cf53c219693 6433 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6434 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
hudakz 0:2cf53c219693 6435 #define CAN_RI0R_IDE_Pos (2U)
hudakz 0:2cf53c219693 6436 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6437 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
hudakz 0:2cf53c219693 6438 #define CAN_RI0R_EXID_Pos (3U)
hudakz 0:2cf53c219693 6439 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
hudakz 0:2cf53c219693 6440 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
hudakz 0:2cf53c219693 6441 #define CAN_RI0R_STID_Pos (21U)
hudakz 0:2cf53c219693 6442 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
hudakz 0:2cf53c219693 6443 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
hudakz 0:2cf53c219693 6444
hudakz 0:2cf53c219693 6445 /******************* Bit definition for CAN_RDT0R register ******************/
hudakz 0:2cf53c219693 6446 #define CAN_RDT0R_DLC_Pos (0U)
hudakz 0:2cf53c219693 6447 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 6448 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
hudakz 0:2cf53c219693 6449 #define CAN_RDT0R_FMI_Pos (8U)
hudakz 0:2cf53c219693 6450 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6451 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
hudakz 0:2cf53c219693 6452 #define CAN_RDT0R_TIME_Pos (16U)
hudakz 0:2cf53c219693 6453 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
hudakz 0:2cf53c219693 6454 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
hudakz 0:2cf53c219693 6455
hudakz 0:2cf53c219693 6456 /******************* Bit definition for CAN_RDL0R register ******************/
hudakz 0:2cf53c219693 6457 #define CAN_RDL0R_DATA0_Pos (0U)
hudakz 0:2cf53c219693 6458 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6459 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
hudakz 0:2cf53c219693 6460 #define CAN_RDL0R_DATA1_Pos (8U)
hudakz 0:2cf53c219693 6461 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6462 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
hudakz 0:2cf53c219693 6463 #define CAN_RDL0R_DATA2_Pos (16U)
hudakz 0:2cf53c219693 6464 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6465 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
hudakz 0:2cf53c219693 6466 #define CAN_RDL0R_DATA3_Pos (24U)
hudakz 0:2cf53c219693 6467 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6468 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
hudakz 0:2cf53c219693 6469
hudakz 0:2cf53c219693 6470 /******************* Bit definition for CAN_RDH0R register ******************/
hudakz 0:2cf53c219693 6471 #define CAN_RDH0R_DATA4_Pos (0U)
hudakz 0:2cf53c219693 6472 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6473 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
hudakz 0:2cf53c219693 6474 #define CAN_RDH0R_DATA5_Pos (8U)
hudakz 0:2cf53c219693 6475 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6476 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
hudakz 0:2cf53c219693 6477 #define CAN_RDH0R_DATA6_Pos (16U)
hudakz 0:2cf53c219693 6478 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6479 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
hudakz 0:2cf53c219693 6480 #define CAN_RDH0R_DATA7_Pos (24U)
hudakz 0:2cf53c219693 6481 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6482 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
hudakz 0:2cf53c219693 6483
hudakz 0:2cf53c219693 6484 /******************* Bit definition for CAN_RI1R register *******************/
hudakz 0:2cf53c219693 6485 #define CAN_RI1R_RTR_Pos (1U)
hudakz 0:2cf53c219693 6486 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6487 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
hudakz 0:2cf53c219693 6488 #define CAN_RI1R_IDE_Pos (2U)
hudakz 0:2cf53c219693 6489 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6490 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
hudakz 0:2cf53c219693 6491 #define CAN_RI1R_EXID_Pos (3U)
hudakz 0:2cf53c219693 6492 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
hudakz 0:2cf53c219693 6493 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
hudakz 0:2cf53c219693 6494 #define CAN_RI1R_STID_Pos (21U)
hudakz 0:2cf53c219693 6495 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
hudakz 0:2cf53c219693 6496 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
hudakz 0:2cf53c219693 6497
hudakz 0:2cf53c219693 6498 /******************* Bit definition for CAN_RDT1R register ******************/
hudakz 0:2cf53c219693 6499 #define CAN_RDT1R_DLC_Pos (0U)
hudakz 0:2cf53c219693 6500 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 6501 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
hudakz 0:2cf53c219693 6502 #define CAN_RDT1R_FMI_Pos (8U)
hudakz 0:2cf53c219693 6503 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6504 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
hudakz 0:2cf53c219693 6505 #define CAN_RDT1R_TIME_Pos (16U)
hudakz 0:2cf53c219693 6506 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
hudakz 0:2cf53c219693 6507 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
hudakz 0:2cf53c219693 6508
hudakz 0:2cf53c219693 6509 /******************* Bit definition for CAN_RDL1R register ******************/
hudakz 0:2cf53c219693 6510 #define CAN_RDL1R_DATA0_Pos (0U)
hudakz 0:2cf53c219693 6511 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6512 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
hudakz 0:2cf53c219693 6513 #define CAN_RDL1R_DATA1_Pos (8U)
hudakz 0:2cf53c219693 6514 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6515 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
hudakz 0:2cf53c219693 6516 #define CAN_RDL1R_DATA2_Pos (16U)
hudakz 0:2cf53c219693 6517 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6518 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
hudakz 0:2cf53c219693 6519 #define CAN_RDL1R_DATA3_Pos (24U)
hudakz 0:2cf53c219693 6520 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6521 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
hudakz 0:2cf53c219693 6522
hudakz 0:2cf53c219693 6523 /******************* Bit definition for CAN_RDH1R register ******************/
hudakz 0:2cf53c219693 6524 #define CAN_RDH1R_DATA4_Pos (0U)
hudakz 0:2cf53c219693 6525 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 6526 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
hudakz 0:2cf53c219693 6527 #define CAN_RDH1R_DATA5_Pos (8U)
hudakz 0:2cf53c219693 6528 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 6529 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
hudakz 0:2cf53c219693 6530 #define CAN_RDH1R_DATA6_Pos (16U)
hudakz 0:2cf53c219693 6531 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 6532 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
hudakz 0:2cf53c219693 6533 #define CAN_RDH1R_DATA7_Pos (24U)
hudakz 0:2cf53c219693 6534 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 6535 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
hudakz 0:2cf53c219693 6536
hudakz 0:2cf53c219693 6537 /*!< CAN filter registers */
hudakz 0:2cf53c219693 6538 /******************* Bit definition for CAN_FMR register ********************/
hudakz 0:2cf53c219693 6539 #define CAN_FMR_FINIT_Pos (0U)
hudakz 0:2cf53c219693 6540 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6541 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
hudakz 0:2cf53c219693 6542 #define CAN_FMR_CAN2SB_Pos (8U)
hudakz 0:2cf53c219693 6543 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
hudakz 0:2cf53c219693 6544 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
hudakz 0:2cf53c219693 6545
hudakz 0:2cf53c219693 6546 /******************* Bit definition for CAN_FM1R register *******************/
hudakz 0:2cf53c219693 6547 #define CAN_FM1R_FBM_Pos (0U)
hudakz 0:2cf53c219693 6548 #define CAN_FM1R_FBM_Msk (0x3FFFU << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
hudakz 0:2cf53c219693 6549 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
hudakz 0:2cf53c219693 6550 #define CAN_FM1R_FBM0_Pos (0U)
hudakz 0:2cf53c219693 6551 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6552 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
hudakz 0:2cf53c219693 6553 #define CAN_FM1R_FBM1_Pos (1U)
hudakz 0:2cf53c219693 6554 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6555 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
hudakz 0:2cf53c219693 6556 #define CAN_FM1R_FBM2_Pos (2U)
hudakz 0:2cf53c219693 6557 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6558 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
hudakz 0:2cf53c219693 6559 #define CAN_FM1R_FBM3_Pos (3U)
hudakz 0:2cf53c219693 6560 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6561 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
hudakz 0:2cf53c219693 6562 #define CAN_FM1R_FBM4_Pos (4U)
hudakz 0:2cf53c219693 6563 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6564 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
hudakz 0:2cf53c219693 6565 #define CAN_FM1R_FBM5_Pos (5U)
hudakz 0:2cf53c219693 6566 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6567 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
hudakz 0:2cf53c219693 6568 #define CAN_FM1R_FBM6_Pos (6U)
hudakz 0:2cf53c219693 6569 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6570 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
hudakz 0:2cf53c219693 6571 #define CAN_FM1R_FBM7_Pos (7U)
hudakz 0:2cf53c219693 6572 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6573 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
hudakz 0:2cf53c219693 6574 #define CAN_FM1R_FBM8_Pos (8U)
hudakz 0:2cf53c219693 6575 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6576 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
hudakz 0:2cf53c219693 6577 #define CAN_FM1R_FBM9_Pos (9U)
hudakz 0:2cf53c219693 6578 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6579 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
hudakz 0:2cf53c219693 6580 #define CAN_FM1R_FBM10_Pos (10U)
hudakz 0:2cf53c219693 6581 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6582 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
hudakz 0:2cf53c219693 6583 #define CAN_FM1R_FBM11_Pos (11U)
hudakz 0:2cf53c219693 6584 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6585 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
hudakz 0:2cf53c219693 6586 #define CAN_FM1R_FBM12_Pos (12U)
hudakz 0:2cf53c219693 6587 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 6588 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
hudakz 0:2cf53c219693 6589 #define CAN_FM1R_FBM13_Pos (13U)
hudakz 0:2cf53c219693 6590 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 6591 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
hudakz 0:2cf53c219693 6592
hudakz 0:2cf53c219693 6593 /******************* Bit definition for CAN_FS1R register *******************/
hudakz 0:2cf53c219693 6594 #define CAN_FS1R_FSC_Pos (0U)
hudakz 0:2cf53c219693 6595 #define CAN_FS1R_FSC_Msk (0x3FFFU << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
hudakz 0:2cf53c219693 6596 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
hudakz 0:2cf53c219693 6597 #define CAN_FS1R_FSC0_Pos (0U)
hudakz 0:2cf53c219693 6598 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6599 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
hudakz 0:2cf53c219693 6600 #define CAN_FS1R_FSC1_Pos (1U)
hudakz 0:2cf53c219693 6601 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6602 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
hudakz 0:2cf53c219693 6603 #define CAN_FS1R_FSC2_Pos (2U)
hudakz 0:2cf53c219693 6604 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6605 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
hudakz 0:2cf53c219693 6606 #define CAN_FS1R_FSC3_Pos (3U)
hudakz 0:2cf53c219693 6607 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6608 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
hudakz 0:2cf53c219693 6609 #define CAN_FS1R_FSC4_Pos (4U)
hudakz 0:2cf53c219693 6610 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6611 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
hudakz 0:2cf53c219693 6612 #define CAN_FS1R_FSC5_Pos (5U)
hudakz 0:2cf53c219693 6613 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6614 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
hudakz 0:2cf53c219693 6615 #define CAN_FS1R_FSC6_Pos (6U)
hudakz 0:2cf53c219693 6616 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6617 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
hudakz 0:2cf53c219693 6618 #define CAN_FS1R_FSC7_Pos (7U)
hudakz 0:2cf53c219693 6619 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6620 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
hudakz 0:2cf53c219693 6621 #define CAN_FS1R_FSC8_Pos (8U)
hudakz 0:2cf53c219693 6622 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6623 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
hudakz 0:2cf53c219693 6624 #define CAN_FS1R_FSC9_Pos (9U)
hudakz 0:2cf53c219693 6625 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6626 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
hudakz 0:2cf53c219693 6627 #define CAN_FS1R_FSC10_Pos (10U)
hudakz 0:2cf53c219693 6628 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6629 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
hudakz 0:2cf53c219693 6630 #define CAN_FS1R_FSC11_Pos (11U)
hudakz 0:2cf53c219693 6631 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6632 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
hudakz 0:2cf53c219693 6633 #define CAN_FS1R_FSC12_Pos (12U)
hudakz 0:2cf53c219693 6634 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 6635 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
hudakz 0:2cf53c219693 6636 #define CAN_FS1R_FSC13_Pos (13U)
hudakz 0:2cf53c219693 6637 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 6638 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
hudakz 0:2cf53c219693 6639
hudakz 0:2cf53c219693 6640 /****************** Bit definition for CAN_FFA1R register *******************/
hudakz 0:2cf53c219693 6641 #define CAN_FFA1R_FFA_Pos (0U)
hudakz 0:2cf53c219693 6642 #define CAN_FFA1R_FFA_Msk (0x3FFFU << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
hudakz 0:2cf53c219693 6643 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
hudakz 0:2cf53c219693 6644 #define CAN_FFA1R_FFA0_Pos (0U)
hudakz 0:2cf53c219693 6645 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6646 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
hudakz 0:2cf53c219693 6647 #define CAN_FFA1R_FFA1_Pos (1U)
hudakz 0:2cf53c219693 6648 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6649 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
hudakz 0:2cf53c219693 6650 #define CAN_FFA1R_FFA2_Pos (2U)
hudakz 0:2cf53c219693 6651 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6652 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
hudakz 0:2cf53c219693 6653 #define CAN_FFA1R_FFA3_Pos (3U)
hudakz 0:2cf53c219693 6654 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6655 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
hudakz 0:2cf53c219693 6656 #define CAN_FFA1R_FFA4_Pos (4U)
hudakz 0:2cf53c219693 6657 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6658 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
hudakz 0:2cf53c219693 6659 #define CAN_FFA1R_FFA5_Pos (5U)
hudakz 0:2cf53c219693 6660 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6661 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
hudakz 0:2cf53c219693 6662 #define CAN_FFA1R_FFA6_Pos (6U)
hudakz 0:2cf53c219693 6663 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6664 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
hudakz 0:2cf53c219693 6665 #define CAN_FFA1R_FFA7_Pos (7U)
hudakz 0:2cf53c219693 6666 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6667 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
hudakz 0:2cf53c219693 6668 #define CAN_FFA1R_FFA8_Pos (8U)
hudakz 0:2cf53c219693 6669 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6670 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
hudakz 0:2cf53c219693 6671 #define CAN_FFA1R_FFA9_Pos (9U)
hudakz 0:2cf53c219693 6672 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6673 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
hudakz 0:2cf53c219693 6674 #define CAN_FFA1R_FFA10_Pos (10U)
hudakz 0:2cf53c219693 6675 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6676 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
hudakz 0:2cf53c219693 6677 #define CAN_FFA1R_FFA11_Pos (11U)
hudakz 0:2cf53c219693 6678 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6679 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
hudakz 0:2cf53c219693 6680 #define CAN_FFA1R_FFA12_Pos (12U)
hudakz 0:2cf53c219693 6681 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 6682 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
hudakz 0:2cf53c219693 6683 #define CAN_FFA1R_FFA13_Pos (13U)
hudakz 0:2cf53c219693 6684 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 6685 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
hudakz 0:2cf53c219693 6686
hudakz 0:2cf53c219693 6687 /******************* Bit definition for CAN_FA1R register *******************/
hudakz 0:2cf53c219693 6688 #define CAN_FA1R_FACT_Pos (0U)
hudakz 0:2cf53c219693 6689 #define CAN_FA1R_FACT_Msk (0x3FFFU << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
hudakz 0:2cf53c219693 6690 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
hudakz 0:2cf53c219693 6691 #define CAN_FA1R_FACT0_Pos (0U)
hudakz 0:2cf53c219693 6692 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6693 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
hudakz 0:2cf53c219693 6694 #define CAN_FA1R_FACT1_Pos (1U)
hudakz 0:2cf53c219693 6695 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6696 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
hudakz 0:2cf53c219693 6697 #define CAN_FA1R_FACT2_Pos (2U)
hudakz 0:2cf53c219693 6698 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6699 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
hudakz 0:2cf53c219693 6700 #define CAN_FA1R_FACT3_Pos (3U)
hudakz 0:2cf53c219693 6701 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6702 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
hudakz 0:2cf53c219693 6703 #define CAN_FA1R_FACT4_Pos (4U)
hudakz 0:2cf53c219693 6704 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6705 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
hudakz 0:2cf53c219693 6706 #define CAN_FA1R_FACT5_Pos (5U)
hudakz 0:2cf53c219693 6707 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6708 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
hudakz 0:2cf53c219693 6709 #define CAN_FA1R_FACT6_Pos (6U)
hudakz 0:2cf53c219693 6710 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6711 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
hudakz 0:2cf53c219693 6712 #define CAN_FA1R_FACT7_Pos (7U)
hudakz 0:2cf53c219693 6713 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6714 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
hudakz 0:2cf53c219693 6715 #define CAN_FA1R_FACT8_Pos (8U)
hudakz 0:2cf53c219693 6716 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6717 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
hudakz 0:2cf53c219693 6718 #define CAN_FA1R_FACT9_Pos (9U)
hudakz 0:2cf53c219693 6719 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6720 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
hudakz 0:2cf53c219693 6721 #define CAN_FA1R_FACT10_Pos (10U)
hudakz 0:2cf53c219693 6722 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6723 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
hudakz 0:2cf53c219693 6724 #define CAN_FA1R_FACT11_Pos (11U)
hudakz 0:2cf53c219693 6725 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6726 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
hudakz 0:2cf53c219693 6727 #define CAN_FA1R_FACT12_Pos (12U)
hudakz 0:2cf53c219693 6728 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 6729 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
hudakz 0:2cf53c219693 6730 #define CAN_FA1R_FACT13_Pos (13U)
hudakz 0:2cf53c219693 6731 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 6732 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
hudakz 0:2cf53c219693 6733
hudakz 0:2cf53c219693 6734 /******************* Bit definition for CAN_F0R1 register *******************/
hudakz 0:2cf53c219693 6735 #define CAN_F0R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 6736 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6737 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 6738 #define CAN_F0R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 6739 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6740 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 6741 #define CAN_F0R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 6742 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6743 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 6744 #define CAN_F0R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 6745 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6746 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 6747 #define CAN_F0R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 6748 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6749 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 6750 #define CAN_F0R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 6751 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6752 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 6753 #define CAN_F0R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 6754 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6755 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 6756 #define CAN_F0R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 6757 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6758 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 6759 #define CAN_F0R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 6760 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6761 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 6762 #define CAN_F0R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 6763 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6764 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 6765 #define CAN_F0R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 6766 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6767 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 6768 #define CAN_F0R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 6769 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6770 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 6771 #define CAN_F0R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 6772 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 6773 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 6774 #define CAN_F0R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 6775 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 6776 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 6777 #define CAN_F0R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 6778 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 6779 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 6780 #define CAN_F0R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 6781 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 6782 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 6783 #define CAN_F0R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 6784 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 6785 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 6786 #define CAN_F0R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 6787 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 6788 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 6789 #define CAN_F0R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 6790 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 6791 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 6792 #define CAN_F0R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 6793 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 6794 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 6795 #define CAN_F0R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 6796 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 6797 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 6798 #define CAN_F0R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 6799 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 6800 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 6801 #define CAN_F0R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 6802 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 6803 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 6804 #define CAN_F0R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 6805 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 6806 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 6807 #define CAN_F0R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 6808 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 6809 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 6810 #define CAN_F0R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 6811 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 6812 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 6813 #define CAN_F0R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 6814 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 6815 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 6816 #define CAN_F0R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 6817 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 6818 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 6819 #define CAN_F0R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 6820 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 6821 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 6822 #define CAN_F0R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 6823 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 6824 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 6825 #define CAN_F0R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 6826 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 6827 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 6828 #define CAN_F0R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 6829 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 6830 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 6831
hudakz 0:2cf53c219693 6832 /******************* Bit definition for CAN_F1R1 register *******************/
hudakz 0:2cf53c219693 6833 #define CAN_F1R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 6834 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6835 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 6836 #define CAN_F1R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 6837 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6838 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 6839 #define CAN_F1R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 6840 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6841 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 6842 #define CAN_F1R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 6843 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6844 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 6845 #define CAN_F1R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 6846 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6847 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 6848 #define CAN_F1R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 6849 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6850 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 6851 #define CAN_F1R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 6852 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6853 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 6854 #define CAN_F1R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 6855 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6856 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 6857 #define CAN_F1R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 6858 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6859 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 6860 #define CAN_F1R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 6861 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6862 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 6863 #define CAN_F1R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 6864 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6865 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 6866 #define CAN_F1R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 6867 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6868 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 6869 #define CAN_F1R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 6870 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 6871 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 6872 #define CAN_F1R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 6873 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 6874 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 6875 #define CAN_F1R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 6876 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 6877 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 6878 #define CAN_F1R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 6879 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 6880 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 6881 #define CAN_F1R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 6882 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 6883 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 6884 #define CAN_F1R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 6885 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 6886 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 6887 #define CAN_F1R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 6888 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 6889 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 6890 #define CAN_F1R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 6891 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 6892 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 6893 #define CAN_F1R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 6894 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 6895 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 6896 #define CAN_F1R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 6897 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 6898 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 6899 #define CAN_F1R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 6900 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 6901 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 6902 #define CAN_F1R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 6903 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 6904 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 6905 #define CAN_F1R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 6906 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 6907 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 6908 #define CAN_F1R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 6909 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 6910 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 6911 #define CAN_F1R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 6912 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 6913 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 6914 #define CAN_F1R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 6915 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 6916 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 6917 #define CAN_F1R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 6918 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 6919 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 6920 #define CAN_F1R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 6921 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 6922 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 6923 #define CAN_F1R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 6924 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 6925 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 6926 #define CAN_F1R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 6927 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 6928 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 6929
hudakz 0:2cf53c219693 6930 /******************* Bit definition for CAN_F2R1 register *******************/
hudakz 0:2cf53c219693 6931 #define CAN_F2R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 6932 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 6933 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 6934 #define CAN_F2R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 6935 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 6936 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 6937 #define CAN_F2R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 6938 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 6939 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 6940 #define CAN_F2R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 6941 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 6942 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 6943 #define CAN_F2R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 6944 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 6945 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 6946 #define CAN_F2R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 6947 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 6948 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 6949 #define CAN_F2R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 6950 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 6951 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 6952 #define CAN_F2R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 6953 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 6954 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 6955 #define CAN_F2R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 6956 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 6957 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 6958 #define CAN_F2R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 6959 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 6960 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 6961 #define CAN_F2R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 6962 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 6963 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 6964 #define CAN_F2R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 6965 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 6966 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 6967 #define CAN_F2R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 6968 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 6969 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 6970 #define CAN_F2R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 6971 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 6972 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 6973 #define CAN_F2R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 6974 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 6975 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 6976 #define CAN_F2R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 6977 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 6978 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 6979 #define CAN_F2R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 6980 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 6981 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 6982 #define CAN_F2R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 6983 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 6984 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 6985 #define CAN_F2R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 6986 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 6987 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 6988 #define CAN_F2R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 6989 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 6990 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 6991 #define CAN_F2R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 6992 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 6993 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 6994 #define CAN_F2R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 6995 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 6996 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 6997 #define CAN_F2R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 6998 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 6999 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7000 #define CAN_F2R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7001 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7002 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7003 #define CAN_F2R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7004 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7005 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7006 #define CAN_F2R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7007 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7008 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7009 #define CAN_F2R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7010 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7011 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7012 #define CAN_F2R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7013 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7014 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7015 #define CAN_F2R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7016 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7017 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7018 #define CAN_F2R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7019 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7020 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7021 #define CAN_F2R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7022 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7023 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7024 #define CAN_F2R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7025 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7026 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7027
hudakz 0:2cf53c219693 7028 /******************* Bit definition for CAN_F3R1 register *******************/
hudakz 0:2cf53c219693 7029 #define CAN_F3R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7030 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7031 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7032 #define CAN_F3R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7033 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7034 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7035 #define CAN_F3R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7036 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7037 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7038 #define CAN_F3R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7039 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7040 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7041 #define CAN_F3R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7042 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7043 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7044 #define CAN_F3R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7045 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7046 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7047 #define CAN_F3R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7048 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7049 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7050 #define CAN_F3R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7051 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7052 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7053 #define CAN_F3R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7054 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7055 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7056 #define CAN_F3R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7057 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7058 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7059 #define CAN_F3R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7060 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7061 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7062 #define CAN_F3R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7063 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7064 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7065 #define CAN_F3R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7066 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7067 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7068 #define CAN_F3R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7069 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7070 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7071 #define CAN_F3R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7072 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7073 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7074 #define CAN_F3R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7075 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7076 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7077 #define CAN_F3R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7078 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7079 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7080 #define CAN_F3R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7081 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7082 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7083 #define CAN_F3R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7084 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7085 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7086 #define CAN_F3R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7087 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7088 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7089 #define CAN_F3R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7090 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7091 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7092 #define CAN_F3R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7093 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7094 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7095 #define CAN_F3R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7096 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7097 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7098 #define CAN_F3R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7099 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7100 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7101 #define CAN_F3R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7102 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7103 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7104 #define CAN_F3R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7105 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7106 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7107 #define CAN_F3R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7108 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7109 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7110 #define CAN_F3R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7111 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7112 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7113 #define CAN_F3R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7114 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7115 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7116 #define CAN_F3R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7117 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7118 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7119 #define CAN_F3R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7120 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7121 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7122 #define CAN_F3R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7123 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7124 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7125
hudakz 0:2cf53c219693 7126 /******************* Bit definition for CAN_F4R1 register *******************/
hudakz 0:2cf53c219693 7127 #define CAN_F4R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7128 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7129 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7130 #define CAN_F4R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7131 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7132 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7133 #define CAN_F4R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7134 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7135 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7136 #define CAN_F4R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7137 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7138 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7139 #define CAN_F4R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7140 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7141 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7142 #define CAN_F4R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7143 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7144 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7145 #define CAN_F4R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7146 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7147 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7148 #define CAN_F4R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7149 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7150 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7151 #define CAN_F4R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7152 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7153 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7154 #define CAN_F4R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7155 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7156 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7157 #define CAN_F4R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7158 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7159 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7160 #define CAN_F4R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7161 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7162 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7163 #define CAN_F4R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7164 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7165 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7166 #define CAN_F4R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7167 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7168 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7169 #define CAN_F4R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7170 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7171 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7172 #define CAN_F4R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7173 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7174 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7175 #define CAN_F4R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7176 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7177 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7178 #define CAN_F4R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7179 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7180 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7181 #define CAN_F4R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7182 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7183 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7184 #define CAN_F4R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7185 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7186 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7187 #define CAN_F4R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7188 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7189 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7190 #define CAN_F4R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7191 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7192 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7193 #define CAN_F4R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7194 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7195 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7196 #define CAN_F4R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7197 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7198 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7199 #define CAN_F4R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7200 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7201 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7202 #define CAN_F4R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7203 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7204 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7205 #define CAN_F4R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7206 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7207 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7208 #define CAN_F4R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7209 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7210 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7211 #define CAN_F4R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7212 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7213 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7214 #define CAN_F4R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7215 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7216 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7217 #define CAN_F4R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7218 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7219 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7220 #define CAN_F4R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7221 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7222 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7223
hudakz 0:2cf53c219693 7224 /******************* Bit definition for CAN_F5R1 register *******************/
hudakz 0:2cf53c219693 7225 #define CAN_F5R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7226 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7227 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7228 #define CAN_F5R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7229 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7230 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7231 #define CAN_F5R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7232 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7233 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7234 #define CAN_F5R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7235 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7236 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7237 #define CAN_F5R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7238 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7239 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7240 #define CAN_F5R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7241 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7242 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7243 #define CAN_F5R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7244 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7245 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7246 #define CAN_F5R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7247 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7248 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7249 #define CAN_F5R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7250 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7251 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7252 #define CAN_F5R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7253 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7254 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7255 #define CAN_F5R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7256 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7257 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7258 #define CAN_F5R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7259 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7260 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7261 #define CAN_F5R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7262 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7263 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7264 #define CAN_F5R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7265 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7266 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7267 #define CAN_F5R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7268 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7269 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7270 #define CAN_F5R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7271 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7272 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7273 #define CAN_F5R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7274 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7275 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7276 #define CAN_F5R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7277 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7278 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7279 #define CAN_F5R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7280 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7281 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7282 #define CAN_F5R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7283 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7284 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7285 #define CAN_F5R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7286 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7287 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7288 #define CAN_F5R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7289 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7290 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7291 #define CAN_F5R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7292 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7293 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7294 #define CAN_F5R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7295 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7296 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7297 #define CAN_F5R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7298 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7299 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7300 #define CAN_F5R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7301 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7302 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7303 #define CAN_F5R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7304 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7305 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7306 #define CAN_F5R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7307 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7308 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7309 #define CAN_F5R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7310 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7311 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7312 #define CAN_F5R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7313 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7314 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7315 #define CAN_F5R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7316 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7317 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7318 #define CAN_F5R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7319 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7320 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7321
hudakz 0:2cf53c219693 7322 /******************* Bit definition for CAN_F6R1 register *******************/
hudakz 0:2cf53c219693 7323 #define CAN_F6R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7324 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7325 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7326 #define CAN_F6R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7327 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7328 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7329 #define CAN_F6R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7330 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7331 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7332 #define CAN_F6R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7333 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7334 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7335 #define CAN_F6R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7336 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7337 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7338 #define CAN_F6R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7339 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7340 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7341 #define CAN_F6R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7342 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7343 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7344 #define CAN_F6R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7345 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7346 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7347 #define CAN_F6R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7348 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7349 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7350 #define CAN_F6R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7351 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7352 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7353 #define CAN_F6R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7354 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7355 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7356 #define CAN_F6R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7357 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7358 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7359 #define CAN_F6R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7360 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7361 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7362 #define CAN_F6R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7363 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7364 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7365 #define CAN_F6R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7366 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7367 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7368 #define CAN_F6R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7369 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7370 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7371 #define CAN_F6R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7372 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7373 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7374 #define CAN_F6R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7375 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7376 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7377 #define CAN_F6R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7378 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7379 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7380 #define CAN_F6R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7381 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7382 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7383 #define CAN_F6R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7384 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7385 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7386 #define CAN_F6R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7387 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7388 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7389 #define CAN_F6R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7390 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7391 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7392 #define CAN_F6R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7393 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7394 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7395 #define CAN_F6R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7396 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7397 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7398 #define CAN_F6R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7399 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7400 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7401 #define CAN_F6R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7402 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7403 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7404 #define CAN_F6R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7405 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7406 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7407 #define CAN_F6R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7408 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7409 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7410 #define CAN_F6R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7411 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7412 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7413 #define CAN_F6R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7414 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7415 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7416 #define CAN_F6R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7417 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7418 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7419
hudakz 0:2cf53c219693 7420 /******************* Bit definition for CAN_F7R1 register *******************/
hudakz 0:2cf53c219693 7421 #define CAN_F7R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7422 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7423 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7424 #define CAN_F7R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7425 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7426 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7427 #define CAN_F7R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7428 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7429 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7430 #define CAN_F7R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7431 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7432 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7433 #define CAN_F7R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7434 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7435 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7436 #define CAN_F7R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7437 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7438 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7439 #define CAN_F7R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7440 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7441 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7442 #define CAN_F7R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7443 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7444 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7445 #define CAN_F7R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7446 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7447 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7448 #define CAN_F7R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7449 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7450 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7451 #define CAN_F7R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7452 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7453 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7454 #define CAN_F7R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7455 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7456 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7457 #define CAN_F7R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7458 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7459 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7460 #define CAN_F7R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7461 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7462 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7463 #define CAN_F7R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7464 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7465 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7466 #define CAN_F7R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7467 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7468 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7469 #define CAN_F7R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7470 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7471 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7472 #define CAN_F7R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7473 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7474 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7475 #define CAN_F7R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7476 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7477 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7478 #define CAN_F7R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7479 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7480 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7481 #define CAN_F7R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7482 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7483 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7484 #define CAN_F7R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7485 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7486 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7487 #define CAN_F7R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7488 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7489 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7490 #define CAN_F7R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7491 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7492 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7493 #define CAN_F7R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7494 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7495 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7496 #define CAN_F7R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7497 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7498 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7499 #define CAN_F7R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7500 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7501 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7502 #define CAN_F7R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7503 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7504 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7505 #define CAN_F7R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7506 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7507 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7508 #define CAN_F7R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7509 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7510 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7511 #define CAN_F7R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7512 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7513 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7514 #define CAN_F7R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7515 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7516 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7517
hudakz 0:2cf53c219693 7518 /******************* Bit definition for CAN_F8R1 register *******************/
hudakz 0:2cf53c219693 7519 #define CAN_F8R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7520 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7521 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7522 #define CAN_F8R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7523 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7524 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7525 #define CAN_F8R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7526 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7527 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7528 #define CAN_F8R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7529 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7530 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7531 #define CAN_F8R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7532 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7533 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7534 #define CAN_F8R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7535 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7536 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7537 #define CAN_F8R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7538 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7539 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7540 #define CAN_F8R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7541 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7542 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7543 #define CAN_F8R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7544 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7545 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7546 #define CAN_F8R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7547 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7548 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7549 #define CAN_F8R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7550 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7551 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7552 #define CAN_F8R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7553 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7554 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7555 #define CAN_F8R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7556 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7557 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7558 #define CAN_F8R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7559 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7560 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7561 #define CAN_F8R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7562 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7563 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7564 #define CAN_F8R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7565 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7566 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7567 #define CAN_F8R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7568 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7569 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7570 #define CAN_F8R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7571 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7572 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7573 #define CAN_F8R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7574 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7575 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7576 #define CAN_F8R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7577 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7578 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7579 #define CAN_F8R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7580 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7581 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7582 #define CAN_F8R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7583 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7584 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7585 #define CAN_F8R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7586 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7587 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7588 #define CAN_F8R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7589 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7590 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7591 #define CAN_F8R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7592 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7593 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7594 #define CAN_F8R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7595 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7596 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7597 #define CAN_F8R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7598 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7599 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7600 #define CAN_F8R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7601 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7602 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7603 #define CAN_F8R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7604 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7605 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7606 #define CAN_F8R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7607 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7608 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7609 #define CAN_F8R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7610 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7611 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7612 #define CAN_F8R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7613 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7614 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7615
hudakz 0:2cf53c219693 7616 /******************* Bit definition for CAN_F9R1 register *******************/
hudakz 0:2cf53c219693 7617 #define CAN_F9R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7618 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7619 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7620 #define CAN_F9R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7621 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7622 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7623 #define CAN_F9R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7624 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7625 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7626 #define CAN_F9R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7627 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7628 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7629 #define CAN_F9R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7630 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7631 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7632 #define CAN_F9R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7633 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7634 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7635 #define CAN_F9R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7636 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7637 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7638 #define CAN_F9R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7639 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7640 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7641 #define CAN_F9R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7642 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7643 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7644 #define CAN_F9R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7645 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7646 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7647 #define CAN_F9R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7648 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7649 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7650 #define CAN_F9R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7651 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7652 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7653 #define CAN_F9R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7654 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7655 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7656 #define CAN_F9R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7657 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7658 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7659 #define CAN_F9R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7660 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7661 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7662 #define CAN_F9R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7663 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7664 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7665 #define CAN_F9R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7666 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7667 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7668 #define CAN_F9R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7669 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7670 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7671 #define CAN_F9R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7672 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7673 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7674 #define CAN_F9R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7675 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7676 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7677 #define CAN_F9R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7678 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7679 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7680 #define CAN_F9R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7681 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7682 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7683 #define CAN_F9R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7684 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7685 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7686 #define CAN_F9R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7687 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7688 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7689 #define CAN_F9R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7690 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7691 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7692 #define CAN_F9R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7693 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7694 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7695 #define CAN_F9R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7696 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7697 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7698 #define CAN_F9R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7699 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7700 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7701 #define CAN_F9R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7702 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7703 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7704 #define CAN_F9R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7705 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7706 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7707 #define CAN_F9R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7708 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7709 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7710 #define CAN_F9R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7711 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7712 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7713
hudakz 0:2cf53c219693 7714 /******************* Bit definition for CAN_F10R1 register ******************/
hudakz 0:2cf53c219693 7715 #define CAN_F10R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7716 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7717 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7718 #define CAN_F10R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7719 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7720 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7721 #define CAN_F10R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7722 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7723 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7724 #define CAN_F10R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7725 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7726 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7727 #define CAN_F10R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7728 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7729 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7730 #define CAN_F10R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7731 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7732 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7733 #define CAN_F10R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7734 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7735 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7736 #define CAN_F10R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7737 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7738 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7739 #define CAN_F10R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7740 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7741 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7742 #define CAN_F10R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7743 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7744 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7745 #define CAN_F10R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7746 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7747 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7748 #define CAN_F10R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7749 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7750 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7751 #define CAN_F10R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7752 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7753 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7754 #define CAN_F10R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7755 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7756 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7757 #define CAN_F10R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7758 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7759 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7760 #define CAN_F10R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7761 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7762 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7763 #define CAN_F10R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7764 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7765 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7766 #define CAN_F10R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7767 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7768 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7769 #define CAN_F10R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7770 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7771 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7772 #define CAN_F10R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7773 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7774 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7775 #define CAN_F10R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7776 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7777 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7778 #define CAN_F10R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7779 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7780 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7781 #define CAN_F10R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7782 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7783 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7784 #define CAN_F10R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7785 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7786 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7787 #define CAN_F10R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7788 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7789 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7790 #define CAN_F10R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7791 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7792 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7793 #define CAN_F10R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7794 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7795 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7796 #define CAN_F10R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7797 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7798 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7799 #define CAN_F10R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7800 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7801 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7802 #define CAN_F10R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7803 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7804 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7805 #define CAN_F10R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7806 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7807 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7808 #define CAN_F10R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7809 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7810 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7811
hudakz 0:2cf53c219693 7812 /******************* Bit definition for CAN_F11R1 register ******************/
hudakz 0:2cf53c219693 7813 #define CAN_F11R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7814 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7815 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7816 #define CAN_F11R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7817 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7818 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7819 #define CAN_F11R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7820 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7821 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7822 #define CAN_F11R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7823 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7824 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7825 #define CAN_F11R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7826 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7827 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7828 #define CAN_F11R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7829 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7830 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7831 #define CAN_F11R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7832 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7833 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7834 #define CAN_F11R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7835 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7836 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7837 #define CAN_F11R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7838 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7839 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7840 #define CAN_F11R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7841 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7842 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7843 #define CAN_F11R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7844 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7845 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7846 #define CAN_F11R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7847 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7848 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7849 #define CAN_F11R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7850 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7851 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7852 #define CAN_F11R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7853 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7854 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7855 #define CAN_F11R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7856 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7857 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7858 #define CAN_F11R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7859 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7860 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7861 #define CAN_F11R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7862 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7863 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7864 #define CAN_F11R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7865 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7866 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7867 #define CAN_F11R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7868 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7869 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7870 #define CAN_F11R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7871 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7872 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7873 #define CAN_F11R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7874 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7875 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7876 #define CAN_F11R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7877 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7878 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7879 #define CAN_F11R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7880 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7881 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7882 #define CAN_F11R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7883 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7884 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7885 #define CAN_F11R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7886 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7887 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7888 #define CAN_F11R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7889 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7890 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7891 #define CAN_F11R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7892 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7893 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7894 #define CAN_F11R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7895 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7896 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7897 #define CAN_F11R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7898 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7899 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7900 #define CAN_F11R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7901 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 7902 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 7903 #define CAN_F11R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 7904 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 7905 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 7906 #define CAN_F11R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 7907 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 7908 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 7909
hudakz 0:2cf53c219693 7910 /******************* Bit definition for CAN_F12R1 register ******************/
hudakz 0:2cf53c219693 7911 #define CAN_F12R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 7912 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 7913 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 7914 #define CAN_F12R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 7915 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 7916 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 7917 #define CAN_F12R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 7918 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 7919 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 7920 #define CAN_F12R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 7921 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 7922 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 7923 #define CAN_F12R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 7924 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 7925 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 7926 #define CAN_F12R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 7927 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 7928 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 7929 #define CAN_F12R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 7930 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 7931 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 7932 #define CAN_F12R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 7933 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 7934 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 7935 #define CAN_F12R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 7936 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 7937 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 7938 #define CAN_F12R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 7939 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 7940 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 7941 #define CAN_F12R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 7942 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 7943 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 7944 #define CAN_F12R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 7945 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 7946 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 7947 #define CAN_F12R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 7948 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 7949 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 7950 #define CAN_F12R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 7951 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 7952 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 7953 #define CAN_F12R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 7954 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 7955 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 7956 #define CAN_F12R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 7957 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 7958 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 7959 #define CAN_F12R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 7960 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 7961 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 7962 #define CAN_F12R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 7963 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 7964 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 7965 #define CAN_F12R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 7966 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 7967 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 7968 #define CAN_F12R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 7969 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 7970 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 7971 #define CAN_F12R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 7972 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 7973 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 7974 #define CAN_F12R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 7975 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 7976 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 7977 #define CAN_F12R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 7978 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 7979 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 7980 #define CAN_F12R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 7981 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 7982 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 7983 #define CAN_F12R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 7984 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 7985 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 7986 #define CAN_F12R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 7987 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 7988 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 7989 #define CAN_F12R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 7990 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 7991 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 7992 #define CAN_F12R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 7993 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 7994 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 7995 #define CAN_F12R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 7996 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 7997 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 7998 #define CAN_F12R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 7999 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8000 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8001 #define CAN_F12R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 8002 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8003 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8004 #define CAN_F12R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 8005 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8006 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8007
hudakz 0:2cf53c219693 8008 /******************* Bit definition for CAN_F13R1 register ******************/
hudakz 0:2cf53c219693 8009 #define CAN_F13R1_FB0_Pos (0U)
hudakz 0:2cf53c219693 8010 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8011 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8012 #define CAN_F13R1_FB1_Pos (1U)
hudakz 0:2cf53c219693 8013 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8014 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8015 #define CAN_F13R1_FB2_Pos (2U)
hudakz 0:2cf53c219693 8016 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8017 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8018 #define CAN_F13R1_FB3_Pos (3U)
hudakz 0:2cf53c219693 8019 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8020 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8021 #define CAN_F13R1_FB4_Pos (4U)
hudakz 0:2cf53c219693 8022 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8023 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8024 #define CAN_F13R1_FB5_Pos (5U)
hudakz 0:2cf53c219693 8025 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8026 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8027 #define CAN_F13R1_FB6_Pos (6U)
hudakz 0:2cf53c219693 8028 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8029 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8030 #define CAN_F13R1_FB7_Pos (7U)
hudakz 0:2cf53c219693 8031 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8032 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8033 #define CAN_F13R1_FB8_Pos (8U)
hudakz 0:2cf53c219693 8034 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8035 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8036 #define CAN_F13R1_FB9_Pos (9U)
hudakz 0:2cf53c219693 8037 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8038 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8039 #define CAN_F13R1_FB10_Pos (10U)
hudakz 0:2cf53c219693 8040 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8041 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8042 #define CAN_F13R1_FB11_Pos (11U)
hudakz 0:2cf53c219693 8043 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8044 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8045 #define CAN_F13R1_FB12_Pos (12U)
hudakz 0:2cf53c219693 8046 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8047 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8048 #define CAN_F13R1_FB13_Pos (13U)
hudakz 0:2cf53c219693 8049 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8050 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8051 #define CAN_F13R1_FB14_Pos (14U)
hudakz 0:2cf53c219693 8052 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8053 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8054 #define CAN_F13R1_FB15_Pos (15U)
hudakz 0:2cf53c219693 8055 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8056 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8057 #define CAN_F13R1_FB16_Pos (16U)
hudakz 0:2cf53c219693 8058 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8059 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8060 #define CAN_F13R1_FB17_Pos (17U)
hudakz 0:2cf53c219693 8061 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8062 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8063 #define CAN_F13R1_FB18_Pos (18U)
hudakz 0:2cf53c219693 8064 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8065 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8066 #define CAN_F13R1_FB19_Pos (19U)
hudakz 0:2cf53c219693 8067 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8068 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8069 #define CAN_F13R1_FB20_Pos (20U)
hudakz 0:2cf53c219693 8070 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8071 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8072 #define CAN_F13R1_FB21_Pos (21U)
hudakz 0:2cf53c219693 8073 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8074 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8075 #define CAN_F13R1_FB22_Pos (22U)
hudakz 0:2cf53c219693 8076 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8077 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8078 #define CAN_F13R1_FB23_Pos (23U)
hudakz 0:2cf53c219693 8079 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8080 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8081 #define CAN_F13R1_FB24_Pos (24U)
hudakz 0:2cf53c219693 8082 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8083 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8084 #define CAN_F13R1_FB25_Pos (25U)
hudakz 0:2cf53c219693 8085 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8086 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8087 #define CAN_F13R1_FB26_Pos (26U)
hudakz 0:2cf53c219693 8088 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8089 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8090 #define CAN_F13R1_FB27_Pos (27U)
hudakz 0:2cf53c219693 8091 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8092 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8093 #define CAN_F13R1_FB28_Pos (28U)
hudakz 0:2cf53c219693 8094 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8095 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8096 #define CAN_F13R1_FB29_Pos (29U)
hudakz 0:2cf53c219693 8097 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8098 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8099 #define CAN_F13R1_FB30_Pos (30U)
hudakz 0:2cf53c219693 8100 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8101 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8102 #define CAN_F13R1_FB31_Pos (31U)
hudakz 0:2cf53c219693 8103 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8104 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8105
hudakz 0:2cf53c219693 8106 /******************* Bit definition for CAN_F0R2 register *******************/
hudakz 0:2cf53c219693 8107 #define CAN_F0R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8108 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8109 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8110 #define CAN_F0R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8111 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8112 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8113 #define CAN_F0R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8114 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8115 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8116 #define CAN_F0R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8117 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8118 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8119 #define CAN_F0R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8120 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8121 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8122 #define CAN_F0R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8123 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8124 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8125 #define CAN_F0R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8126 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8127 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8128 #define CAN_F0R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8129 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8130 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8131 #define CAN_F0R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8132 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8133 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8134 #define CAN_F0R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8135 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8136 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8137 #define CAN_F0R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8138 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8139 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8140 #define CAN_F0R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8141 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8142 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8143 #define CAN_F0R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8144 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8145 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8146 #define CAN_F0R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8147 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8148 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8149 #define CAN_F0R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8150 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8151 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8152 #define CAN_F0R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8153 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8154 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8155 #define CAN_F0R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8156 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8157 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8158 #define CAN_F0R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8159 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8160 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8161 #define CAN_F0R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8162 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8163 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8164 #define CAN_F0R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8165 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8166 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8167 #define CAN_F0R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8168 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8169 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8170 #define CAN_F0R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8171 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8172 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8173 #define CAN_F0R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8174 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8175 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8176 #define CAN_F0R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8177 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8178 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8179 #define CAN_F0R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8180 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8181 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8182 #define CAN_F0R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8183 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8184 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8185 #define CAN_F0R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8186 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8187 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8188 #define CAN_F0R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8189 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8190 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8191 #define CAN_F0R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8192 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8193 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8194 #define CAN_F0R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8195 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8196 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8197 #define CAN_F0R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8198 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8199 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8200 #define CAN_F0R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8201 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8202 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8203
hudakz 0:2cf53c219693 8204 /******************* Bit definition for CAN_F1R2 register *******************/
hudakz 0:2cf53c219693 8205 #define CAN_F1R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8206 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8207 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8208 #define CAN_F1R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8209 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8210 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8211 #define CAN_F1R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8212 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8213 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8214 #define CAN_F1R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8215 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8216 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8217 #define CAN_F1R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8218 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8219 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8220 #define CAN_F1R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8221 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8222 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8223 #define CAN_F1R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8224 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8225 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8226 #define CAN_F1R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8227 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8228 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8229 #define CAN_F1R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8230 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8231 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8232 #define CAN_F1R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8233 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8234 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8235 #define CAN_F1R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8236 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8237 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8238 #define CAN_F1R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8239 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8240 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8241 #define CAN_F1R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8242 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8243 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8244 #define CAN_F1R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8245 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8246 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8247 #define CAN_F1R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8248 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8249 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8250 #define CAN_F1R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8251 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8252 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8253 #define CAN_F1R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8254 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8255 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8256 #define CAN_F1R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8257 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8258 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8259 #define CAN_F1R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8260 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8261 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8262 #define CAN_F1R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8263 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8264 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8265 #define CAN_F1R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8266 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8267 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8268 #define CAN_F1R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8269 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8270 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8271 #define CAN_F1R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8272 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8273 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8274 #define CAN_F1R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8275 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8276 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8277 #define CAN_F1R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8278 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8279 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8280 #define CAN_F1R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8281 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8282 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8283 #define CAN_F1R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8284 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8285 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8286 #define CAN_F1R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8287 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8288 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8289 #define CAN_F1R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8290 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8291 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8292 #define CAN_F1R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8293 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8294 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8295 #define CAN_F1R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8296 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8297 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8298 #define CAN_F1R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8299 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8300 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8301
hudakz 0:2cf53c219693 8302 /******************* Bit definition for CAN_F2R2 register *******************/
hudakz 0:2cf53c219693 8303 #define CAN_F2R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8304 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8305 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8306 #define CAN_F2R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8307 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8308 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8309 #define CAN_F2R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8310 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8311 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8312 #define CAN_F2R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8313 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8314 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8315 #define CAN_F2R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8316 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8317 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8318 #define CAN_F2R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8319 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8320 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8321 #define CAN_F2R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8322 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8323 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8324 #define CAN_F2R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8325 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8326 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8327 #define CAN_F2R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8328 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8329 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8330 #define CAN_F2R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8331 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8332 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8333 #define CAN_F2R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8334 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8335 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8336 #define CAN_F2R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8337 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8338 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8339 #define CAN_F2R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8340 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8341 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8342 #define CAN_F2R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8343 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8344 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8345 #define CAN_F2R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8346 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8347 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8348 #define CAN_F2R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8349 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8350 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8351 #define CAN_F2R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8352 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8353 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8354 #define CAN_F2R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8355 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8356 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8357 #define CAN_F2R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8358 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8359 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8360 #define CAN_F2R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8361 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8362 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8363 #define CAN_F2R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8364 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8365 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8366 #define CAN_F2R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8367 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8368 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8369 #define CAN_F2R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8370 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8371 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8372 #define CAN_F2R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8373 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8374 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8375 #define CAN_F2R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8376 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8377 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8378 #define CAN_F2R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8379 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8380 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8381 #define CAN_F2R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8382 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8383 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8384 #define CAN_F2R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8385 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8386 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8387 #define CAN_F2R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8388 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8389 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8390 #define CAN_F2R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8391 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8392 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8393 #define CAN_F2R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8394 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8395 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8396 #define CAN_F2R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8397 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8398 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8399
hudakz 0:2cf53c219693 8400 /******************* Bit definition for CAN_F3R2 register *******************/
hudakz 0:2cf53c219693 8401 #define CAN_F3R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8402 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8403 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8404 #define CAN_F3R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8405 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8406 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8407 #define CAN_F3R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8408 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8409 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8410 #define CAN_F3R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8411 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8412 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8413 #define CAN_F3R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8414 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8415 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8416 #define CAN_F3R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8417 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8418 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8419 #define CAN_F3R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8420 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8421 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8422 #define CAN_F3R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8423 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8424 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8425 #define CAN_F3R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8426 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8427 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8428 #define CAN_F3R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8429 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8430 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8431 #define CAN_F3R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8432 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8433 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8434 #define CAN_F3R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8435 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8436 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8437 #define CAN_F3R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8438 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8439 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8440 #define CAN_F3R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8441 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8442 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8443 #define CAN_F3R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8444 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8445 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8446 #define CAN_F3R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8447 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8448 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8449 #define CAN_F3R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8450 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8451 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8452 #define CAN_F3R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8453 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8454 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8455 #define CAN_F3R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8456 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8457 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8458 #define CAN_F3R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8459 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8460 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8461 #define CAN_F3R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8462 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8463 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8464 #define CAN_F3R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8465 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8466 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8467 #define CAN_F3R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8468 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8469 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8470 #define CAN_F3R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8471 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8472 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8473 #define CAN_F3R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8474 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8475 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8476 #define CAN_F3R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8477 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8478 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8479 #define CAN_F3R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8480 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8481 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8482 #define CAN_F3R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8483 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8484 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8485 #define CAN_F3R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8486 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8487 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8488 #define CAN_F3R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8489 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8490 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8491 #define CAN_F3R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8492 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8493 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8494 #define CAN_F3R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8495 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8496 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8497
hudakz 0:2cf53c219693 8498 /******************* Bit definition for CAN_F4R2 register *******************/
hudakz 0:2cf53c219693 8499 #define CAN_F4R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8500 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8501 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8502 #define CAN_F4R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8503 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8504 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8505 #define CAN_F4R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8506 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8507 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8508 #define CAN_F4R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8509 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8510 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8511 #define CAN_F4R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8512 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8513 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8514 #define CAN_F4R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8515 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8516 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8517 #define CAN_F4R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8518 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8519 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8520 #define CAN_F4R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8521 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8522 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8523 #define CAN_F4R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8524 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8525 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8526 #define CAN_F4R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8527 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8528 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8529 #define CAN_F4R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8530 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8531 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8532 #define CAN_F4R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8533 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8534 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8535 #define CAN_F4R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8536 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8537 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8538 #define CAN_F4R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8539 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8540 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8541 #define CAN_F4R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8542 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8543 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8544 #define CAN_F4R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8545 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8546 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8547 #define CAN_F4R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8548 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8549 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8550 #define CAN_F4R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8551 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8552 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8553 #define CAN_F4R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8554 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8555 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8556 #define CAN_F4R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8557 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8558 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8559 #define CAN_F4R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8560 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8561 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8562 #define CAN_F4R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8563 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8564 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8565 #define CAN_F4R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8566 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8567 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8568 #define CAN_F4R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8569 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8570 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8571 #define CAN_F4R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8572 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8573 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8574 #define CAN_F4R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8575 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8576 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8577 #define CAN_F4R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8578 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8579 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8580 #define CAN_F4R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8581 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8582 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8583 #define CAN_F4R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8584 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8585 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8586 #define CAN_F4R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8587 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8588 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8589 #define CAN_F4R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8590 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8591 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8592 #define CAN_F4R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8593 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8594 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8595
hudakz 0:2cf53c219693 8596 /******************* Bit definition for CAN_F5R2 register *******************/
hudakz 0:2cf53c219693 8597 #define CAN_F5R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8598 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8599 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8600 #define CAN_F5R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8601 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8602 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8603 #define CAN_F5R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8604 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8605 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8606 #define CAN_F5R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8607 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8608 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8609 #define CAN_F5R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8610 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8611 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8612 #define CAN_F5R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8613 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8614 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8615 #define CAN_F5R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8616 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8617 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8618 #define CAN_F5R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8619 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8620 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8621 #define CAN_F5R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8622 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8623 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8624 #define CAN_F5R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8625 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8626 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8627 #define CAN_F5R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8628 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8629 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8630 #define CAN_F5R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8631 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8632 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8633 #define CAN_F5R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8634 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8635 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8636 #define CAN_F5R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8637 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8638 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8639 #define CAN_F5R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8640 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8641 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8642 #define CAN_F5R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8643 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8644 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8645 #define CAN_F5R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8646 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8647 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8648 #define CAN_F5R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8649 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8650 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8651 #define CAN_F5R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8652 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8653 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8654 #define CAN_F5R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8655 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8656 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8657 #define CAN_F5R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8658 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8659 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8660 #define CAN_F5R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8661 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8662 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8663 #define CAN_F5R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8664 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8665 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8666 #define CAN_F5R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8667 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8668 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8669 #define CAN_F5R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8670 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8671 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8672 #define CAN_F5R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8673 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8674 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8675 #define CAN_F5R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8676 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8677 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8678 #define CAN_F5R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8679 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8680 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8681 #define CAN_F5R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8682 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8683 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8684 #define CAN_F5R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8685 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8686 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8687 #define CAN_F5R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8688 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8689 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8690 #define CAN_F5R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8691 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8692 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8693
hudakz 0:2cf53c219693 8694 /******************* Bit definition for CAN_F6R2 register *******************/
hudakz 0:2cf53c219693 8695 #define CAN_F6R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8696 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8697 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8698 #define CAN_F6R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8699 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8700 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8701 #define CAN_F6R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8702 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8703 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8704 #define CAN_F6R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8705 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8706 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8707 #define CAN_F6R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8708 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8709 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8710 #define CAN_F6R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8711 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8712 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8713 #define CAN_F6R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8714 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8715 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8716 #define CAN_F6R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8717 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8718 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8719 #define CAN_F6R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8720 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8721 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8722 #define CAN_F6R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8723 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8724 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8725 #define CAN_F6R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8726 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8727 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8728 #define CAN_F6R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8729 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8730 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8731 #define CAN_F6R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8732 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8733 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8734 #define CAN_F6R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8735 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8736 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8737 #define CAN_F6R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8738 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8739 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8740 #define CAN_F6R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8741 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8742 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8743 #define CAN_F6R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8744 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8745 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8746 #define CAN_F6R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8747 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8748 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8749 #define CAN_F6R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8750 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8751 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8752 #define CAN_F6R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8753 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8754 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8755 #define CAN_F6R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8756 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8757 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8758 #define CAN_F6R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8759 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8760 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8761 #define CAN_F6R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8762 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8763 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8764 #define CAN_F6R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8765 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8766 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8767 #define CAN_F6R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8768 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8769 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8770 #define CAN_F6R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8771 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8772 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8773 #define CAN_F6R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8774 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8775 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8776 #define CAN_F6R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8777 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8778 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8779 #define CAN_F6R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8780 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8781 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8782 #define CAN_F6R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8783 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8784 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8785 #define CAN_F6R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8786 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8787 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8788 #define CAN_F6R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8789 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8790 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8791
hudakz 0:2cf53c219693 8792 /******************* Bit definition for CAN_F7R2 register *******************/
hudakz 0:2cf53c219693 8793 #define CAN_F7R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8794 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8795 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8796 #define CAN_F7R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8797 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8798 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8799 #define CAN_F7R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8800 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8801 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8802 #define CAN_F7R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8803 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8804 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8805 #define CAN_F7R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8806 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8807 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8808 #define CAN_F7R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8809 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8810 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8811 #define CAN_F7R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8812 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8813 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8814 #define CAN_F7R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8815 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8816 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8817 #define CAN_F7R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8818 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8819 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8820 #define CAN_F7R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8821 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8822 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8823 #define CAN_F7R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8824 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8825 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8826 #define CAN_F7R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8827 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8828 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8829 #define CAN_F7R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8830 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8831 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8832 #define CAN_F7R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8833 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8834 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8835 #define CAN_F7R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8836 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8837 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8838 #define CAN_F7R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8839 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8840 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8841 #define CAN_F7R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8842 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8843 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8844 #define CAN_F7R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8845 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8846 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8847 #define CAN_F7R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8848 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8849 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8850 #define CAN_F7R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8851 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8852 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8853 #define CAN_F7R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8854 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8855 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8856 #define CAN_F7R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8857 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8858 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8859 #define CAN_F7R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8860 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8861 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8862 #define CAN_F7R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8863 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8864 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8865 #define CAN_F7R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8866 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8867 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8868 #define CAN_F7R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8869 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8870 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8871 #define CAN_F7R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8872 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8873 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8874 #define CAN_F7R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8875 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8876 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8877 #define CAN_F7R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8878 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8879 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8880 #define CAN_F7R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8881 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8882 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8883 #define CAN_F7R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8884 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8885 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8886 #define CAN_F7R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8887 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8888 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8889
hudakz 0:2cf53c219693 8890 /******************* Bit definition for CAN_F8R2 register *******************/
hudakz 0:2cf53c219693 8891 #define CAN_F8R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8892 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8893 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8894 #define CAN_F8R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8895 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8896 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8897 #define CAN_F8R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8898 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8899 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8900 #define CAN_F8R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8901 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 8902 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 8903 #define CAN_F8R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 8904 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 8905 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 8906 #define CAN_F8R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 8907 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 8908 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 8909 #define CAN_F8R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 8910 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 8911 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 8912 #define CAN_F8R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 8913 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 8914 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 8915 #define CAN_F8R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 8916 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 8917 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 8918 #define CAN_F8R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 8919 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 8920 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 8921 #define CAN_F8R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 8922 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 8923 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 8924 #define CAN_F8R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 8925 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 8926 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 8927 #define CAN_F8R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 8928 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 8929 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 8930 #define CAN_F8R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 8931 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 8932 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 8933 #define CAN_F8R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 8934 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 8935 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 8936 #define CAN_F8R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 8937 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 8938 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 8939 #define CAN_F8R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 8940 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 8941 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 8942 #define CAN_F8R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 8943 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 8944 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 8945 #define CAN_F8R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 8946 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 8947 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 8948 #define CAN_F8R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 8949 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 8950 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 8951 #define CAN_F8R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 8952 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 8953 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 8954 #define CAN_F8R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 8955 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 8956 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 8957 #define CAN_F8R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 8958 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 8959 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 8960 #define CAN_F8R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 8961 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 8962 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 8963 #define CAN_F8R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 8964 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 8965 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 8966 #define CAN_F8R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 8967 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 8968 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 8969 #define CAN_F8R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 8970 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 8971 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 8972 #define CAN_F8R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 8973 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 8974 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 8975 #define CAN_F8R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 8976 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 8977 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 8978 #define CAN_F8R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 8979 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 8980 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 8981 #define CAN_F8R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 8982 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 8983 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 8984 #define CAN_F8R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 8985 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 8986 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 8987
hudakz 0:2cf53c219693 8988 /******************* Bit definition for CAN_F9R2 register *******************/
hudakz 0:2cf53c219693 8989 #define CAN_F9R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 8990 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 8991 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 8992 #define CAN_F9R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 8993 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 8994 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 8995 #define CAN_F9R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 8996 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 8997 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 8998 #define CAN_F9R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 8999 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9000 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 9001 #define CAN_F9R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 9002 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9003 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 9004 #define CAN_F9R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 9005 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9006 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 9007 #define CAN_F9R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 9008 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9009 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 9010 #define CAN_F9R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 9011 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9012 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 9013 #define CAN_F9R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 9014 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9015 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 9016 #define CAN_F9R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 9017 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9018 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 9019 #define CAN_F9R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 9020 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9021 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 9022 #define CAN_F9R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 9023 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9024 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 9025 #define CAN_F9R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 9026 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9027 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 9028 #define CAN_F9R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 9029 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9030 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 9031 #define CAN_F9R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 9032 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9033 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 9034 #define CAN_F9R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 9035 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9036 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 9037 #define CAN_F9R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 9038 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 9039 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 9040 #define CAN_F9R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 9041 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 9042 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 9043 #define CAN_F9R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 9044 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 9045 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 9046 #define CAN_F9R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 9047 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 9048 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 9049 #define CAN_F9R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 9050 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 9051 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 9052 #define CAN_F9R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 9053 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 9054 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 9055 #define CAN_F9R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 9056 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 9057 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 9058 #define CAN_F9R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 9059 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 9060 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 9061 #define CAN_F9R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 9062 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 9063 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 9064 #define CAN_F9R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 9065 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 9066 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 9067 #define CAN_F9R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 9068 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 9069 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 9070 #define CAN_F9R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 9071 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 9072 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 9073 #define CAN_F9R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 9074 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 9075 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 9076 #define CAN_F9R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 9077 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 9078 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 9079 #define CAN_F9R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 9080 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 9081 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 9082 #define CAN_F9R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 9083 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 9084 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 9085
hudakz 0:2cf53c219693 9086 /******************* Bit definition for CAN_F10R2 register ******************/
hudakz 0:2cf53c219693 9087 #define CAN_F10R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 9088 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9089 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 9090 #define CAN_F10R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 9091 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9092 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 9093 #define CAN_F10R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 9094 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9095 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 9096 #define CAN_F10R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 9097 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9098 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 9099 #define CAN_F10R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 9100 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9101 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 9102 #define CAN_F10R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 9103 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9104 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 9105 #define CAN_F10R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 9106 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9107 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 9108 #define CAN_F10R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 9109 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9110 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 9111 #define CAN_F10R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 9112 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9113 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 9114 #define CAN_F10R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 9115 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9116 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 9117 #define CAN_F10R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 9118 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9119 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 9120 #define CAN_F10R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 9121 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9122 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 9123 #define CAN_F10R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 9124 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9125 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 9126 #define CAN_F10R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 9127 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9128 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 9129 #define CAN_F10R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 9130 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9131 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 9132 #define CAN_F10R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 9133 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9134 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 9135 #define CAN_F10R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 9136 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 9137 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 9138 #define CAN_F10R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 9139 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 9140 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 9141 #define CAN_F10R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 9142 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 9143 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 9144 #define CAN_F10R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 9145 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 9146 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 9147 #define CAN_F10R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 9148 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 9149 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 9150 #define CAN_F10R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 9151 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 9152 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 9153 #define CAN_F10R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 9154 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 9155 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 9156 #define CAN_F10R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 9157 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 9158 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 9159 #define CAN_F10R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 9160 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 9161 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 9162 #define CAN_F10R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 9163 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 9164 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 9165 #define CAN_F10R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 9166 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 9167 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 9168 #define CAN_F10R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 9169 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 9170 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 9171 #define CAN_F10R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 9172 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 9173 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 9174 #define CAN_F10R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 9175 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 9176 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 9177 #define CAN_F10R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 9178 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 9179 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 9180 #define CAN_F10R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 9181 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 9182 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 9183
hudakz 0:2cf53c219693 9184 /******************* Bit definition for CAN_F11R2 register ******************/
hudakz 0:2cf53c219693 9185 #define CAN_F11R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 9186 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9187 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 9188 #define CAN_F11R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 9189 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9190 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 9191 #define CAN_F11R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 9192 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9193 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 9194 #define CAN_F11R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 9195 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9196 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 9197 #define CAN_F11R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 9198 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9199 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 9200 #define CAN_F11R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 9201 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9202 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 9203 #define CAN_F11R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 9204 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9205 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 9206 #define CAN_F11R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 9207 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9208 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 9209 #define CAN_F11R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 9210 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9211 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 9212 #define CAN_F11R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 9213 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9214 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 9215 #define CAN_F11R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 9216 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9217 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 9218 #define CAN_F11R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 9219 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9220 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 9221 #define CAN_F11R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 9222 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9223 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 9224 #define CAN_F11R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 9225 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9226 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 9227 #define CAN_F11R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 9228 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9229 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 9230 #define CAN_F11R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 9231 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9232 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 9233 #define CAN_F11R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 9234 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 9235 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 9236 #define CAN_F11R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 9237 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 9238 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 9239 #define CAN_F11R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 9240 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 9241 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 9242 #define CAN_F11R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 9243 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 9244 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 9245 #define CAN_F11R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 9246 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 9247 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 9248 #define CAN_F11R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 9249 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 9250 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 9251 #define CAN_F11R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 9252 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 9253 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 9254 #define CAN_F11R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 9255 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 9256 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 9257 #define CAN_F11R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 9258 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 9259 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 9260 #define CAN_F11R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 9261 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 9262 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 9263 #define CAN_F11R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 9264 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 9265 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 9266 #define CAN_F11R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 9267 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 9268 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 9269 #define CAN_F11R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 9270 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 9271 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 9272 #define CAN_F11R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 9273 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 9274 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 9275 #define CAN_F11R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 9276 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 9277 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 9278 #define CAN_F11R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 9279 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 9280 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 9281
hudakz 0:2cf53c219693 9282 /******************* Bit definition for CAN_F12R2 register ******************/
hudakz 0:2cf53c219693 9283 #define CAN_F12R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 9284 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9285 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 9286 #define CAN_F12R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 9287 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9288 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 9289 #define CAN_F12R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 9290 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9291 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 9292 #define CAN_F12R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 9293 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9294 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 9295 #define CAN_F12R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 9296 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9297 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 9298 #define CAN_F12R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 9299 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9300 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 9301 #define CAN_F12R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 9302 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9303 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 9304 #define CAN_F12R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 9305 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9306 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 9307 #define CAN_F12R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 9308 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9309 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 9310 #define CAN_F12R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 9311 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9312 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 9313 #define CAN_F12R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 9314 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9315 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 9316 #define CAN_F12R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 9317 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9318 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 9319 #define CAN_F12R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 9320 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9321 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 9322 #define CAN_F12R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 9323 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9324 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 9325 #define CAN_F12R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 9326 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9327 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 9328 #define CAN_F12R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 9329 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9330 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 9331 #define CAN_F12R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 9332 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 9333 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 9334 #define CAN_F12R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 9335 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 9336 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 9337 #define CAN_F12R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 9338 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 9339 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 9340 #define CAN_F12R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 9341 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 9342 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 9343 #define CAN_F12R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 9344 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 9345 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 9346 #define CAN_F12R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 9347 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 9348 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 9349 #define CAN_F12R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 9350 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 9351 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 9352 #define CAN_F12R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 9353 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 9354 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 9355 #define CAN_F12R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 9356 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 9357 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 9358 #define CAN_F12R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 9359 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 9360 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 9361 #define CAN_F12R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 9362 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 9363 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 9364 #define CAN_F12R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 9365 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 9366 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 9367 #define CAN_F12R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 9368 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 9369 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 9370 #define CAN_F12R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 9371 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 9372 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 9373 #define CAN_F12R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 9374 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 9375 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 9376 #define CAN_F12R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 9377 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 9378 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 9379
hudakz 0:2cf53c219693 9380 /******************* Bit definition for CAN_F13R2 register ******************/
hudakz 0:2cf53c219693 9381 #define CAN_F13R2_FB0_Pos (0U)
hudakz 0:2cf53c219693 9382 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9383 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
hudakz 0:2cf53c219693 9384 #define CAN_F13R2_FB1_Pos (1U)
hudakz 0:2cf53c219693 9385 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9386 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
hudakz 0:2cf53c219693 9387 #define CAN_F13R2_FB2_Pos (2U)
hudakz 0:2cf53c219693 9388 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9389 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
hudakz 0:2cf53c219693 9390 #define CAN_F13R2_FB3_Pos (3U)
hudakz 0:2cf53c219693 9391 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9392 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
hudakz 0:2cf53c219693 9393 #define CAN_F13R2_FB4_Pos (4U)
hudakz 0:2cf53c219693 9394 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9395 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
hudakz 0:2cf53c219693 9396 #define CAN_F13R2_FB5_Pos (5U)
hudakz 0:2cf53c219693 9397 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9398 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
hudakz 0:2cf53c219693 9399 #define CAN_F13R2_FB6_Pos (6U)
hudakz 0:2cf53c219693 9400 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9401 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
hudakz 0:2cf53c219693 9402 #define CAN_F13R2_FB7_Pos (7U)
hudakz 0:2cf53c219693 9403 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9404 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
hudakz 0:2cf53c219693 9405 #define CAN_F13R2_FB8_Pos (8U)
hudakz 0:2cf53c219693 9406 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9407 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
hudakz 0:2cf53c219693 9408 #define CAN_F13R2_FB9_Pos (9U)
hudakz 0:2cf53c219693 9409 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9410 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
hudakz 0:2cf53c219693 9411 #define CAN_F13R2_FB10_Pos (10U)
hudakz 0:2cf53c219693 9412 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9413 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
hudakz 0:2cf53c219693 9414 #define CAN_F13R2_FB11_Pos (11U)
hudakz 0:2cf53c219693 9415 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9416 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
hudakz 0:2cf53c219693 9417 #define CAN_F13R2_FB12_Pos (12U)
hudakz 0:2cf53c219693 9418 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9419 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
hudakz 0:2cf53c219693 9420 #define CAN_F13R2_FB13_Pos (13U)
hudakz 0:2cf53c219693 9421 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9422 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
hudakz 0:2cf53c219693 9423 #define CAN_F13R2_FB14_Pos (14U)
hudakz 0:2cf53c219693 9424 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9425 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
hudakz 0:2cf53c219693 9426 #define CAN_F13R2_FB15_Pos (15U)
hudakz 0:2cf53c219693 9427 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9428 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
hudakz 0:2cf53c219693 9429 #define CAN_F13R2_FB16_Pos (16U)
hudakz 0:2cf53c219693 9430 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 9431 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
hudakz 0:2cf53c219693 9432 #define CAN_F13R2_FB17_Pos (17U)
hudakz 0:2cf53c219693 9433 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 9434 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
hudakz 0:2cf53c219693 9435 #define CAN_F13R2_FB18_Pos (18U)
hudakz 0:2cf53c219693 9436 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 9437 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
hudakz 0:2cf53c219693 9438 #define CAN_F13R2_FB19_Pos (19U)
hudakz 0:2cf53c219693 9439 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 9440 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
hudakz 0:2cf53c219693 9441 #define CAN_F13R2_FB20_Pos (20U)
hudakz 0:2cf53c219693 9442 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 9443 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
hudakz 0:2cf53c219693 9444 #define CAN_F13R2_FB21_Pos (21U)
hudakz 0:2cf53c219693 9445 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 9446 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
hudakz 0:2cf53c219693 9447 #define CAN_F13R2_FB22_Pos (22U)
hudakz 0:2cf53c219693 9448 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 9449 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
hudakz 0:2cf53c219693 9450 #define CAN_F13R2_FB23_Pos (23U)
hudakz 0:2cf53c219693 9451 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 9452 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
hudakz 0:2cf53c219693 9453 #define CAN_F13R2_FB24_Pos (24U)
hudakz 0:2cf53c219693 9454 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 9455 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
hudakz 0:2cf53c219693 9456 #define CAN_F13R2_FB25_Pos (25U)
hudakz 0:2cf53c219693 9457 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 9458 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
hudakz 0:2cf53c219693 9459 #define CAN_F13R2_FB26_Pos (26U)
hudakz 0:2cf53c219693 9460 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 9461 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
hudakz 0:2cf53c219693 9462 #define CAN_F13R2_FB27_Pos (27U)
hudakz 0:2cf53c219693 9463 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 9464 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
hudakz 0:2cf53c219693 9465 #define CAN_F13R2_FB28_Pos (28U)
hudakz 0:2cf53c219693 9466 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 9467 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
hudakz 0:2cf53c219693 9468 #define CAN_F13R2_FB29_Pos (29U)
hudakz 0:2cf53c219693 9469 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 9470 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
hudakz 0:2cf53c219693 9471 #define CAN_F13R2_FB30_Pos (30U)
hudakz 0:2cf53c219693 9472 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 9473 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
hudakz 0:2cf53c219693 9474 #define CAN_F13R2_FB31_Pos (31U)
hudakz 0:2cf53c219693 9475 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 9476 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
hudakz 0:2cf53c219693 9477
hudakz 0:2cf53c219693 9478 /******************************************************************************/
hudakz 0:2cf53c219693 9479 /* */
hudakz 0:2cf53c219693 9480 /* Serial Peripheral Interface */
hudakz 0:2cf53c219693 9481 /* */
hudakz 0:2cf53c219693 9482 /******************************************************************************/
hudakz 0:2cf53c219693 9483
hudakz 0:2cf53c219693 9484 /******************* Bit definition for SPI_CR1 register ********************/
hudakz 0:2cf53c219693 9485 #define SPI_CR1_CPHA_Pos (0U)
hudakz 0:2cf53c219693 9486 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9487 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
hudakz 0:2cf53c219693 9488 #define SPI_CR1_CPOL_Pos (1U)
hudakz 0:2cf53c219693 9489 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9490 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
hudakz 0:2cf53c219693 9491 #define SPI_CR1_MSTR_Pos (2U)
hudakz 0:2cf53c219693 9492 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9493 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
hudakz 0:2cf53c219693 9494
hudakz 0:2cf53c219693 9495 #define SPI_CR1_BR_Pos (3U)
hudakz 0:2cf53c219693 9496 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
hudakz 0:2cf53c219693 9497 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
hudakz 0:2cf53c219693 9498 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9499 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9500 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9501
hudakz 0:2cf53c219693 9502 #define SPI_CR1_SPE_Pos (6U)
hudakz 0:2cf53c219693 9503 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9504 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
hudakz 0:2cf53c219693 9505 #define SPI_CR1_LSBFIRST_Pos (7U)
hudakz 0:2cf53c219693 9506 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9507 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
hudakz 0:2cf53c219693 9508 #define SPI_CR1_SSI_Pos (8U)
hudakz 0:2cf53c219693 9509 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9510 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
hudakz 0:2cf53c219693 9511 #define SPI_CR1_SSM_Pos (9U)
hudakz 0:2cf53c219693 9512 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9513 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
hudakz 0:2cf53c219693 9514 #define SPI_CR1_RXONLY_Pos (10U)
hudakz 0:2cf53c219693 9515 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9516 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
hudakz 0:2cf53c219693 9517 #define SPI_CR1_DFF_Pos (11U)
hudakz 0:2cf53c219693 9518 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9519 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
hudakz 0:2cf53c219693 9520 #define SPI_CR1_CRCNEXT_Pos (12U)
hudakz 0:2cf53c219693 9521 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9522 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
hudakz 0:2cf53c219693 9523 #define SPI_CR1_CRCEN_Pos (13U)
hudakz 0:2cf53c219693 9524 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9525 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
hudakz 0:2cf53c219693 9526 #define SPI_CR1_BIDIOE_Pos (14U)
hudakz 0:2cf53c219693 9527 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9528 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
hudakz 0:2cf53c219693 9529 #define SPI_CR1_BIDIMODE_Pos (15U)
hudakz 0:2cf53c219693 9530 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9531 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
hudakz 0:2cf53c219693 9532
hudakz 0:2cf53c219693 9533 /******************* Bit definition for SPI_CR2 register ********************/
hudakz 0:2cf53c219693 9534 #define SPI_CR2_RXDMAEN_Pos (0U)
hudakz 0:2cf53c219693 9535 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9536 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
hudakz 0:2cf53c219693 9537 #define SPI_CR2_TXDMAEN_Pos (1U)
hudakz 0:2cf53c219693 9538 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9539 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
hudakz 0:2cf53c219693 9540 #define SPI_CR2_SSOE_Pos (2U)
hudakz 0:2cf53c219693 9541 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9542 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
hudakz 0:2cf53c219693 9543 #define SPI_CR2_ERRIE_Pos (5U)
hudakz 0:2cf53c219693 9544 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9545 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
hudakz 0:2cf53c219693 9546 #define SPI_CR2_RXNEIE_Pos (6U)
hudakz 0:2cf53c219693 9547 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9548 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
hudakz 0:2cf53c219693 9549 #define SPI_CR2_TXEIE_Pos (7U)
hudakz 0:2cf53c219693 9550 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9551 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
hudakz 0:2cf53c219693 9552
hudakz 0:2cf53c219693 9553 /******************** Bit definition for SPI_SR register ********************/
hudakz 0:2cf53c219693 9554 #define SPI_SR_RXNE_Pos (0U)
hudakz 0:2cf53c219693 9555 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9556 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
hudakz 0:2cf53c219693 9557 #define SPI_SR_TXE_Pos (1U)
hudakz 0:2cf53c219693 9558 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9559 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
hudakz 0:2cf53c219693 9560 #define SPI_SR_CHSIDE_Pos (2U)
hudakz 0:2cf53c219693 9561 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9562 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
hudakz 0:2cf53c219693 9563 #define SPI_SR_UDR_Pos (3U)
hudakz 0:2cf53c219693 9564 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9565 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
hudakz 0:2cf53c219693 9566 #define SPI_SR_CRCERR_Pos (4U)
hudakz 0:2cf53c219693 9567 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9568 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
hudakz 0:2cf53c219693 9569 #define SPI_SR_MODF_Pos (5U)
hudakz 0:2cf53c219693 9570 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9571 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
hudakz 0:2cf53c219693 9572 #define SPI_SR_OVR_Pos (6U)
hudakz 0:2cf53c219693 9573 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9574 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
hudakz 0:2cf53c219693 9575 #define SPI_SR_BSY_Pos (7U)
hudakz 0:2cf53c219693 9576 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9577 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
hudakz 0:2cf53c219693 9578
hudakz 0:2cf53c219693 9579 /******************** Bit definition for SPI_DR register ********************/
hudakz 0:2cf53c219693 9580 #define SPI_DR_DR_Pos (0U)
hudakz 0:2cf53c219693 9581 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 9582 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
hudakz 0:2cf53c219693 9583
hudakz 0:2cf53c219693 9584 /******************* Bit definition for SPI_CRCPR register ******************/
hudakz 0:2cf53c219693 9585 #define SPI_CRCPR_CRCPOLY_Pos (0U)
hudakz 0:2cf53c219693 9586 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 9587 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
hudakz 0:2cf53c219693 9588
hudakz 0:2cf53c219693 9589 /****************** Bit definition for SPI_RXCRCR register ******************/
hudakz 0:2cf53c219693 9590 #define SPI_RXCRCR_RXCRC_Pos (0U)
hudakz 0:2cf53c219693 9591 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 9592 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
hudakz 0:2cf53c219693 9593
hudakz 0:2cf53c219693 9594 /****************** Bit definition for SPI_TXCRCR register ******************/
hudakz 0:2cf53c219693 9595 #define SPI_TXCRCR_TXCRC_Pos (0U)
hudakz 0:2cf53c219693 9596 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
hudakz 0:2cf53c219693 9597 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
hudakz 0:2cf53c219693 9598
hudakz 0:2cf53c219693 9599 /****************** Bit definition for SPI_I2SCFGR register *****************/
hudakz 0:2cf53c219693 9600 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
hudakz 0:2cf53c219693 9601 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9602 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
hudakz 0:2cf53c219693 9603
hudakz 0:2cf53c219693 9604
hudakz 0:2cf53c219693 9605 /******************************************************************************/
hudakz 0:2cf53c219693 9606 /* */
hudakz 0:2cf53c219693 9607 /* Inter-integrated Circuit Interface */
hudakz 0:2cf53c219693 9608 /* */
hudakz 0:2cf53c219693 9609 /******************************************************************************/
hudakz 0:2cf53c219693 9610
hudakz 0:2cf53c219693 9611 /******************* Bit definition for I2C_CR1 register ********************/
hudakz 0:2cf53c219693 9612 #define I2C_CR1_PE_Pos (0U)
hudakz 0:2cf53c219693 9613 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9614 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
hudakz 0:2cf53c219693 9615 #define I2C_CR1_SMBUS_Pos (1U)
hudakz 0:2cf53c219693 9616 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9617 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
hudakz 0:2cf53c219693 9618 #define I2C_CR1_SMBTYPE_Pos (3U)
hudakz 0:2cf53c219693 9619 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9620 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
hudakz 0:2cf53c219693 9621 #define I2C_CR1_ENARP_Pos (4U)
hudakz 0:2cf53c219693 9622 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9623 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
hudakz 0:2cf53c219693 9624 #define I2C_CR1_ENPEC_Pos (5U)
hudakz 0:2cf53c219693 9625 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9626 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
hudakz 0:2cf53c219693 9627 #define I2C_CR1_ENGC_Pos (6U)
hudakz 0:2cf53c219693 9628 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9629 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
hudakz 0:2cf53c219693 9630 #define I2C_CR1_NOSTRETCH_Pos (7U)
hudakz 0:2cf53c219693 9631 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9632 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
hudakz 0:2cf53c219693 9633 #define I2C_CR1_START_Pos (8U)
hudakz 0:2cf53c219693 9634 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9635 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
hudakz 0:2cf53c219693 9636 #define I2C_CR1_STOP_Pos (9U)
hudakz 0:2cf53c219693 9637 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9638 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
hudakz 0:2cf53c219693 9639 #define I2C_CR1_ACK_Pos (10U)
hudakz 0:2cf53c219693 9640 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9641 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
hudakz 0:2cf53c219693 9642 #define I2C_CR1_POS_Pos (11U)
hudakz 0:2cf53c219693 9643 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9644 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
hudakz 0:2cf53c219693 9645 #define I2C_CR1_PEC_Pos (12U)
hudakz 0:2cf53c219693 9646 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9647 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
hudakz 0:2cf53c219693 9648 #define I2C_CR1_ALERT_Pos (13U)
hudakz 0:2cf53c219693 9649 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9650 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
hudakz 0:2cf53c219693 9651 #define I2C_CR1_SWRST_Pos (15U)
hudakz 0:2cf53c219693 9652 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9653 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
hudakz 0:2cf53c219693 9654
hudakz 0:2cf53c219693 9655 /******************* Bit definition for I2C_CR2 register ********************/
hudakz 0:2cf53c219693 9656 #define I2C_CR2_FREQ_Pos (0U)
hudakz 0:2cf53c219693 9657 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
hudakz 0:2cf53c219693 9658 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
hudakz 0:2cf53c219693 9659 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9660 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9661 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9662 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9663 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9664 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9665
hudakz 0:2cf53c219693 9666 #define I2C_CR2_ITERREN_Pos (8U)
hudakz 0:2cf53c219693 9667 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9668 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
hudakz 0:2cf53c219693 9669 #define I2C_CR2_ITEVTEN_Pos (9U)
hudakz 0:2cf53c219693 9670 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9671 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
hudakz 0:2cf53c219693 9672 #define I2C_CR2_ITBUFEN_Pos (10U)
hudakz 0:2cf53c219693 9673 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9674 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
hudakz 0:2cf53c219693 9675 #define I2C_CR2_DMAEN_Pos (11U)
hudakz 0:2cf53c219693 9676 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9677 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
hudakz 0:2cf53c219693 9678 #define I2C_CR2_LAST_Pos (12U)
hudakz 0:2cf53c219693 9679 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9680 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
hudakz 0:2cf53c219693 9681
hudakz 0:2cf53c219693 9682 /******************* Bit definition for I2C_OAR1 register *******************/
hudakz 0:2cf53c219693 9683 #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
hudakz 0:2cf53c219693 9684 #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
hudakz 0:2cf53c219693 9685
hudakz 0:2cf53c219693 9686 #define I2C_OAR1_ADD0_Pos (0U)
hudakz 0:2cf53c219693 9687 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9688 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
hudakz 0:2cf53c219693 9689 #define I2C_OAR1_ADD1_Pos (1U)
hudakz 0:2cf53c219693 9690 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9691 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
hudakz 0:2cf53c219693 9692 #define I2C_OAR1_ADD2_Pos (2U)
hudakz 0:2cf53c219693 9693 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9694 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
hudakz 0:2cf53c219693 9695 #define I2C_OAR1_ADD3_Pos (3U)
hudakz 0:2cf53c219693 9696 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9697 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
hudakz 0:2cf53c219693 9698 #define I2C_OAR1_ADD4_Pos (4U)
hudakz 0:2cf53c219693 9699 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9700 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
hudakz 0:2cf53c219693 9701 #define I2C_OAR1_ADD5_Pos (5U)
hudakz 0:2cf53c219693 9702 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9703 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
hudakz 0:2cf53c219693 9704 #define I2C_OAR1_ADD6_Pos (6U)
hudakz 0:2cf53c219693 9705 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9706 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
hudakz 0:2cf53c219693 9707 #define I2C_OAR1_ADD7_Pos (7U)
hudakz 0:2cf53c219693 9708 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9709 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
hudakz 0:2cf53c219693 9710 #define I2C_OAR1_ADD8_Pos (8U)
hudakz 0:2cf53c219693 9711 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9712 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
hudakz 0:2cf53c219693 9713 #define I2C_OAR1_ADD9_Pos (9U)
hudakz 0:2cf53c219693 9714 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9715 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
hudakz 0:2cf53c219693 9716
hudakz 0:2cf53c219693 9717 #define I2C_OAR1_ADDMODE_Pos (15U)
hudakz 0:2cf53c219693 9718 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9719 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
hudakz 0:2cf53c219693 9720
hudakz 0:2cf53c219693 9721 /******************* Bit definition for I2C_OAR2 register *******************/
hudakz 0:2cf53c219693 9722 #define I2C_OAR2_ENDUAL_Pos (0U)
hudakz 0:2cf53c219693 9723 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9724 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
hudakz 0:2cf53c219693 9725 #define I2C_OAR2_ADD2_Pos (1U)
hudakz 0:2cf53c219693 9726 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
hudakz 0:2cf53c219693 9727 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
hudakz 0:2cf53c219693 9728
hudakz 0:2cf53c219693 9729 /******************** Bit definition for I2C_DR register ********************/
hudakz 0:2cf53c219693 9730 #define I2C_DR_DR_Pos (0U)
hudakz 0:2cf53c219693 9731 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 9732 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
hudakz 0:2cf53c219693 9733
hudakz 0:2cf53c219693 9734 /******************* Bit definition for I2C_SR1 register ********************/
hudakz 0:2cf53c219693 9735 #define I2C_SR1_SB_Pos (0U)
hudakz 0:2cf53c219693 9736 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9737 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
hudakz 0:2cf53c219693 9738 #define I2C_SR1_ADDR_Pos (1U)
hudakz 0:2cf53c219693 9739 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9740 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
hudakz 0:2cf53c219693 9741 #define I2C_SR1_BTF_Pos (2U)
hudakz 0:2cf53c219693 9742 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9743 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
hudakz 0:2cf53c219693 9744 #define I2C_SR1_ADD10_Pos (3U)
hudakz 0:2cf53c219693 9745 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9746 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
hudakz 0:2cf53c219693 9747 #define I2C_SR1_STOPF_Pos (4U)
hudakz 0:2cf53c219693 9748 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9749 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
hudakz 0:2cf53c219693 9750 #define I2C_SR1_RXNE_Pos (6U)
hudakz 0:2cf53c219693 9751 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9752 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
hudakz 0:2cf53c219693 9753 #define I2C_SR1_TXE_Pos (7U)
hudakz 0:2cf53c219693 9754 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9755 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
hudakz 0:2cf53c219693 9756 #define I2C_SR1_BERR_Pos (8U)
hudakz 0:2cf53c219693 9757 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9758 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
hudakz 0:2cf53c219693 9759 #define I2C_SR1_ARLO_Pos (9U)
hudakz 0:2cf53c219693 9760 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9761 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
hudakz 0:2cf53c219693 9762 #define I2C_SR1_AF_Pos (10U)
hudakz 0:2cf53c219693 9763 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9764 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
hudakz 0:2cf53c219693 9765 #define I2C_SR1_OVR_Pos (11U)
hudakz 0:2cf53c219693 9766 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9767 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
hudakz 0:2cf53c219693 9768 #define I2C_SR1_PECERR_Pos (12U)
hudakz 0:2cf53c219693 9769 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9770 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
hudakz 0:2cf53c219693 9771 #define I2C_SR1_TIMEOUT_Pos (14U)
hudakz 0:2cf53c219693 9772 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9773 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
hudakz 0:2cf53c219693 9774 #define I2C_SR1_SMBALERT_Pos (15U)
hudakz 0:2cf53c219693 9775 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9776 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
hudakz 0:2cf53c219693 9777
hudakz 0:2cf53c219693 9778 /******************* Bit definition for I2C_SR2 register ********************/
hudakz 0:2cf53c219693 9779 #define I2C_SR2_MSL_Pos (0U)
hudakz 0:2cf53c219693 9780 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9781 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
hudakz 0:2cf53c219693 9782 #define I2C_SR2_BUSY_Pos (1U)
hudakz 0:2cf53c219693 9783 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9784 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
hudakz 0:2cf53c219693 9785 #define I2C_SR2_TRA_Pos (2U)
hudakz 0:2cf53c219693 9786 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9787 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
hudakz 0:2cf53c219693 9788 #define I2C_SR2_GENCALL_Pos (4U)
hudakz 0:2cf53c219693 9789 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9790 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
hudakz 0:2cf53c219693 9791 #define I2C_SR2_SMBDEFAULT_Pos (5U)
hudakz 0:2cf53c219693 9792 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9793 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
hudakz 0:2cf53c219693 9794 #define I2C_SR2_SMBHOST_Pos (6U)
hudakz 0:2cf53c219693 9795 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9796 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
hudakz 0:2cf53c219693 9797 #define I2C_SR2_DUALF_Pos (7U)
hudakz 0:2cf53c219693 9798 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9799 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
hudakz 0:2cf53c219693 9800 #define I2C_SR2_PEC_Pos (8U)
hudakz 0:2cf53c219693 9801 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 9802 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
hudakz 0:2cf53c219693 9803
hudakz 0:2cf53c219693 9804 /******************* Bit definition for I2C_CCR register ********************/
hudakz 0:2cf53c219693 9805 #define I2C_CCR_CCR_Pos (0U)
hudakz 0:2cf53c219693 9806 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 9807 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
hudakz 0:2cf53c219693 9808 #define I2C_CCR_DUTY_Pos (14U)
hudakz 0:2cf53c219693 9809 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9810 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
hudakz 0:2cf53c219693 9811 #define I2C_CCR_FS_Pos (15U)
hudakz 0:2cf53c219693 9812 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 9813 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
hudakz 0:2cf53c219693 9814
hudakz 0:2cf53c219693 9815 /****************** Bit definition for I2C_TRISE register *******************/
hudakz 0:2cf53c219693 9816 #define I2C_TRISE_TRISE_Pos (0U)
hudakz 0:2cf53c219693 9817 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
hudakz 0:2cf53c219693 9818 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
hudakz 0:2cf53c219693 9819
hudakz 0:2cf53c219693 9820 /******************************************************************************/
hudakz 0:2cf53c219693 9821 /* */
hudakz 0:2cf53c219693 9822 /* Universal Synchronous Asynchronous Receiver Transmitter */
hudakz 0:2cf53c219693 9823 /* */
hudakz 0:2cf53c219693 9824 /******************************************************************************/
hudakz 0:2cf53c219693 9825
hudakz 0:2cf53c219693 9826 /******************* Bit definition for USART_SR register *******************/
hudakz 0:2cf53c219693 9827 #define USART_SR_PE_Pos (0U)
hudakz 0:2cf53c219693 9828 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9829 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
hudakz 0:2cf53c219693 9830 #define USART_SR_FE_Pos (1U)
hudakz 0:2cf53c219693 9831 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9832 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
hudakz 0:2cf53c219693 9833 #define USART_SR_NE_Pos (2U)
hudakz 0:2cf53c219693 9834 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9835 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
hudakz 0:2cf53c219693 9836 #define USART_SR_ORE_Pos (3U)
hudakz 0:2cf53c219693 9837 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9838 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
hudakz 0:2cf53c219693 9839 #define USART_SR_IDLE_Pos (4U)
hudakz 0:2cf53c219693 9840 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9841 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
hudakz 0:2cf53c219693 9842 #define USART_SR_RXNE_Pos (5U)
hudakz 0:2cf53c219693 9843 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9844 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
hudakz 0:2cf53c219693 9845 #define USART_SR_TC_Pos (6U)
hudakz 0:2cf53c219693 9846 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9847 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
hudakz 0:2cf53c219693 9848 #define USART_SR_TXE_Pos (7U)
hudakz 0:2cf53c219693 9849 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9850 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
hudakz 0:2cf53c219693 9851 #define USART_SR_LBD_Pos (8U)
hudakz 0:2cf53c219693 9852 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9853 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
hudakz 0:2cf53c219693 9854 #define USART_SR_CTS_Pos (9U)
hudakz 0:2cf53c219693 9855 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9856 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
hudakz 0:2cf53c219693 9857
hudakz 0:2cf53c219693 9858 /******************* Bit definition for USART_DR register *******************/
hudakz 0:2cf53c219693 9859 #define USART_DR_DR_Pos (0U)
hudakz 0:2cf53c219693 9860 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
hudakz 0:2cf53c219693 9861 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
hudakz 0:2cf53c219693 9862
hudakz 0:2cf53c219693 9863 /****************** Bit definition for USART_BRR register *******************/
hudakz 0:2cf53c219693 9864 #define USART_BRR_DIV_Fraction_Pos (0U)
hudakz 0:2cf53c219693 9865 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 9866 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
hudakz 0:2cf53c219693 9867 #define USART_BRR_DIV_Mantissa_Pos (4U)
hudakz 0:2cf53c219693 9868 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
hudakz 0:2cf53c219693 9869 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
hudakz 0:2cf53c219693 9870
hudakz 0:2cf53c219693 9871 /****************** Bit definition for USART_CR1 register *******************/
hudakz 0:2cf53c219693 9872 #define USART_CR1_SBK_Pos (0U)
hudakz 0:2cf53c219693 9873 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9874 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
hudakz 0:2cf53c219693 9875 #define USART_CR1_RWU_Pos (1U)
hudakz 0:2cf53c219693 9876 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9877 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
hudakz 0:2cf53c219693 9878 #define USART_CR1_RE_Pos (2U)
hudakz 0:2cf53c219693 9879 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9880 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
hudakz 0:2cf53c219693 9881 #define USART_CR1_TE_Pos (3U)
hudakz 0:2cf53c219693 9882 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9883 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
hudakz 0:2cf53c219693 9884 #define USART_CR1_IDLEIE_Pos (4U)
hudakz 0:2cf53c219693 9885 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9886 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
hudakz 0:2cf53c219693 9887 #define USART_CR1_RXNEIE_Pos (5U)
hudakz 0:2cf53c219693 9888 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9889 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
hudakz 0:2cf53c219693 9890 #define USART_CR1_TCIE_Pos (6U)
hudakz 0:2cf53c219693 9891 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9892 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
hudakz 0:2cf53c219693 9893 #define USART_CR1_TXEIE_Pos (7U)
hudakz 0:2cf53c219693 9894 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9895 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
hudakz 0:2cf53c219693 9896 #define USART_CR1_PEIE_Pos (8U)
hudakz 0:2cf53c219693 9897 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9898 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
hudakz 0:2cf53c219693 9899 #define USART_CR1_PS_Pos (9U)
hudakz 0:2cf53c219693 9900 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9901 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
hudakz 0:2cf53c219693 9902 #define USART_CR1_PCE_Pos (10U)
hudakz 0:2cf53c219693 9903 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9904 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
hudakz 0:2cf53c219693 9905 #define USART_CR1_WAKE_Pos (11U)
hudakz 0:2cf53c219693 9906 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9907 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
hudakz 0:2cf53c219693 9908 #define USART_CR1_M_Pos (12U)
hudakz 0:2cf53c219693 9909 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9910 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
hudakz 0:2cf53c219693 9911 #define USART_CR1_UE_Pos (13U)
hudakz 0:2cf53c219693 9912 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9913 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
hudakz 0:2cf53c219693 9914
hudakz 0:2cf53c219693 9915 /****************** Bit definition for USART_CR2 register *******************/
hudakz 0:2cf53c219693 9916 #define USART_CR2_ADD_Pos (0U)
hudakz 0:2cf53c219693 9917 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
hudakz 0:2cf53c219693 9918 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
hudakz 0:2cf53c219693 9919 #define USART_CR2_LBDL_Pos (5U)
hudakz 0:2cf53c219693 9920 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9921 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
hudakz 0:2cf53c219693 9922 #define USART_CR2_LBDIE_Pos (6U)
hudakz 0:2cf53c219693 9923 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9924 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
hudakz 0:2cf53c219693 9925 #define USART_CR2_LBCL_Pos (8U)
hudakz 0:2cf53c219693 9926 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9927 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
hudakz 0:2cf53c219693 9928 #define USART_CR2_CPHA_Pos (9U)
hudakz 0:2cf53c219693 9929 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9930 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
hudakz 0:2cf53c219693 9931 #define USART_CR2_CPOL_Pos (10U)
hudakz 0:2cf53c219693 9932 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9933 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
hudakz 0:2cf53c219693 9934 #define USART_CR2_CLKEN_Pos (11U)
hudakz 0:2cf53c219693 9935 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 9936 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
hudakz 0:2cf53c219693 9937
hudakz 0:2cf53c219693 9938 #define USART_CR2_STOP_Pos (12U)
hudakz 0:2cf53c219693 9939 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
hudakz 0:2cf53c219693 9940 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
hudakz 0:2cf53c219693 9941 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 9942 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 9943
hudakz 0:2cf53c219693 9944 #define USART_CR2_LINEN_Pos (14U)
hudakz 0:2cf53c219693 9945 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 9946 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
hudakz 0:2cf53c219693 9947
hudakz 0:2cf53c219693 9948 /****************** Bit definition for USART_CR3 register *******************/
hudakz 0:2cf53c219693 9949 #define USART_CR3_EIE_Pos (0U)
hudakz 0:2cf53c219693 9950 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9951 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
hudakz 0:2cf53c219693 9952 #define USART_CR3_IREN_Pos (1U)
hudakz 0:2cf53c219693 9953 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9954 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
hudakz 0:2cf53c219693 9955 #define USART_CR3_IRLP_Pos (2U)
hudakz 0:2cf53c219693 9956 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9957 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
hudakz 0:2cf53c219693 9958 #define USART_CR3_HDSEL_Pos (3U)
hudakz 0:2cf53c219693 9959 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9960 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
hudakz 0:2cf53c219693 9961 #define USART_CR3_NACK_Pos (4U)
hudakz 0:2cf53c219693 9962 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9963 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
hudakz 0:2cf53c219693 9964 #define USART_CR3_SCEN_Pos (5U)
hudakz 0:2cf53c219693 9965 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9966 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
hudakz 0:2cf53c219693 9967 #define USART_CR3_DMAR_Pos (6U)
hudakz 0:2cf53c219693 9968 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9969 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
hudakz 0:2cf53c219693 9970 #define USART_CR3_DMAT_Pos (7U)
hudakz 0:2cf53c219693 9971 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9972 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
hudakz 0:2cf53c219693 9973 #define USART_CR3_RTSE_Pos (8U)
hudakz 0:2cf53c219693 9974 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 9975 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
hudakz 0:2cf53c219693 9976 #define USART_CR3_CTSE_Pos (9U)
hudakz 0:2cf53c219693 9977 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 9978 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
hudakz 0:2cf53c219693 9979 #define USART_CR3_CTSIE_Pos (10U)
hudakz 0:2cf53c219693 9980 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 9981 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
hudakz 0:2cf53c219693 9982
hudakz 0:2cf53c219693 9983 /****************** Bit definition for USART_GTPR register ******************/
hudakz 0:2cf53c219693 9984 #define USART_GTPR_PSC_Pos (0U)
hudakz 0:2cf53c219693 9985 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 9986 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
hudakz 0:2cf53c219693 9987 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 9988 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 9989 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 9990 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 9991 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 9992 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 9993 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 9994 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 9995
hudakz 0:2cf53c219693 9996 #define USART_GTPR_GT_Pos (8U)
hudakz 0:2cf53c219693 9997 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 9998 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
hudakz 0:2cf53c219693 9999
hudakz 0:2cf53c219693 10000 /******************************************************************************/
hudakz 0:2cf53c219693 10001 /* */
hudakz 0:2cf53c219693 10002 /* Debug MCU */
hudakz 0:2cf53c219693 10003 /* */
hudakz 0:2cf53c219693 10004 /******************************************************************************/
hudakz 0:2cf53c219693 10005
hudakz 0:2cf53c219693 10006 /**************** Bit definition for DBGMCU_IDCODE register *****************/
hudakz 0:2cf53c219693 10007 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
hudakz 0:2cf53c219693 10008 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
hudakz 0:2cf53c219693 10009 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
hudakz 0:2cf53c219693 10010
hudakz 0:2cf53c219693 10011 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
hudakz 0:2cf53c219693 10012 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
hudakz 0:2cf53c219693 10013 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
hudakz 0:2cf53c219693 10014 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 10015 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
hudakz 0:2cf53c219693 10016 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
hudakz 0:2cf53c219693 10017 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
hudakz 0:2cf53c219693 10018 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
hudakz 0:2cf53c219693 10019 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
hudakz 0:2cf53c219693 10020 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
hudakz 0:2cf53c219693 10021 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
hudakz 0:2cf53c219693 10022 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
hudakz 0:2cf53c219693 10023 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
hudakz 0:2cf53c219693 10024 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
hudakz 0:2cf53c219693 10025 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
hudakz 0:2cf53c219693 10026 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
hudakz 0:2cf53c219693 10027 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
hudakz 0:2cf53c219693 10028 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
hudakz 0:2cf53c219693 10029 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
hudakz 0:2cf53c219693 10030
hudakz 0:2cf53c219693 10031 /****************** Bit definition for DBGMCU_CR register *******************/
hudakz 0:2cf53c219693 10032 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
hudakz 0:2cf53c219693 10033 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 10034 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
hudakz 0:2cf53c219693 10035 #define DBGMCU_CR_DBG_STOP_Pos (1U)
hudakz 0:2cf53c219693 10036 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 10037 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
hudakz 0:2cf53c219693 10038 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
hudakz 0:2cf53c219693 10039 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 10040 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
hudakz 0:2cf53c219693 10041 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
hudakz 0:2cf53c219693 10042 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 10043 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
hudakz 0:2cf53c219693 10044
hudakz 0:2cf53c219693 10045 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
hudakz 0:2cf53c219693 10046 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
hudakz 0:2cf53c219693 10047 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
hudakz 0:2cf53c219693 10048 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 10049 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 10050
hudakz 0:2cf53c219693 10051 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
hudakz 0:2cf53c219693 10052 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
hudakz 0:2cf53c219693 10053 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
hudakz 0:2cf53c219693 10054 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
hudakz 0:2cf53c219693 10055 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 10056 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
hudakz 0:2cf53c219693 10057 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
hudakz 0:2cf53c219693 10058 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 10059 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
hudakz 0:2cf53c219693 10060 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
hudakz 0:2cf53c219693 10061 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
hudakz 0:2cf53c219693 10062 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
hudakz 0:2cf53c219693 10063 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
hudakz 0:2cf53c219693 10064 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 10065 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
hudakz 0:2cf53c219693 10066 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
hudakz 0:2cf53c219693 10067 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
hudakz 0:2cf53c219693 10068 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
hudakz 0:2cf53c219693 10069 #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
hudakz 0:2cf53c219693 10070 #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
hudakz 0:2cf53c219693 10071 #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
hudakz 0:2cf53c219693 10072 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
hudakz 0:2cf53c219693 10073 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
hudakz 0:2cf53c219693 10074 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
hudakz 0:2cf53c219693 10075 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
hudakz 0:2cf53c219693 10076 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
hudakz 0:2cf53c219693 10077 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
hudakz 0:2cf53c219693 10078
hudakz 0:2cf53c219693 10079 /******************************************************************************/
hudakz 0:2cf53c219693 10080 /* */
hudakz 0:2cf53c219693 10081 /* FLASH and Option Bytes Registers */
hudakz 0:2cf53c219693 10082 /* */
hudakz 0:2cf53c219693 10083 /******************************************************************************/
hudakz 0:2cf53c219693 10084 /******************* Bit definition for FLASH_ACR register ******************/
hudakz 0:2cf53c219693 10085 #define FLASH_ACR_LATENCY_Pos (0U)
hudakz 0:2cf53c219693 10086 #define FLASH_ACR_LATENCY_Msk (0x7U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
hudakz 0:2cf53c219693 10087 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
hudakz 0:2cf53c219693 10088 #define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 10089 #define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 10090 #define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 10091
hudakz 0:2cf53c219693 10092 #define FLASH_ACR_HLFCYA_Pos (3U)
hudakz 0:2cf53c219693 10093 #define FLASH_ACR_HLFCYA_Msk (0x1U << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 10094 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
hudakz 0:2cf53c219693 10095 #define FLASH_ACR_PRFTBE_Pos (4U)
hudakz 0:2cf53c219693 10096 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 10097 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
hudakz 0:2cf53c219693 10098 #define FLASH_ACR_PRFTBS_Pos (5U)
hudakz 0:2cf53c219693 10099 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 10100 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
hudakz 0:2cf53c219693 10101
hudakz 0:2cf53c219693 10102 /****************** Bit definition for FLASH_KEYR register ******************/
hudakz 0:2cf53c219693 10103 #define FLASH_KEYR_FKEYR_Pos (0U)
hudakz 0:2cf53c219693 10104 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 10105 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
hudakz 0:2cf53c219693 10106
hudakz 0:2cf53c219693 10107 #define RDP_KEY_Pos (0U)
hudakz 0:2cf53c219693 10108 #define RDP_KEY_Msk (0xA5U << RDP_KEY_Pos) /*!< 0x000000A5 */
hudakz 0:2cf53c219693 10109 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
hudakz 0:2cf53c219693 10110 #define FLASH_KEY1_Pos (0U)
hudakz 0:2cf53c219693 10111 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
hudakz 0:2cf53c219693 10112 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
hudakz 0:2cf53c219693 10113 #define FLASH_KEY2_Pos (0U)
hudakz 0:2cf53c219693 10114 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
hudakz 0:2cf53c219693 10115 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
hudakz 0:2cf53c219693 10116
hudakz 0:2cf53c219693 10117 /***************** Bit definition for FLASH_OPTKEYR register ****************/
hudakz 0:2cf53c219693 10118 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
hudakz 0:2cf53c219693 10119 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 10120 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
hudakz 0:2cf53c219693 10121
hudakz 0:2cf53c219693 10122 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
hudakz 0:2cf53c219693 10123 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
hudakz 0:2cf53c219693 10124
hudakz 0:2cf53c219693 10125 /****************** Bit definition for FLASH_SR register ********************/
hudakz 0:2cf53c219693 10126 #define FLASH_SR_BSY_Pos (0U)
hudakz 0:2cf53c219693 10127 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 10128 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
hudakz 0:2cf53c219693 10129 #define FLASH_SR_PGERR_Pos (2U)
hudakz 0:2cf53c219693 10130 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 10131 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
hudakz 0:2cf53c219693 10132 #define FLASH_SR_WRPRTERR_Pos (4U)
hudakz 0:2cf53c219693 10133 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 10134 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
hudakz 0:2cf53c219693 10135 #define FLASH_SR_EOP_Pos (5U)
hudakz 0:2cf53c219693 10136 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 10137 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
hudakz 0:2cf53c219693 10138
hudakz 0:2cf53c219693 10139 /******************* Bit definition for FLASH_CR register *******************/
hudakz 0:2cf53c219693 10140 #define FLASH_CR_PG_Pos (0U)
hudakz 0:2cf53c219693 10141 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 10142 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
hudakz 0:2cf53c219693 10143 #define FLASH_CR_PER_Pos (1U)
hudakz 0:2cf53c219693 10144 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 10145 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
hudakz 0:2cf53c219693 10146 #define FLASH_CR_MER_Pos (2U)
hudakz 0:2cf53c219693 10147 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 10148 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
hudakz 0:2cf53c219693 10149 #define FLASH_CR_OPTPG_Pos (4U)
hudakz 0:2cf53c219693 10150 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 10151 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
hudakz 0:2cf53c219693 10152 #define FLASH_CR_OPTER_Pos (5U)
hudakz 0:2cf53c219693 10153 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
hudakz 0:2cf53c219693 10154 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
hudakz 0:2cf53c219693 10155 #define FLASH_CR_STRT_Pos (6U)
hudakz 0:2cf53c219693 10156 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
hudakz 0:2cf53c219693 10157 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
hudakz 0:2cf53c219693 10158 #define FLASH_CR_LOCK_Pos (7U)
hudakz 0:2cf53c219693 10159 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
hudakz 0:2cf53c219693 10160 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
hudakz 0:2cf53c219693 10161 #define FLASH_CR_OPTWRE_Pos (9U)
hudakz 0:2cf53c219693 10162 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
hudakz 0:2cf53c219693 10163 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
hudakz 0:2cf53c219693 10164 #define FLASH_CR_ERRIE_Pos (10U)
hudakz 0:2cf53c219693 10165 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
hudakz 0:2cf53c219693 10166 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
hudakz 0:2cf53c219693 10167 #define FLASH_CR_EOPIE_Pos (12U)
hudakz 0:2cf53c219693 10168 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
hudakz 0:2cf53c219693 10169 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
hudakz 0:2cf53c219693 10170
hudakz 0:2cf53c219693 10171 /******************* Bit definition for FLASH_AR register *******************/
hudakz 0:2cf53c219693 10172 #define FLASH_AR_FAR_Pos (0U)
hudakz 0:2cf53c219693 10173 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 10174 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
hudakz 0:2cf53c219693 10175
hudakz 0:2cf53c219693 10176 /****************** Bit definition for FLASH_OBR register *******************/
hudakz 0:2cf53c219693 10177 #define FLASH_OBR_OPTERR_Pos (0U)
hudakz 0:2cf53c219693 10178 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
hudakz 0:2cf53c219693 10179 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
hudakz 0:2cf53c219693 10180 #define FLASH_OBR_RDPRT_Pos (1U)
hudakz 0:2cf53c219693 10181 #define FLASH_OBR_RDPRT_Msk (0x1U << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
hudakz 0:2cf53c219693 10182 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
hudakz 0:2cf53c219693 10183
hudakz 0:2cf53c219693 10184 #define FLASH_OBR_IWDG_SW_Pos (2U)
hudakz 0:2cf53c219693 10185 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
hudakz 0:2cf53c219693 10186 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
hudakz 0:2cf53c219693 10187 #define FLASH_OBR_nRST_STOP_Pos (3U)
hudakz 0:2cf53c219693 10188 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
hudakz 0:2cf53c219693 10189 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
hudakz 0:2cf53c219693 10190 #define FLASH_OBR_nRST_STDBY_Pos (4U)
hudakz 0:2cf53c219693 10191 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
hudakz 0:2cf53c219693 10192 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
hudakz 0:2cf53c219693 10193 #define FLASH_OBR_USER_Pos (2U)
hudakz 0:2cf53c219693 10194 #define FLASH_OBR_USER_Msk (0x7U << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
hudakz 0:2cf53c219693 10195 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
hudakz 0:2cf53c219693 10196 #define FLASH_OBR_DATA0_Pos (10U)
hudakz 0:2cf53c219693 10197 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
hudakz 0:2cf53c219693 10198 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
hudakz 0:2cf53c219693 10199 #define FLASH_OBR_DATA1_Pos (18U)
hudakz 0:2cf53c219693 10200 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
hudakz 0:2cf53c219693 10201 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
hudakz 0:2cf53c219693 10202
hudakz 0:2cf53c219693 10203 /****************** Bit definition for FLASH_WRPR register ******************/
hudakz 0:2cf53c219693 10204 #define FLASH_WRPR_WRP_Pos (0U)
hudakz 0:2cf53c219693 10205 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
hudakz 0:2cf53c219693 10206 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
hudakz 0:2cf53c219693 10207
hudakz 0:2cf53c219693 10208 /*----------------------------------------------------------------------------*/
hudakz 0:2cf53c219693 10209
hudakz 0:2cf53c219693 10210 /****************** Bit definition for FLASH_RDP register *******************/
hudakz 0:2cf53c219693 10211 #define FLASH_RDP_RDP_Pos (0U)
hudakz 0:2cf53c219693 10212 #define FLASH_RDP_RDP_Msk (0xFFU << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 10213 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
hudakz 0:2cf53c219693 10214 #define FLASH_RDP_nRDP_Pos (8U)
hudakz 0:2cf53c219693 10215 #define FLASH_RDP_nRDP_Msk (0xFFU << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 10216 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
hudakz 0:2cf53c219693 10217
hudakz 0:2cf53c219693 10218 /****************** Bit definition for FLASH_USER register ******************/
hudakz 0:2cf53c219693 10219 #define FLASH_USER_USER_Pos (16U)
hudakz 0:2cf53c219693 10220 #define FLASH_USER_USER_Msk (0xFFU << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 10221 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
hudakz 0:2cf53c219693 10222 #define FLASH_USER_nUSER_Pos (24U)
hudakz 0:2cf53c219693 10223 #define FLASH_USER_nUSER_Msk (0xFFU << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 10224 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
hudakz 0:2cf53c219693 10225
hudakz 0:2cf53c219693 10226 /****************** Bit definition for FLASH_Data0 register *****************/
hudakz 0:2cf53c219693 10227 #define FLASH_DATA0_DATA0_Pos (0U)
hudakz 0:2cf53c219693 10228 #define FLASH_DATA0_DATA0_Msk (0xFFU << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 10229 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
hudakz 0:2cf53c219693 10230 #define FLASH_DATA0_nDATA0_Pos (8U)
hudakz 0:2cf53c219693 10231 #define FLASH_DATA0_nDATA0_Msk (0xFFU << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 10232 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
hudakz 0:2cf53c219693 10233
hudakz 0:2cf53c219693 10234 /****************** Bit definition for FLASH_Data1 register *****************/
hudakz 0:2cf53c219693 10235 #define FLASH_DATA1_DATA1_Pos (16U)
hudakz 0:2cf53c219693 10236 #define FLASH_DATA1_DATA1_Msk (0xFFU << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 10237 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
hudakz 0:2cf53c219693 10238 #define FLASH_DATA1_nDATA1_Pos (24U)
hudakz 0:2cf53c219693 10239 #define FLASH_DATA1_nDATA1_Msk (0xFFU << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 10240 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
hudakz 0:2cf53c219693 10241
hudakz 0:2cf53c219693 10242 /****************** Bit definition for FLASH_WRP0 register ******************/
hudakz 0:2cf53c219693 10243 #define FLASH_WRP0_WRP0_Pos (0U)
hudakz 0:2cf53c219693 10244 #define FLASH_WRP0_WRP0_Msk (0xFFU << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 10245 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
hudakz 0:2cf53c219693 10246 #define FLASH_WRP0_nWRP0_Pos (8U)
hudakz 0:2cf53c219693 10247 #define FLASH_WRP0_nWRP0_Msk (0xFFU << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 10248 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
hudakz 0:2cf53c219693 10249
hudakz 0:2cf53c219693 10250 /****************** Bit definition for FLASH_WRP1 register ******************/
hudakz 0:2cf53c219693 10251 #define FLASH_WRP1_WRP1_Pos (16U)
hudakz 0:2cf53c219693 10252 #define FLASH_WRP1_WRP1_Msk (0xFFU << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 10253 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
hudakz 0:2cf53c219693 10254 #define FLASH_WRP1_nWRP1_Pos (24U)
hudakz 0:2cf53c219693 10255 #define FLASH_WRP1_nWRP1_Msk (0xFFU << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 10256 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
hudakz 0:2cf53c219693 10257
hudakz 0:2cf53c219693 10258 /****************** Bit definition for FLASH_WRP2 register ******************/
hudakz 0:2cf53c219693 10259 #define FLASH_WRP2_WRP2_Pos (0U)
hudakz 0:2cf53c219693 10260 #define FLASH_WRP2_WRP2_Msk (0xFFU << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
hudakz 0:2cf53c219693 10261 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
hudakz 0:2cf53c219693 10262 #define FLASH_WRP2_nWRP2_Pos (8U)
hudakz 0:2cf53c219693 10263 #define FLASH_WRP2_nWRP2_Msk (0xFFU << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
hudakz 0:2cf53c219693 10264 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
hudakz 0:2cf53c219693 10265
hudakz 0:2cf53c219693 10266 /****************** Bit definition for FLASH_WRP3 register ******************/
hudakz 0:2cf53c219693 10267 #define FLASH_WRP3_WRP3_Pos (16U)
hudakz 0:2cf53c219693 10268 #define FLASH_WRP3_WRP3_Msk (0xFFU << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
hudakz 0:2cf53c219693 10269 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
hudakz 0:2cf53c219693 10270 #define FLASH_WRP3_nWRP3_Pos (24U)
hudakz 0:2cf53c219693 10271 #define FLASH_WRP3_nWRP3_Msk (0xFFU << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
hudakz 0:2cf53c219693 10272 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
hudakz 0:2cf53c219693 10273
hudakz 0:2cf53c219693 10274
hudakz 0:2cf53c219693 10275
hudakz 0:2cf53c219693 10276 /**
hudakz 0:2cf53c219693 10277 * @}
hudakz 0:2cf53c219693 10278 */
hudakz 0:2cf53c219693 10279
hudakz 0:2cf53c219693 10280 /**
hudakz 0:2cf53c219693 10281 * @}
hudakz 0:2cf53c219693 10282 */
hudakz 0:2cf53c219693 10283
hudakz 0:2cf53c219693 10284 /** @addtogroup Exported_macro
hudakz 0:2cf53c219693 10285 * @{
hudakz 0:2cf53c219693 10286 */
hudakz 0:2cf53c219693 10287
hudakz 0:2cf53c219693 10288 /****************************** ADC Instances *********************************/
hudakz 0:2cf53c219693 10289 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
hudakz 0:2cf53c219693 10290 ((INSTANCE) == ADC2))
hudakz 0:2cf53c219693 10291
hudakz 0:2cf53c219693 10292 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
hudakz 0:2cf53c219693 10293
hudakz 0:2cf53c219693 10294 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
hudakz 0:2cf53c219693 10295
hudakz 0:2cf53c219693 10296 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
hudakz 0:2cf53c219693 10297
hudakz 0:2cf53c219693 10298 /****************************** CAN Instances *********************************/
hudakz 0:2cf53c219693 10299 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
hudakz 0:2cf53c219693 10300
hudakz 0:2cf53c219693 10301 /****************************** CRC Instances *********************************/
hudakz 0:2cf53c219693 10302 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
hudakz 0:2cf53c219693 10303
hudakz 0:2cf53c219693 10304 /****************************** DAC Instances *********************************/
hudakz 0:2cf53c219693 10305
hudakz 0:2cf53c219693 10306 /****************************** DMA Instances *********************************/
hudakz 0:2cf53c219693 10307 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
hudakz 0:2cf53c219693 10308 ((INSTANCE) == DMA1_Channel2) || \
hudakz 0:2cf53c219693 10309 ((INSTANCE) == DMA1_Channel3) || \
hudakz 0:2cf53c219693 10310 ((INSTANCE) == DMA1_Channel4) || \
hudakz 0:2cf53c219693 10311 ((INSTANCE) == DMA1_Channel5) || \
hudakz 0:2cf53c219693 10312 ((INSTANCE) == DMA1_Channel6) || \
hudakz 0:2cf53c219693 10313 ((INSTANCE) == DMA1_Channel7))
hudakz 0:2cf53c219693 10314
hudakz 0:2cf53c219693 10315 /******************************* GPIO Instances *******************************/
hudakz 0:2cf53c219693 10316 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
hudakz 0:2cf53c219693 10317 ((INSTANCE) == GPIOB) || \
hudakz 0:2cf53c219693 10318 ((INSTANCE) == GPIOC) || \
hudakz 0:2cf53c219693 10319 ((INSTANCE) == GPIOD) || \
hudakz 0:2cf53c219693 10320 ((INSTANCE) == GPIOE))
hudakz 0:2cf53c219693 10321
hudakz 0:2cf53c219693 10322 /**************************** GPIO Alternate Function Instances ***************/
hudakz 0:2cf53c219693 10323 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
hudakz 0:2cf53c219693 10324
hudakz 0:2cf53c219693 10325 /**************************** GPIO Lock Instances *****************************/
hudakz 0:2cf53c219693 10326 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
hudakz 0:2cf53c219693 10327
hudakz 0:2cf53c219693 10328 /******************************** I2C Instances *******************************/
hudakz 0:2cf53c219693 10329 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
hudakz 0:2cf53c219693 10330 ((INSTANCE) == I2C2))
hudakz 0:2cf53c219693 10331
hudakz 0:2cf53c219693 10332 /******************************* SMBUS Instances ******************************/
hudakz 0:2cf53c219693 10333 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
hudakz 0:2cf53c219693 10334
hudakz 0:2cf53c219693 10335 /****************************** IWDG Instances ********************************/
hudakz 0:2cf53c219693 10336 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
hudakz 0:2cf53c219693 10337
hudakz 0:2cf53c219693 10338 /******************************** SPI Instances *******************************/
hudakz 0:2cf53c219693 10339 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
hudakz 0:2cf53c219693 10340 ((INSTANCE) == SPI2))
hudakz 0:2cf53c219693 10341
hudakz 0:2cf53c219693 10342 /****************************** START TIM Instances ***************************/
hudakz 0:2cf53c219693 10343 /****************************** TIM Instances *********************************/
hudakz 0:2cf53c219693 10344 #define IS_TIM_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10345 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10346 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10347 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10348 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10349
hudakz 0:2cf53c219693 10350 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
hudakz 0:2cf53c219693 10351
hudakz 0:2cf53c219693 10352 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10353 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10354 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10355 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10356 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10357
hudakz 0:2cf53c219693 10358 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10359 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10360 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10361 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10362 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10363
hudakz 0:2cf53c219693 10364 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10365 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10366 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10367 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10368 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10369
hudakz 0:2cf53c219693 10370 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10371 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10372 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10373 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10374 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10375
hudakz 0:2cf53c219693 10376 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10377 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10378 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10379 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10380 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10381
hudakz 0:2cf53c219693 10382 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10383 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10384 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10385 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10386 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10387
hudakz 0:2cf53c219693 10388 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10389 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10390 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10391 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10392 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10393
hudakz 0:2cf53c219693 10394 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10395 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10396 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10397 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10398 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10399
hudakz 0:2cf53c219693 10400 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10401 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10402 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10403 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10404 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10405
hudakz 0:2cf53c219693 10406 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10407 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10408 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10409 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10410 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10411
hudakz 0:2cf53c219693 10412 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10413 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10414 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10415 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10416 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10417
hudakz 0:2cf53c219693 10418 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10419 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10420 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10421 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10422 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10423
hudakz 0:2cf53c219693 10424 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10425 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10426 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10427 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10428 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10429
hudakz 0:2cf53c219693 10430 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10431 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10432 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10433 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10434 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10435
hudakz 0:2cf53c219693 10436 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10437 ((INSTANCE) == TIM1)
hudakz 0:2cf53c219693 10438
hudakz 0:2cf53c219693 10439 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
hudakz 0:2cf53c219693 10440 ((((INSTANCE) == TIM1) && \
hudakz 0:2cf53c219693 10441 (((CHANNEL) == TIM_CHANNEL_1) || \
hudakz 0:2cf53c219693 10442 ((CHANNEL) == TIM_CHANNEL_2) || \
hudakz 0:2cf53c219693 10443 ((CHANNEL) == TIM_CHANNEL_3) || \
hudakz 0:2cf53c219693 10444 ((CHANNEL) == TIM_CHANNEL_4))) \
hudakz 0:2cf53c219693 10445 || \
hudakz 0:2cf53c219693 10446 (((INSTANCE) == TIM2) && \
hudakz 0:2cf53c219693 10447 (((CHANNEL) == TIM_CHANNEL_1) || \
hudakz 0:2cf53c219693 10448 ((CHANNEL) == TIM_CHANNEL_2) || \
hudakz 0:2cf53c219693 10449 ((CHANNEL) == TIM_CHANNEL_3) || \
hudakz 0:2cf53c219693 10450 ((CHANNEL) == TIM_CHANNEL_4))) \
hudakz 0:2cf53c219693 10451 || \
hudakz 0:2cf53c219693 10452 (((INSTANCE) == TIM3) && \
hudakz 0:2cf53c219693 10453 (((CHANNEL) == TIM_CHANNEL_1) || \
hudakz 0:2cf53c219693 10454 ((CHANNEL) == TIM_CHANNEL_2) || \
hudakz 0:2cf53c219693 10455 ((CHANNEL) == TIM_CHANNEL_3) || \
hudakz 0:2cf53c219693 10456 ((CHANNEL) == TIM_CHANNEL_4))) \
hudakz 0:2cf53c219693 10457 || \
hudakz 0:2cf53c219693 10458 (((INSTANCE) == TIM4) && \
hudakz 0:2cf53c219693 10459 (((CHANNEL) == TIM_CHANNEL_1) || \
hudakz 0:2cf53c219693 10460 ((CHANNEL) == TIM_CHANNEL_2) || \
hudakz 0:2cf53c219693 10461 ((CHANNEL) == TIM_CHANNEL_3) || \
hudakz 0:2cf53c219693 10462 ((CHANNEL) == TIM_CHANNEL_4))))
hudakz 0:2cf53c219693 10463
hudakz 0:2cf53c219693 10464 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
hudakz 0:2cf53c219693 10465 (((INSTANCE) == TIM1) && \
hudakz 0:2cf53c219693 10466 (((CHANNEL) == TIM_CHANNEL_1) || \
hudakz 0:2cf53c219693 10467 ((CHANNEL) == TIM_CHANNEL_2) || \
hudakz 0:2cf53c219693 10468 ((CHANNEL) == TIM_CHANNEL_3)))
hudakz 0:2cf53c219693 10469
hudakz 0:2cf53c219693 10470 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10471 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10472 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10473 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10474 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10475
hudakz 0:2cf53c219693 10476 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10477 ((INSTANCE) == TIM1)
hudakz 0:2cf53c219693 10478
hudakz 0:2cf53c219693 10479 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10480 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10481 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10482 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10483 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10484
hudakz 0:2cf53c219693 10485 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10486 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10487 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10488 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10489 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10490
hudakz 0:2cf53c219693 10491 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10492 (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10493 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10494 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10495 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10496
hudakz 0:2cf53c219693 10497 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
hudakz 0:2cf53c219693 10498 ((INSTANCE) == TIM1)
hudakz 0:2cf53c219693 10499
hudakz 0:2cf53c219693 10500 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10501 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10502 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10503 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10504
hudakz 0:2cf53c219693 10505 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
hudakz 0:2cf53c219693 10506 ((INSTANCE) == TIM2) || \
hudakz 0:2cf53c219693 10507 ((INSTANCE) == TIM3) || \
hudakz 0:2cf53c219693 10508 ((INSTANCE) == TIM4))
hudakz 0:2cf53c219693 10509
hudakz 0:2cf53c219693 10510 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
hudakz 0:2cf53c219693 10511
hudakz 0:2cf53c219693 10512 /****************************** END TIM Instances *****************************/
hudakz 0:2cf53c219693 10513
hudakz 0:2cf53c219693 10514
hudakz 0:2cf53c219693 10515 /******************** USART Instances : Synchronous mode **********************/
hudakz 0:2cf53c219693 10516 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10517 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10518 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10519
hudakz 0:2cf53c219693 10520 /******************** UART Instances : Asynchronous mode **********************/
hudakz 0:2cf53c219693 10521 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10522 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10523 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10524
hudakz 0:2cf53c219693 10525 /******************** UART Instances : Half-Duplex mode **********************/
hudakz 0:2cf53c219693 10526 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10527 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10528 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10529
hudakz 0:2cf53c219693 10530 /******************** UART Instances : LIN mode **********************/
hudakz 0:2cf53c219693 10531 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10532 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10533 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10534
hudakz 0:2cf53c219693 10535 /****************** UART Instances : Hardware Flow control ********************/
hudakz 0:2cf53c219693 10536 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10537 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10538 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10539
hudakz 0:2cf53c219693 10540 /********************* UART Instances : Smard card mode ***********************/
hudakz 0:2cf53c219693 10541 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10542 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10543 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10544
hudakz 0:2cf53c219693 10545 /*********************** UART Instances : IRDA mode ***************************/
hudakz 0:2cf53c219693 10546 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10547 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10548 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10549
hudakz 0:2cf53c219693 10550 /***************** UART Instances : Multi-Processor mode **********************/
hudakz 0:2cf53c219693 10551 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10552 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10553 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10554
hudakz 0:2cf53c219693 10555 /***************** UART Instances : DMA mode available **********************/
hudakz 0:2cf53c219693 10556 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
hudakz 0:2cf53c219693 10557 ((INSTANCE) == USART2) || \
hudakz 0:2cf53c219693 10558 ((INSTANCE) == USART3))
hudakz 0:2cf53c219693 10559
hudakz 0:2cf53c219693 10560 /****************************** RTC Instances *********************************/
hudakz 0:2cf53c219693 10561 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
hudakz 0:2cf53c219693 10562
hudakz 0:2cf53c219693 10563 /**************************** WWDG Instances *****************************/
hudakz 0:2cf53c219693 10564 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
hudakz 0:2cf53c219693 10565
hudakz 0:2cf53c219693 10566 /****************************** USB Instances ********************************/
hudakz 0:2cf53c219693 10567 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
hudakz 0:2cf53c219693 10568
hudakz 0:2cf53c219693 10569
hudakz 0:2cf53c219693 10570
hudakz 0:2cf53c219693 10571 #define RCC_HSE_MIN 4000000U
hudakz 0:2cf53c219693 10572 #define RCC_HSE_MAX 16000000U
hudakz 0:2cf53c219693 10573
hudakz 0:2cf53c219693 10574 #define RCC_MAX_FREQUENCY 72000000U
hudakz 0:2cf53c219693 10575
hudakz 0:2cf53c219693 10576 /**
hudakz 0:2cf53c219693 10577 * @}
hudakz 0:2cf53c219693 10578 */
hudakz 0:2cf53c219693 10579 /******************************************************************************/
hudakz 0:2cf53c219693 10580 /* For a painless codes migration between the STM32F1xx device product */
hudakz 0:2cf53c219693 10581 /* lines, the aliases defined below are put in place to overcome the */
hudakz 0:2cf53c219693 10582 /* differences in the interrupt handlers and IRQn definitions. */
hudakz 0:2cf53c219693 10583 /* No need to update developed interrupt code when moving across */
hudakz 0:2cf53c219693 10584 /* product lines within the same STM32F1 Family */
hudakz 0:2cf53c219693 10585 /******************************************************************************/
hudakz 0:2cf53c219693 10586
hudakz 0:2cf53c219693 10587 /* Aliases for __IRQn */
hudakz 0:2cf53c219693 10588 #define ADC1_IRQn ADC1_2_IRQn
hudakz 0:2cf53c219693 10589 #define TIM9_IRQn TIM1_BRK_IRQn
hudakz 0:2cf53c219693 10590 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
hudakz 0:2cf53c219693 10591 #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
hudakz 0:2cf53c219693 10592 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
hudakz 0:2cf53c219693 10593 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
hudakz 0:2cf53c219693 10594 #define TIM11_IRQn TIM1_TRG_COM_IRQn
hudakz 0:2cf53c219693 10595 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
hudakz 0:2cf53c219693 10596 #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
hudakz 0:2cf53c219693 10597 #define TIM10_IRQn TIM1_UP_IRQn
hudakz 0:2cf53c219693 10598 #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
hudakz 0:2cf53c219693 10599 #define CEC_IRQn USBWakeUp_IRQn
hudakz 0:2cf53c219693 10600 #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
hudakz 0:2cf53c219693 10601 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
hudakz 0:2cf53c219693 10602 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
hudakz 0:2cf53c219693 10603 #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
hudakz 0:2cf53c219693 10604
hudakz 0:2cf53c219693 10605
hudakz 0:2cf53c219693 10606 /* Aliases for __IRQHandler */
hudakz 0:2cf53c219693 10607 #define ADC1_IRQHandler ADC1_2_IRQHandler
hudakz 0:2cf53c219693 10608 #define TIM9_IRQHandler TIM1_BRK_IRQHandler
hudakz 0:2cf53c219693 10609 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
hudakz 0:2cf53c219693 10610 #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
hudakz 0:2cf53c219693 10611 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
hudakz 0:2cf53c219693 10612 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
hudakz 0:2cf53c219693 10613 #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
hudakz 0:2cf53c219693 10614 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
hudakz 0:2cf53c219693 10615 #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
hudakz 0:2cf53c219693 10616 #define TIM10_IRQHandler TIM1_UP_IRQHandler
hudakz 0:2cf53c219693 10617 #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
hudakz 0:2cf53c219693 10618 #define CEC_IRQHandler USBWakeUp_IRQHandler
hudakz 0:2cf53c219693 10619 #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
hudakz 0:2cf53c219693 10620 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
hudakz 0:2cf53c219693 10621 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
hudakz 0:2cf53c219693 10622 #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
hudakz 0:2cf53c219693 10623
hudakz 0:2cf53c219693 10624
hudakz 0:2cf53c219693 10625 /**
hudakz 0:2cf53c219693 10626 * @}
hudakz 0:2cf53c219693 10627 */
hudakz 0:2cf53c219693 10628
hudakz 0:2cf53c219693 10629 /**
hudakz 0:2cf53c219693 10630 * @}
hudakz 0:2cf53c219693 10631 */
hudakz 0:2cf53c219693 10632
hudakz 0:2cf53c219693 10633
hudakz 0:2cf53c219693 10634 #ifdef __cplusplus
hudakz 0:2cf53c219693 10635 }
hudakz 0:2cf53c219693 10636 #endif /* __cplusplus */
hudakz 0:2cf53c219693 10637
hudakz 0:2cf53c219693 10638 #endif /* __STM32F103xB_H */
hudakz 0:2cf53c219693 10639
hudakz 0:2cf53c219693 10640
hudakz 0:2cf53c219693 10641
hudakz 0:2cf53c219693 10642 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/