Zoltan Hudak / Mbed OS Baremetal_EventQue_Bluepill

Bare-metal configuration with EventQueue for a Bluepill board.

Warning

It does not work with the Mbed Online Compiler.

Follow these steps to import and compile it with Mbed CLI:

mbed import https://os.mbed.com/users/hudakz/code/Baremetal_EventQue_Bluepill
mbed compile -t GCC_ARM -m bluepill

TARGET_BLUEPILL/device/system_clock.c@4:b57198581ca4, 2020-06-04 (annotated)

Committer:
hudakz
Date:
Thu Jun 04 21:49:34 2020 +0000
Revision:
4:b57198581ca4
Parent:
0:2cf53c219693 
Bare-metal with EventQueue on Bluepill.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
hudakz 0:2cf53c219693 1 /* mbed Microcontroller Library
hudakz 0:2cf53c219693 2 * Copyright (c) 2006-2017 ARM Limited
hudakz 0:2cf53c219693 3 *
hudakz 0:2cf53c219693 4 * Licensed under the Apache License, Version 2.0 (the "License");
hudakz 0:2cf53c219693 5 * you may not use this file except in compliance with the License.
hudakz 0:2cf53c219693 6 * You may obtain a copy of the License at
hudakz 0:2cf53c219693 7 *
hudakz 0:2cf53c219693 8 * http://www.apache.org/licenses/LICENSE-2.0
hudakz 0:2cf53c219693 9 *
hudakz 0:2cf53c219693 10 * Unless required by applicable law or agreed to in writing, software
hudakz 0:2cf53c219693 11 * distributed under the License is distributed on an "AS IS" BASIS,
hudakz 0:2cf53c219693 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
hudakz 0:2cf53c219693 13 * See the License for the specific language governing permissions and
hudakz 0:2cf53c219693 14 * limitations under the License.
hudakz 0:2cf53c219693 15 */
hudakz 0:2cf53c219693 16
hudakz 0:2cf53c219693 17 /**
hudakz 0:2cf53c219693 18 * This file configures the system clock as follows:
hudakz 0:2cf53c219693 19 *-----------------------------------------------------------------------------
hudakz 0:2cf53c219693 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
hudakz 0:2cf53c219693 21 * | (external 8 MHz clock) | (internal 8 MHz)
hudakz 0:2cf53c219693 22 * | 2- PLL_HSE_XTAL |
hudakz 0:2cf53c219693 23 * | (external 8 MHz xtal) |
hudakz 0:2cf53c219693 24 *-----------------------------------------------------------------------------
hudakz 0:2cf53c219693 25 * SYSCLK(MHz) | 72 | 64
hudakz 0:2cf53c219693 26 *-----------------------------------------------------------------------------
hudakz 0:2cf53c219693 27 * AHBCLK (MHz) | 72 | 64
hudakz 0:2cf53c219693 28 *-----------------------------------------------------------------------------
hudakz 0:2cf53c219693 29 * APB1CLK (MHz) | 36 | 32
hudakz 0:2cf53c219693 30 *-----------------------------------------------------------------------------
hudakz 0:2cf53c219693 31 * APB2CLK (MHz) | 72 | 64
hudakz 0:2cf53c219693 32 *-----------------------------------------------------------------------------
hudakz 0:2cf53c219693 33 * USB capable (48 MHz precise clock) | NO | NO
hudakz 0:2cf53c219693 34 *-----------------------------------------------------------------------------
hudakz 0:2cf53c219693 35 ******************************************************************************
hudakz 0:2cf53c219693 36 */
hudakz 0:2cf53c219693 37
hudakz 0:2cf53c219693 38 #include "stm32f1xx.h"
hudakz 0:2cf53c219693 39
hudakz 0:2cf53c219693 40 /*!< Uncomment the following line if you need to relocate your vector Table in
hudakz 0:2cf53c219693 41 Internal SRAM. */
hudakz 0:2cf53c219693 42 /* #define VECT_TAB_SRAM */
hudakz 0:2cf53c219693 43 #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
hudakz 0:2cf53c219693 44 This value must be a multiple of 0x200. */
hudakz 0:2cf53c219693 45
hudakz 0:2cf53c219693 46
hudakz 0:2cf53c219693 47 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
hudakz 0:2cf53c219693 48 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
hudakz 0:2cf53c219693 49 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
hudakz 0:2cf53c219693 50
hudakz 0:2cf53c219693 51
hudakz 0:2cf53c219693 52 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
hudakz 0:2cf53c219693 53 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
hudakz 0:2cf53c219693 54 #endif
hudakz 0:2cf53c219693 55
hudakz 0:2cf53c219693 56 uint8_t SetSysClock_PLL_HSI(void);
hudakz 0:2cf53c219693 57
hudakz 0:2cf53c219693 58
hudakz 0:2cf53c219693 59 /**
hudakz 0:2cf53c219693 60 * @brief Setup the microcontroller system
hudakz 0:2cf53c219693 61 * Initialize the Embedded Flash Interface, the PLL and update the
hudakz 0:2cf53c219693 62 * SystemCoreClock variable.
hudakz 0:2cf53c219693 63 * @note This function should be used only after reset.
hudakz 0:2cf53c219693 64 * @param None
hudakz 0:2cf53c219693 65 * @retval None
hudakz 0:2cf53c219693 66 */
hudakz 0:2cf53c219693 67 void SystemInit (void)
hudakz 0:2cf53c219693 68 {
hudakz 0:2cf53c219693 69 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
hudakz 0:2cf53c219693 70 /* Set HSION bit */
hudakz 0:2cf53c219693 71 RCC->CR |= 0x00000001U;
hudakz 0:2cf53c219693 72
hudakz 0:2cf53c219693 73 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
hudakz 0:2cf53c219693 74 #if !defined(STM32F105xC) && !defined(STM32F107xC)
hudakz 0:2cf53c219693 75 RCC->CFGR &= 0xF8FF0000U;
hudakz 0:2cf53c219693 76 #else
hudakz 0:2cf53c219693 77 RCC->CFGR &= 0xF0FF0000U;
hudakz 0:2cf53c219693 78 #endif /* STM32F105xC */
hudakz 0:2cf53c219693 79
hudakz 0:2cf53c219693 80 /* Reset HSEON, CSSON and PLLON bits */
hudakz 0:2cf53c219693 81 RCC->CR &= 0xFEF6FFFFU;
hudakz 0:2cf53c219693 82
hudakz 0:2cf53c219693 83 /* Reset HSEBYP bit */
hudakz 0:2cf53c219693 84 RCC->CR &= 0xFFFBFFFFU;
hudakz 0:2cf53c219693 85
hudakz 0:2cf53c219693 86 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
hudakz 0:2cf53c219693 87 RCC->CFGR &= 0xFF80FFFFU;
hudakz 0:2cf53c219693 88
hudakz 0:2cf53c219693 89 #if defined(STM32F105xC) || defined(STM32F107xC)
hudakz 0:2cf53c219693 90 /* Reset PLL2ON and PLL3ON bits */
hudakz 0:2cf53c219693 91 RCC->CR &= 0xEBFFFFFFU;
hudakz 0:2cf53c219693 92
hudakz 0:2cf53c219693 93 /* Disable all interrupts and clear pending bits */
hudakz 0:2cf53c219693 94 RCC->CIR = 0x00FF0000U;
hudakz 0:2cf53c219693 95
hudakz 0:2cf53c219693 96 /* Reset CFGR2 register */
hudakz 0:2cf53c219693 97 RCC->CFGR2 = 0x00000000U;
hudakz 0:2cf53c219693 98 #elif defined(STM32F100xB) || defined(STM32F100xE)
hudakz 0:2cf53c219693 99 /* Disable all interrupts and clear pending bits */
hudakz 0:2cf53c219693 100 RCC->CIR = 0x009F0000U;
hudakz 0:2cf53c219693 101
hudakz 0:2cf53c219693 102 /* Reset CFGR2 register */
hudakz 0:2cf53c219693 103 RCC->CFGR2 = 0x00000000U;
hudakz 0:2cf53c219693 104 #else
hudakz 0:2cf53c219693 105 /* Disable all interrupts and clear pending bits */
hudakz 0:2cf53c219693 106 RCC->CIR = 0x009F0000U;
hudakz 0:2cf53c219693 107 #endif /* STM32F105xC */
hudakz 0:2cf53c219693 108
hudakz 0:2cf53c219693 109 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
hudakz 0:2cf53c219693 110 #ifdef DATA_IN_ExtSRAM
hudakz 0:2cf53c219693 111 SystemInit_ExtMemCtl();
hudakz 0:2cf53c219693 112 #endif /* DATA_IN_ExtSRAM */
hudakz 0:2cf53c219693 113 #endif
hudakz 0:2cf53c219693 114
hudakz 0:2cf53c219693 115 #ifdef VECT_TAB_SRAM
hudakz 0:2cf53c219693 116 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
hudakz 0:2cf53c219693 117 #else
hudakz 0:2cf53c219693 118 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
hudakz 0:2cf53c219693 119 #endif
hudakz 0:2cf53c219693 120
hudakz 0:2cf53c219693 121 }
hudakz 0:2cf53c219693 122
hudakz 0:2cf53c219693 123 /**
hudakz 0:2cf53c219693 124 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
hudakz 0:2cf53c219693 125 * AHB/APBx prescalers and Flash settings
hudakz 0:2cf53c219693 126 * @note This function should be called only once the RCC clock configuration
hudakz 0:2cf53c219693 127 * is reset to the default reset state (done in SystemInit() function).
hudakz 0:2cf53c219693 128 * @param None
hudakz 0:2cf53c219693 129 * @retval None
hudakz 0:2cf53c219693 130 */
hudakz 0:2cf53c219693 131 void SetSysClock(void)
hudakz 0:2cf53c219693 132 {
hudakz 0:2cf53c219693 133 /* 1- Try to start with HSE and external clock */
hudakz 0:2cf53c219693 134 #if USE_PLL_HSE_EXTC != 0
hudakz 0:2cf53c219693 135 if (SetSysClock_PLL_HSE(1) == 0)
hudakz 0:2cf53c219693 136 #endif
hudakz 0:2cf53c219693 137 {
hudakz 0:2cf53c219693 138 /* 2- If fail try to start with HSE and external xtal */
hudakz 0:2cf53c219693 139 #if USE_PLL_HSE_XTAL != 0
hudakz 0:2cf53c219693 140 if (SetSysClock_PLL_HSE(0) == 0)
hudakz 0:2cf53c219693 141 #endif
hudakz 0:2cf53c219693 142 {
hudakz 0:2cf53c219693 143 /* 3- If fail start with HSI clock */
hudakz 0:2cf53c219693 144 if (SetSysClock_PLL_HSI() == 0) {
hudakz 0:2cf53c219693 145 while(1) {
hudakz 0:2cf53c219693 146 // [TODO] Put something here to tell the user that a problem occured...
hudakz 0:2cf53c219693 147 }
hudakz 0:2cf53c219693 148 }
hudakz 0:2cf53c219693 149 }
hudakz 0:2cf53c219693 150 }
hudakz 0:2cf53c219693 151
hudakz 0:2cf53c219693 152 /* Output clock on MCO1 pin(PA8) for debugging purpose */
hudakz 0:2cf53c219693 153 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz
hudakz 0:2cf53c219693 154 }
hudakz 0:2cf53c219693 155
hudakz 0:2cf53c219693 156 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
hudakz 0:2cf53c219693 157 /******************************************************************************/
hudakz 0:2cf53c219693 158 /* PLL (clocked by HSE) used as System clock source */
hudakz 0:2cf53c219693 159 /******************************************************************************/
hudakz 0:2cf53c219693 160 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
hudakz 0:2cf53c219693 161 {
hudakz 0:2cf53c219693 162 RCC_ClkInitTypeDef RCC_ClkInitStruct;
hudakz 0:2cf53c219693 163 RCC_OscInitTypeDef RCC_OscInitStruct;
hudakz 0:2cf53c219693 164
hudakz 0:2cf53c219693 165 /* Enable HSE oscillator and activate PLL with HSE as source */
hudakz 0:2cf53c219693 166 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
hudakz 0:2cf53c219693 167 if (bypass == 0) {
hudakz 0:2cf53c219693 168 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
hudakz 0:2cf53c219693 169 } else {
hudakz 0:2cf53c219693 170 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
hudakz 0:2cf53c219693 171 }
hudakz 0:2cf53c219693 172 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
hudakz 0:2cf53c219693 173 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
hudakz 0:2cf53c219693 174 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
hudakz 0:2cf53c219693 175 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
hudakz 0:2cf53c219693 176 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
hudakz 0:2cf53c219693 177 return 0; // FAIL
hudakz 0:2cf53c219693 178 }
hudakz 0:2cf53c219693 179
hudakz 0:2cf53c219693 180 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
hudakz 0:2cf53c219693 181 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
hudakz 0:2cf53c219693 182 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
hudakz 0:2cf53c219693 183 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
hudakz 0:2cf53c219693 184 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
hudakz 0:2cf53c219693 185 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
hudakz 0:2cf53c219693 186 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
hudakz 0:2cf53c219693 187 return 0; // FAIL
hudakz 0:2cf53c219693 188 }
hudakz 0:2cf53c219693 189
hudakz 0:2cf53c219693 190 /* Output clock on MCO1 pin(PA8) for debugging purpose */
hudakz 0:2cf53c219693 191 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
hudakz 0:2cf53c219693 192
hudakz 0:2cf53c219693 193 return 1; // OK
hudakz 0:2cf53c219693 194 }
hudakz 0:2cf53c219693 195 #endif
hudakz 0:2cf53c219693 196
hudakz 0:2cf53c219693 197 /******************************************************************************/
hudakz 0:2cf53c219693 198 /* PLL (clocked by HSI) used as System clock source */
hudakz 0:2cf53c219693 199 /******************************************************************************/
hudakz 0:2cf53c219693 200 uint8_t SetSysClock_PLL_HSI(void)
hudakz 0:2cf53c219693 201 {
hudakz 0:2cf53c219693 202 RCC_ClkInitTypeDef RCC_ClkInitStruct;
hudakz 0:2cf53c219693 203 RCC_OscInitTypeDef RCC_OscInitStruct;
hudakz 0:2cf53c219693 204
hudakz 0:2cf53c219693 205 /* Enable HSI oscillator and activate PLL with HSI as source */
hudakz 0:2cf53c219693 206 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
hudakz 0:2cf53c219693 207 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
hudakz 0:2cf53c219693 208 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
hudakz 0:2cf53c219693 209 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
hudakz 0:2cf53c219693 210 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
hudakz 0:2cf53c219693 211 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
hudakz 0:2cf53c219693 212 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
hudakz 0:2cf53c219693 213 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
hudakz 0:2cf53c219693 214 return 0; // FAIL
hudakz 0:2cf53c219693 215 }
hudakz 0:2cf53c219693 216
hudakz 0:2cf53c219693 217 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
hudakz 0:2cf53c219693 218 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
hudakz 0:2cf53c219693 219 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
hudakz 0:2cf53c219693 220 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
hudakz 0:2cf53c219693 221 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
hudakz 0:2cf53c219693 222 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
hudakz 0:2cf53c219693 223 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
hudakz 0:2cf53c219693 224 return 0; // FAIL
hudakz 0:2cf53c219693 225 }
hudakz 0:2cf53c219693 226
hudakz 0:2cf53c219693 227 /* Output clock on MCO1 pin(PA8) for debugging purpose */
hudakz 0:2cf53c219693 228 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
hudakz 0:2cf53c219693 229
hudakz 0:2cf53c219693 230 return 1; // OK
hudakz 0:2cf53c219693 231 }
hudakz 0:2cf53c219693 232