This is a non working version of my ethernet with sd card, i do not know why
Dependencies: SDFileSystem mbed
Fork of eth_v13 by
w5100.h
00001 /* 00002 * Copyright (c) 2010 by Cristian Maglie <c.maglie@bug.st> 00003 * 00004 * This file is free software; you can redistribute it and/or modify 00005 * it under the terms of either the GNU General Public License version 2 00006 * or the GNU Lesser General Public License version 2.1, both as 00007 * published by the Free Software Foundation. 00008 */ 00009 00010 #ifndef W5100_H_INCLUDED 00011 #define W5100_H_INCLUDED 00012 00013 #define MBED 00014 00015 #ifdef MBED 00016 #include "mbed.h" 00017 typedef unsigned char uint8_t; 00018 typedef unsigned short uint16_t; 00019 #else //MBED 00020 #include <avr/pgmspace.h> 00021 #include <SPI.h> 00022 #endif //MBED 00023 00024 #include "ipaddr.h" 00025 00026 //#define W5200 00027 00028 #ifdef W5200 00029 #define MAX_SOCK_NUM 8 00030 #else 00031 #define MAX_SOCK_NUM 4 00032 #endif 00033 00034 00035 typedef uint8_t SOCKET; 00036 00037 #ifndef W5200 00038 #define IDM_OR 0x8000 00039 #define IDM_AR0 0x8001 00040 #define IDM_AR1 0x8002 00041 #define IDM_DR 0x8003 00042 #endif 00043 00044 /* 00045 class MR { 00046 public: 00047 static const uint8_t RST = 0x80; 00048 static const uint8_t PB = 0x10; 00049 static const uint8_t PPPOE = 0x08; 00050 static const uint8_t LB = 0x04; 00051 static const uint8_t AI = 0x02; 00052 static const uint8_t IND = 0x01; 00053 }; 00054 */ 00055 /* 00056 class IR { 00057 public: 00058 static const uint8_t CONFLICT = 0x80; 00059 static const uint8_t UNREACH = 0x40; 00060 static const uint8_t PPPoE = 0x20; 00061 static const uint8_t SOCK0 = 0x01; 00062 static const uint8_t SOCK1 = 0x02; 00063 static const uint8_t SOCK2 = 0x04; 00064 static const uint8_t SOCK3 = 0x08; 00065 static inline uint8_t SOCK(SOCKET ch) { return (0x01 << ch); }; 00066 }; 00067 */ 00068 00069 00070 00071 00072 class SnMR 00073 { 00074 public: 00075 static const uint8_t CLOSE = 0x00; 00076 static const uint8_t TCP = 0x01; 00077 static const uint8_t UDP = 0x02; 00078 static const uint8_t IPRAW = 0x03; 00079 static const uint8_t MACRAW = 0x04; 00080 static const uint8_t PPPOE = 0x05; 00081 static const uint8_t ND = 0x20; 00082 static const uint8_t MULTI = 0x80; 00083 }; 00084 00085 enum SockCMD { 00086 Sock_OPEN = 0x01, 00087 Sock_LISTEN = 0x02, 00088 Sock_CONNECT = 0x04, 00089 Sock_DISCON = 0x08, 00090 Sock_CLOSE = 0x10, 00091 Sock_SEND = 0x20, 00092 Sock_SEND_MAC = 0x21, 00093 Sock_SEND_KEEP = 0x22, 00094 Sock_RECV = 0x40 00095 }; 00096 00097 /*class SnCmd { 00098 public: 00099 static const uint8_t OPEN = 0x01; 00100 static const uint8_t LISTEN = 0x02; 00101 static const uint8_t CONNECT = 0x04; 00102 static const uint8_t DISCON = 0x08; 00103 static const uint8_t CLOSE = 0x10; 00104 static const uint8_t SEND = 0x20; 00105 static const uint8_t SEND_MAC = 0x21; 00106 static const uint8_t SEND_KEEP = 0x22; 00107 static const uint8_t RECV = 0x40; 00108 }; 00109 */ 00110 00111 class SnIR 00112 { 00113 public: 00114 static const uint8_t SEND_OK = 0x10; 00115 static const uint8_t TIMEOUT = 0x08; 00116 static const uint8_t RECV = 0x04; 00117 static const uint8_t DISCON = 0x02; 00118 static const uint8_t CON = 0x01; 00119 }; 00120 00121 class SnSR 00122 { 00123 public: 00124 static const uint8_t CLOSED = 0x00; 00125 static const uint8_t INIT = 0x13; 00126 static const uint8_t LISTEN = 0x14; 00127 static const uint8_t SYNSENT = 0x15; 00128 static const uint8_t SYNRECV = 0x16; 00129 static const uint8_t ESTABLISHED = 0x17; 00130 static const uint8_t FIN_WAIT = 0x18; 00131 static const uint8_t CLOSING = 0x1A; 00132 static const uint8_t TIME_WAIT = 0x1B; 00133 static const uint8_t CLOSE_WAIT = 0x1C; 00134 static const uint8_t LAST_ACK = 0x1D; 00135 static const uint8_t UDP = 0x22; 00136 static const uint8_t IPRAW = 0x32; 00137 static const uint8_t MACRAW = 0x42; 00138 static const uint8_t PPPOE = 0x5F; 00139 }; 00140 00141 class IPPROTO 00142 { 00143 public: 00144 static const uint8_t IP = 0; 00145 static const uint8_t ICMP = 1; 00146 static const uint8_t IGMP = 2; 00147 static const uint8_t GGP = 3; 00148 static const uint8_t TCP = 6; 00149 static const uint8_t PUP = 12; 00150 static const uint8_t UDP = 17; 00151 static const uint8_t IDP = 22; 00152 static const uint8_t ND = 77; 00153 static const uint8_t RAW = 255; 00154 }; 00155 00156 class W5100Class 00157 { 00158 public: 00159 #ifdef MBED 00160 void hardware_reset(); 00161 #endif //MBED 00162 void init(); 00163 00164 /** 00165 * @brief This function is being used for copy the data form Receive buffer of the chip to application buffer. 00166 * 00167 * It calculate the actual physical address where one has to read 00168 * the data from Receive buffer. Here also take care of the condition while it exceed 00169 * the Rx memory uper-bound of socket. 00170 */ 00171 void read_data(SOCKET s, volatile uint8_t * src, volatile uint8_t * dst, uint16_t len); 00172 00173 /** 00174 * @brief This function is being called by send() and sendto() function also. 00175 * 00176 * This function read the Tx write pointer register and after copy the data in buffer update the Tx write pointer 00177 * register. User should read upper byte first and lower byte later to get proper value. 00178 */ 00179 void send_data_processing(SOCKET s, const uint8_t *data, uint16_t len); 00180 /** 00181 * @brief A copy of send_data_processing that uses the provided ptr for the 00182 * write offset. Only needed for the "streaming" UDP API, where 00183 * a single UDP packet is built up over a number of calls to 00184 * send_data_processing_ptr, because TX_WR doesn't seem to get updated 00185 * correctly in those scenarios 00186 * @param ptr value to use in place of TX_WR. If 0, then the value is read 00187 * in from TX_WR 00188 * @return New value for ptr, to be used in the next call 00189 */ 00190 // FIXME Update documentation 00191 void send_data_processing_offset(SOCKET s, uint16_t data_offset, const uint8_t *data, uint16_t len); 00192 00193 /** 00194 * @brief This function is being called by recv() also. 00195 * 00196 * This function read the Rx read pointer register 00197 * and after copy the data from receive buffer update the Rx write pointer register. 00198 * User should read upper byte first and lower byte later to get proper value. 00199 */ 00200 void recv_data_processing(SOCKET s, uint8_t *data, uint16_t len, uint8_t peek = 0); 00201 00202 inline void setGatewayIp(uint8_t *_addr); 00203 inline void getGatewayIp(uint8_t *_addr); 00204 00205 inline void setSubnetMask(uint8_t *_addr); 00206 inline void getSubnetMask(uint8_t *_addr); 00207 00208 inline void setMACAddress(uint8_t * addr); 00209 inline void getMACAddress(uint8_t * addr); 00210 00211 inline void setIPAddress(uint8_t * addr); 00212 inline void getIPAddress(uint8_t * addr); 00213 00214 inline void setRetransmissionTime(uint16_t timeout); 00215 inline void setRetransmissionCount(uint8_t _retry); 00216 00217 00218 void execCmdSn(SOCKET s, SockCMD _cmd); 00219 00220 uint16_t getTXFreeSize(SOCKET s); 00221 uint16_t getRXReceivedSize(SOCKET s); 00222 00223 00224 // W5100 Registers 00225 // --------------- 00226 private: 00227 static uint8_t write(uint16_t _addr, uint8_t _data); 00228 static uint16_t write(uint16_t addr, const uint8_t *buf, uint16_t len); 00229 static uint8_t read(uint16_t addr); 00230 static uint16_t read(uint16_t addr, uint8_t *buf, uint16_t len); 00231 00232 #define __GP_REGISTER8(name, address) \ 00233 static inline void write##name(uint8_t _data) { \ 00234 write(address, _data); \ 00235 } \ 00236 static inline uint8_t read##name() { \ 00237 return read(address); \ 00238 } 00239 #define __GP_REGISTER16(name, address) \ 00240 static void write##name(uint16_t _data) { \ 00241 write(address, _data >> 8); \ 00242 write(address+1, _data & 0xFF); \ 00243 } \ 00244 static uint16_t read##name() { \ 00245 uint16_t res = read(address); \ 00246 res = (res << 8) + read(address + 1); \ 00247 return res; \ 00248 } 00249 #define __GP_REGISTER_N(name, address, size) \ 00250 static uint16_t write##name(uint8_t *_buff) { \ 00251 return write(address, _buff, size); \ 00252 } \ 00253 static uint16_t read##name(uint8_t *_buff) { \ 00254 return read(address, _buff, size); \ 00255 } 00256 00257 public: 00258 __GP_REGISTER8 (MR, 0x0000); // Mode 00259 __GP_REGISTER_N(GAR, 0x0001, 4); // Gateway IP address 00260 __GP_REGISTER_N(SUBR, 0x0005, 4); // Subnet mask address 00261 __GP_REGISTER_N(SHAR, 0x0009, 6); // Source MAC address 00262 __GP_REGISTER_N(SIPR, 0x000F, 4); // Source IP address 00263 __GP_REGISTER8 (IR, 0x0015); // Interrupt 00264 __GP_REGISTER8 (IMR, 0x0016); // Interrupt Mask 00265 __GP_REGISTER16(RTR, 0x0017); // Timeout address 00266 __GP_REGISTER8 (RCR, 0x0019); // Retry count 00267 00268 #ifndef W5200 00269 __GP_REGISTER8 (RMSR, 0x001A); // Receive memory size 00270 __GP_REGISTER8 (TMSR, 0x001B); // Transmit memory size 00271 #endif 00272 __GP_REGISTER8 (PATR, 0x001C); // Authentication type address in PPPoE mode 00273 __GP_REGISTER8 (VERSIONR,0x001f); // Chip version 00274 __GP_REGISTER8 (PTIMER, 0x0028); // PPP LCP Request Timer 00275 __GP_REGISTER8 (PMAGIC, 0x0029); // PPP LCP Magic Number 00276 #ifndef W5200 00277 __GP_REGISTER_N(UIPR, 0x002A, 4); // Unreachable IP address in UDP mode 00278 __GP_REGISTER16(UPORT, 0x002E); // Unreachable Port address in UDP mode 00279 #endif 00280 __GP_REGISTER8 (PHYSTATUS,0x0035); // PHY Status 00281 00282 #undef __GP_REGISTER8 00283 #undef __GP_REGISTER16 00284 #undef __GP_REGISTER_N 00285 00286 // W5100 Socket registers 00287 // ---------------------- 00288 private: 00289 static inline uint8_t readSn(SOCKET _s, uint16_t _addr); 00290 static inline uint8_t writeSn(SOCKET _s, uint16_t _addr, uint8_t _data); 00291 static inline uint16_t readSn(SOCKET _s, uint16_t _addr, uint8_t *_buf, uint16_t len); 00292 static inline uint16_t writeSn(SOCKET _s, uint16_t _addr, uint8_t *_buf, uint16_t len); 00293 00294 #ifdef W5200 00295 static const uint16_t CH_BASE = 0x4000; 00296 #else 00297 static const uint16_t CH_BASE = 0x0400; 00298 #endif 00299 00300 static const uint16_t CH_SIZE = 0x0100; 00301 00302 #define __SOCKET_REGISTER8(name, address) \ 00303 static inline void write##name(SOCKET _s, uint8_t _data) { \ 00304 writeSn(_s, address, _data); \ 00305 } \ 00306 static inline uint8_t read##name(SOCKET _s) { \ 00307 return readSn(_s, address); \ 00308 } 00309 #define __SOCKET_REGISTER16(name, address) \ 00310 static void write##name(SOCKET _s, uint16_t _data) { \ 00311 writeSn(_s, address, _data >> 8); \ 00312 writeSn(_s, address+1, _data & 0xFF); \ 00313 } \ 00314 static uint16_t read##name(SOCKET _s) { \ 00315 uint16_t res = readSn(_s, address); \ 00316 res = (res << 8) + readSn(_s, address + 1); \ 00317 return res; \ 00318 } 00319 #define __SOCKET_REGISTER_N(name, address, size) \ 00320 static uint16_t write##name(SOCKET _s, uint8_t *_buff) { \ 00321 return writeSn(_s, address, _buff, size); \ 00322 } \ 00323 static uint16_t read##name(SOCKET _s, uint8_t *_buff) { \ 00324 return readSn(_s, address, _buff, size); \ 00325 } 00326 00327 public: 00328 __SOCKET_REGISTER8(SnMR, 0x0000) // Mode 00329 __SOCKET_REGISTER8(SnCR, 0x0001) // Command 00330 __SOCKET_REGISTER8(SnIR, 0x0002) // Interrupt 00331 __SOCKET_REGISTER8(SnSR, 0x0003) // Status 00332 __SOCKET_REGISTER16(SnPORT, 0x0004) // Source Port 00333 __SOCKET_REGISTER_N(SnDHAR, 0x0006, 6) // Destination Hardw Addr 00334 __SOCKET_REGISTER_N(SnDIPR, 0x000C, 4) // Destination IP Addr 00335 __SOCKET_REGISTER16(SnDPORT, 0x0010) // Destination Port 00336 __SOCKET_REGISTER16(SnMSSR, 0x0012) // Max Segment Size 00337 __SOCKET_REGISTER8(SnPROTO, 0x0014) // Protocol in IP RAW Mode 00338 __SOCKET_REGISTER8(SnTOS, 0x0015) // IP TOS 00339 __SOCKET_REGISTER8(SnTTL, 0x0016) // IP TTL 00340 __SOCKET_REGISTER16(SnTX_FSR, 0x0020) // TX Free Size 00341 __SOCKET_REGISTER16(SnTX_RD, 0x0022) // TX Read Pointer 00342 __SOCKET_REGISTER16(SnTX_WR, 0x0024) // TX Write Pointer 00343 __SOCKET_REGISTER16(SnRX_RSR, 0x0026) // RX Free Size 00344 __SOCKET_REGISTER16(SnRX_RD, 0x0028) // RX Read Pointer 00345 __SOCKET_REGISTER16(SnRX_WR, 0x002A) // RX Write Pointer (supported?) 00346 00347 #undef __SOCKET_REGISTER8 00348 #undef __SOCKET_REGISTER16 00349 #undef __SOCKET_REGISTER_N 00350 00351 00352 private: 00353 static const uint8_t RST = 7; // Reset BIT 00354 00355 #ifdef W5200 00356 static const int SOCKETS = 8; 00357 #else 00358 static const int SOCKETS = 4; 00359 #endif 00360 00361 static const uint16_t SMASK = 0x07FF; // Tx buffer MASK 00362 static const uint16_t RMASK = 0x07FF; // Rx buffer MASK 00363 public: 00364 static const uint16_t SSIZE = 2048; // Max Tx buffer size 00365 private: 00366 static const uint16_t RSIZE = 2048; // Max Rx buffer size 00367 uint16_t SBASE[SOCKETS]; // Tx buffer base address 00368 uint16_t RBASE[SOCKETS]; // Rx buffer base address 00369 00370 private: 00371 #if defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) 00372 inline static void initSS() { 00373 DDRB |= _BV(4); 00374 }; 00375 inline static void setSS() { 00376 PORTB &= ~_BV(4); 00377 }; 00378 inline static void resetSS() { 00379 PORTB |= _BV(4); 00380 }; 00381 #elif defined(__AVR_ATmega32U4__) || defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB162__) 00382 inline static void initSS() { 00383 DDRB |= _BV(0); 00384 }; 00385 inline static void setSS() { 00386 PORTB &= ~_BV(0); 00387 }; 00388 inline static void resetSS() { 00389 PORTB |= _BV(0); 00390 }; 00391 #else 00392 #ifndef MBED 00393 inline static void initSS() { 00394 DDRB |= _BV(2); 00395 }; 00396 inline static void setSS() { 00397 PORTB &= ~_BV(2); 00398 }; 00399 inline static void resetSS() { 00400 PORTB |= _BV(2); 00401 }; 00402 #endif //MBED 00403 #endif 00404 00405 }; 00406 00407 extern W5100Class W5100; 00408 00409 uint8_t W5100Class::readSn(SOCKET _s, uint16_t _addr) 00410 { 00411 return read(CH_BASE + _s * CH_SIZE + _addr); 00412 } 00413 00414 uint8_t W5100Class::writeSn(SOCKET _s, uint16_t _addr, uint8_t _data) 00415 { 00416 return write(CH_BASE + _s * CH_SIZE + _addr, _data); 00417 } 00418 00419 uint16_t W5100Class::readSn(SOCKET _s, uint16_t _addr, uint8_t *_buf, uint16_t _len) 00420 { 00421 return read(CH_BASE + _s * CH_SIZE + _addr, _buf, _len); 00422 } 00423 00424 uint16_t W5100Class::writeSn(SOCKET _s, uint16_t _addr, uint8_t *_buf, uint16_t _len) 00425 { 00426 return write(CH_BASE + _s * CH_SIZE + _addr, _buf, _len); 00427 } 00428 00429 void W5100Class::getGatewayIp(uint8_t *_addr) 00430 { 00431 readGAR(_addr); 00432 } 00433 00434 void W5100Class::setGatewayIp(uint8_t *_addr) 00435 { 00436 writeGAR(_addr); 00437 } 00438 00439 void W5100Class::getSubnetMask(uint8_t *_addr) 00440 { 00441 readSUBR(_addr); 00442 } 00443 00444 void W5100Class::setSubnetMask(uint8_t *_addr) 00445 { 00446 writeSUBR(_addr); 00447 } 00448 00449 void W5100Class::getMACAddress(uint8_t *_addr) 00450 { 00451 readSHAR(_addr); 00452 } 00453 00454 void W5100Class::setMACAddress(uint8_t *_addr) 00455 { 00456 writeSHAR(_addr); 00457 } 00458 00459 void W5100Class::getIPAddress(uint8_t *_addr) 00460 { 00461 readSIPR(_addr); 00462 } 00463 00464 void W5100Class::setIPAddress(uint8_t *_addr) 00465 { 00466 writeSIPR(_addr); 00467 } 00468 00469 void W5100Class::setRetransmissionTime(uint16_t _timeout) 00470 { 00471 writeRTR(_timeout); 00472 } 00473 00474 void W5100Class::setRetransmissionCount(uint8_t _retry) 00475 { 00476 writeRCR(_retry); 00477 } 00478 00479 #endif
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