max30003_app.cpp

00001 /*
00002  * max30003_app.c
00003  *
00004  *  Created on: Jun 20, 2018
00005  *      Author: Mahir.Ozturk
00006  */
00007 #include <mbed.h>
00008 #include "max30003_app.h"
00009 #include "MAX30003.h"
00010 
00011 #define MAX30003_IRQ_ASSERTED_SIGNAL_ID 1
00012 
00013 static Thread *thread = 0;
00014 
00015 /* ECG FIFO nearly full callback */
00016 void ecgFIFO_callback()  {
00017     if (thread != 0) {
00018         thread->signal_set(MAX30003_IRQ_ASSERTED_SIGNAL_ID);
00019     }
00020 }
00021 
00022 void ecg_config(MAX30003& ecgAFE)
00023 {
00024     // Reset ECG to clear registers
00025     ecgAFE.writeRegister( MAX30003::SW_RST , 0);
00026 
00027     // General config register setting
00028     MAX30003::GeneralConfiguration_u CNFG_GEN_r;
00029     CNFG_GEN_r.bits.en_ecg = 1;     // Enable ECG channel
00030     CNFG_GEN_r.bits.rbiasn = 1;     // Enable resistive bias on negative input
00031     CNFG_GEN_r.bits.rbiasp = 1;     // Enable resistive bias on positive input
00032     CNFG_GEN_r.bits.en_rbias = 1;   // Enable resistive bias
00033     CNFG_GEN_r.bits.imag = 2;       // Current magnitude = 10nA
00034     CNFG_GEN_r.bits.en_dcloff = 1;  // Enable DC lead-off detection
00035     ecgAFE.writeRegister( MAX30003::CNFG_GEN , CNFG_GEN_r.all);
00036 
00037 
00038     // ECG Config register setting
00039     MAX30003::ECGConfiguration_u CNFG_ECG_r;
00040     CNFG_ECG_r.bits.dlpf = 1;       // Digital LPF cutoff = 40Hz
00041     CNFG_ECG_r.bits.dhpf = 1;       // Digital HPF cutoff = 0.5Hz
00042     CNFG_ECG_r.bits.gain = 3;       // ECG gain = 160V/V
00043     CNFG_ECG_r.bits.rate = 2;       // Sample rate = 128 sps
00044     ecgAFE.writeRegister( MAX30003::CNFG_ECG , CNFG_ECG_r.all);
00045 
00046 
00047     //R-to-R configuration
00048     MAX30003::RtoR1Configuration_u CNFG_RTOR_r;
00049     CNFG_RTOR_r.bits.wndw = 0b0011;         // WNDW = 96ms
00050     CNFG_RTOR_r.bits.rgain = 0b1111;        // Auto-scale gain
00051     CNFG_RTOR_r.bits.pavg = 0b11;           // 16-average
00052     CNFG_RTOR_r.bits.ptsf = 0b0011;         // PTSF = 4/16
00053     CNFG_RTOR_r.bits.en_rtor = 1;           // Enable R-to-R detection
00054     ecgAFE.writeRegister( MAX30003::CNFG_RTOR1 , CNFG_RTOR_r.all);
00055 
00056 
00057     //Manage interrupts register setting
00058     MAX30003::ManageInterrupts_u MNG_INT_r;
00059     MNG_INT_r.bits.efit = 0b00011;          // Assert EINT w/ 4 unread samples
00060     MNG_INT_r.bits.clr_rrint = 0b01;        // Clear R-to-R on RTOR reg. read back
00061     ecgAFE.writeRegister( MAX30003::MNGR_INT , MNG_INT_r.all);
00062 
00063 
00064     //Enable interrupts register setting
00065     MAX30003::EnableInterrupts_u EN_INT_r;
00066     EN_INT_r.bits.en_eint = 1;              // Enable EINT interrupt
00067     EN_INT_r.bits.en_rrint = 1;             // Enable R-to-R interrupt
00068     EN_INT_r.bits.intb_type = 3;            // Open-drain NMOS with internal pullup
00069     ecgAFE.writeRegister( MAX30003::EN_INT , EN_INT_r.all);
00070 
00071 
00072     //Dyanmic modes config
00073     MAX30003::ManageDynamicModes_u MNG_DYN_r;
00074     MNG_DYN_r.bits.fast = 0;                // Fast recovery mode disabled
00075     ecgAFE.writeRegister( MAX30003::MNGR_DYN , MNG_DYN_r.all);
00076 
00077     // MUX Config
00078     MAX30003::MuxConfiguration_u CNFG_MUX_r;
00079     CNFG_MUX_r.bits.openn = 0;          // Connect ECGN to AFE channel
00080     CNFG_MUX_r.bits.openp = 0;          // Connect ECGP to AFE channel
00081     ecgAFE.writeRegister( MAX30003::CNFG_EMUX , CNFG_MUX_r.all);
00082 
00083     return;
00084 }
00085 
00086 void max30003_reader_task(struct max30003_reader_task_args *args)
00087 {
00088     // Constants
00089     const int EINT_STATUS = 1 << 23;
00090     const int RTOR_STATUS = 1 << 10;
00091     const int RTOR_REG_OFFSET = 10;
00092     const float RTOR_LSB_RES = 0.0078125f;
00093     const int FIFO_OVF = 0x7;
00094     const int FIFO_VALID_SAMPLE = 0x0;
00095     const int FIFO_FAST_SAMPLE = 0x1;
00096     const int ETAG_BITS = 0x7;
00097 
00098     uint32_t ecgFIFO, RtoR, readECGSamples, ETAG[32], status;
00099     float BPM;
00100     Timer bleNotifyTimer;
00101 
00102     thread = args->self;
00103 
00104     MAX30003 max30003(args->spiBus, args->spiCS);       /* MAX30003WING board */
00105 
00106     InterruptIn ecgFIFO_int(P5_4);          // Config P5_4 as int. in for the
00107     ecgFIFO_int.fall(&ecgFIFO_callback);    // ecg FIFO almost full interrupt
00108 
00109     ecg_config(max30003);                   // Config ECG
00110 
00111     max30003.writeRegister( MAX30003::SYNCH , 0);
00112 
00113     bleNotifyTimer.start();
00114     while (1) {
00115         // Read back ECG samples from the FIFO
00116         thread->signal_wait(MAX30003_IRQ_ASSERTED_SIGNAL_ID);
00117 
00118         while (1) {
00119             /* Read back ECG samples from the FIFO */
00120             status = max30003.readRegister( MAX30003::STATUS );      // Read the STATUS register
00121 
00122             if ((status & (RTOR_STATUS | EINT_STATUS)) == 0) {
00123                 break;
00124             }
00125 
00126             // Check if R-to-R interrupt asserted
00127             if ((status & RTOR_STATUS) == RTOR_STATUS) {
00128 
00129                 // printf("R-to-R Interrupt \r\n");
00130 
00131                 // Read RtoR register
00132                 RtoR = max30003.readRegister(MAX30003::RTOR) >>  RTOR_REG_OFFSET;
00133 
00134                 // Convert to BPM
00135                 BPM = 1.0f / ( RtoR * RTOR_LSB_RES / 60.0f );
00136 
00137                 if (bleNotifyTimer.read_ms() >= (args->notify_period_sec * 1000)) {
00138                     printf("BPM: %.2f\r\n", BPM);
00139                     bleGattAttrWrite(args->gatt, (uint8_t *)&BPM, sizeof(BPM));
00140                     bleNotifyTimer.reset();
00141                 }
00142             }
00143 
00144             // Check if EINT interrupt asserted
00145             if ((status & EINT_STATUS) == EINT_STATUS) {
00146                 readECGSamples = 0; // Reset sample counter
00147 
00148                 do {
00149                     ecgFIFO = max30003.readRegister( MAX30003::ECG_FIFO );  // Read FIFO
00150                     ETAG[readECGSamples] = ( ecgFIFO >> 3 ) & ETAG_BITS;    // Isolate ETAG
00151                     readECGSamples++;                                       // Increment sample counter
00152 
00153                 // Check that sample is not last sample in FIFO
00154                 } while (ETAG[readECGSamples-1] == FIFO_VALID_SAMPLE ||
00155                         ETAG[readECGSamples-1] == FIFO_FAST_SAMPLE);
00156 
00157                 // Check if FIFO has overflowed
00158                 if (ETAG[readECGSamples - 1] == FIFO_OVF){
00159                     max30003.writeRegister( MAX30003::FIFO_RST , 0); // Reset FIFO
00160                 }
00161             }
00162         }
00163     }
00164 }
00165 
00166