David Lowe / Mbed 2 deprecated Nucleo_BSP_IHM01A1

X-CUBE-SPN1-20150128 example source code for one motor compiled under mbed. Tested OK on Nucleo F401. l6474.cpp is modified from original with defines in l6474_target_config.h to select the original behaviour (motor de-energised when halted), or new mode to continue powering with a (reduced) current in the coils (braking/position hold capability). On F401 avoid using mbed's InterruptIn on pins 10-15 (any port). Beware of other conflicts! L0 & F0 are included but untested.

Dependencies:   mbed

IHM01A1/stm32l0xx_nucleo_ihm01a1.h@6:19c1b4a04c24, 2015-10-13 (annotated)

Committer:
gregeric
Date:
Tue Oct 13 10:46:01 2015 +0000
Revision:
6:19c1b4a04c24
Parent:
0:b9444a40a999 
Ensure bridge is disabled before resetting the L6474.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gregeric 0:b9444a40a999 1 /**
gregeric 0:b9444a40a999 2 ******************************************************************************
gregeric 0:b9444a40a999 3 * @file stm32l0xx_nucleo_ihm01a1.h
gregeric 0:b9444a40a999 4 * @author IPC Rennes
gregeric 0:b9444a40a999 5 * @version V1.5.0
gregeric 0:b9444a40a999 6 * @date November 12, 2014
gregeric 0:b9444a40a999 7 * @brief Header for BSP driver for x-nucleo-ihm01a1 Nucleo extension board
gregeric 0:b9444a40a999 8 * (based on L6474)
gregeric 0:b9444a40a999 9 ******************************************************************************
gregeric 0:b9444a40a999 10 * @attention
gregeric 0:b9444a40a999 11 *
gregeric 0:b9444a40a999 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
gregeric 0:b9444a40a999 13 *
gregeric 0:b9444a40a999 14 * Redistribution and use in source and binary forms, with or without modification,
gregeric 0:b9444a40a999 15 * are permitted provided that the following conditions are met:
gregeric 0:b9444a40a999 16 * 1. Redistributions of source code must retain the above copyright notice,
gregeric 0:b9444a40a999 17 * this list of conditions and the following disclaimer.
gregeric 0:b9444a40a999 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
gregeric 0:b9444a40a999 19 * this list of conditions and the following disclaimer in the documentation
gregeric 0:b9444a40a999 20 * and/or other materials provided with the distribution.
gregeric 0:b9444a40a999 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
gregeric 0:b9444a40a999 22 * may be used to endorse or promote products derived from this software
gregeric 0:b9444a40a999 23 * without specific prior written permission.
gregeric 0:b9444a40a999 24 *
gregeric 0:b9444a40a999 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gregeric 0:b9444a40a999 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gregeric 0:b9444a40a999 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
gregeric 0:b9444a40a999 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
gregeric 0:b9444a40a999 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
gregeric 0:b9444a40a999 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
gregeric 0:b9444a40a999 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
gregeric 0:b9444a40a999 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
gregeric 0:b9444a40a999 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
gregeric 0:b9444a40a999 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
gregeric 0:b9444a40a999 35 *
gregeric 0:b9444a40a999 36 ******************************************************************************
gregeric 0:b9444a40a999 37 */
gregeric 0:b9444a40a999 38
gregeric 0:b9444a40a999 39 /* Define to prevent recursive inclusion -------------------------------------*/
gregeric 0:b9444a40a999 40 #ifndef __STM32L0XX_NUCLEO_IHM01A1_H
gregeric 0:b9444a40a999 41 #define __STM32L0XX_NUCLEO_IHM01A1_H
gregeric 0:b9444a40a999 42
gregeric 0:b9444a40a999 43 #ifdef __cplusplus
gregeric 0:b9444a40a999 44 extern "C" {
gregeric 0:b9444a40a999 45 #endif
gregeric 0:b9444a40a999 46
gregeric 0:b9444a40a999 47 /* Includes ------------------------------------------------------------------*/
gregeric 0:b9444a40a999 48 //#include "stm32l0xx_nucleo.h"
gregeric 0:b9444a40a999 49
gregeric 0:b9444a40a999 50 /** @addtogroup BSP
gregeric 0:b9444a40a999 51 * @{
gregeric 0:b9444a40a999 52 */
gregeric 0:b9444a40a999 53
gregeric 0:b9444a40a999 54 /** @addtogroup STM32L0XX_NUCLEO_IHM01A1
gregeric 0:b9444a40a999 55 * @{
gregeric 0:b9444a40a999 56 */
gregeric 0:b9444a40a999 57
gregeric 0:b9444a40a999 58 /** @defgroup IHM01A1_Board_Private_Function_Prototypes
gregeric 0:b9444a40a999 59 * @{
gregeric 0:b9444a40a999 60 */
gregeric 0:b9444a40a999 61
gregeric 0:b9444a40a999 62 void BSP_MotorControlBoard_Delay(uint32_t delay); //Delay of the requested number of milliseconds
gregeric 0:b9444a40a999 63 void BSP_MotorControlBoard_DisableIrq(void); //Disable Irq
gregeric 0:b9444a40a999 64 void BSP_MotorControlBoard_EnableIrq(void); //Enable Irq
gregeric 0:b9444a40a999 65 void BSP_MotorControlBoard_GpioInit(uint8_t nbDevices); //Initialise GPIOs used for L6474s
gregeric 0:b9444a40a999 66 void BSP_MotorControlBoard_Pwm1SetFreq(uint16_t newFreq); //Set PWM1 frequency and start it
gregeric 0:b9444a40a999 67 void BSP_MotorControlBoard_Pwm2SetFreq(uint16_t newFreq); //Set PWM2 frequency and start it
gregeric 0:b9444a40a999 68 void BSP_MotorControlBoard_Pwm3SetFreq(uint16_t newFreq); //Set PWM3 frequency and start it
gregeric 0:b9444a40a999 69 void BSP_MotorControlBoard_PwmInit(uint8_t deviceId); //Init the PWM of the specified device
gregeric 0:b9444a40a999 70 void BSP_MotorControlBoard_PwmStop(uint8_t deviceId); //Stop the PWM of the specified device
gregeric 0:b9444a40a999 71 void BSP_MotorControlBoard_ReleaseReset(void); //Reset the L6474 reset pin
gregeric 0:b9444a40a999 72 void BSP_MotorControlBoard_Reset(void); //Set the L6474 reset pin
gregeric 0:b9444a40a999 73 void BSP_MotorControlBoard_SetDirectionGpio(uint8_t deviceId, uint8_t gpioState); //Set direction GPIO
gregeric 0:b9444a40a999 74 uint8_t BSP_MotorControlBoard_SpiInit(void); //Initialise the SPI used for L6474s
gregeric 0:b9444a40a999 75 uint8_t BSP_MotorControlBoard_SpiWriteBytes(uint8_t *pByteToTransmit, uint8_t *pReceivedByte, uint8_t nbDevices); //Write bytes to the L6474s via SPI
gregeric 0:b9444a40a999 76
gregeric 0:b9444a40a999 77
gregeric 0:b9444a40a999 78 /* Exported Constants --------------------------------------------------------*/
gregeric 0:b9444a40a999 79
gregeric 0:b9444a40a999 80 /** @defgroup IHM01A1_Exported_Constants
gregeric 0:b9444a40a999 81 * @{
gregeric 0:b9444a40a999 82 */
gregeric 0:b9444a40a999 83
gregeric 0:b9444a40a999 84 /******************************************************************************/
gregeric 0:b9444a40a999 85 /* USE_STM32L0XX_NUCLEO */
gregeric 0:b9444a40a999 86 /******************************************************************************/
gregeric 0:b9444a40a999 87
gregeric 0:b9444a40a999 88 /** @defgroup Constants_For_STM32L0XX_NUCLEO
gregeric 0:b9444a40a999 89 * @{
gregeric 0:b9444a40a999 90 */
gregeric 0:b9444a40a999 91 /// Interrupt line used for L6474 FLAG
gregeric 0:b9444a40a999 92 #define EXTI_MCU_LINE_IRQn (EXTI4_15_IRQn)
gregeric 0:b9444a40a999 93
gregeric 0:b9444a40a999 94 /// Timer used for PWM1
gregeric 0:b9444a40a999 95 #define BSP_MOTOR_CONTROL_BOARD_TIMER_PWM1 (TIM22)
gregeric 0:b9444a40a999 96
gregeric 0:b9444a40a999 97 /// Timer used for PWM2
gregeric 0:b9444a40a999 98 #define BSP_MOTOR_CONTROL_BOARD_TIMER_PWM2 (TIM2)
gregeric 0:b9444a40a999 99
gregeric 0:b9444a40a999 100 /// Timer used for PWM3
gregeric 0:b9444a40a999 101 #define BSP_MOTOR_CONTROL_BOARD_TIMER_PWM3 (TIM21)
gregeric 0:b9444a40a999 102
gregeric 0:b9444a40a999 103 /// Channel Timer used for PWM1
gregeric 0:b9444a40a999 104 #define BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_PWM1 (TIM_CHANNEL_2)
gregeric 0:b9444a40a999 105
gregeric 0:b9444a40a999 106 /// Channel Timer used for PWM2
gregeric 0:b9444a40a999 107 #define BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_PWM2 (TIM_CHANNEL_2)
gregeric 0:b9444a40a999 108
gregeric 0:b9444a40a999 109 /// Channel Timer used for PWM3
gregeric 0:b9444a40a999 110 #define BSP_MOTOR_CONTROL_BOARD_CHAN_TIMER_PWM3 (TIM_CHANNEL_1)
gregeric 0:b9444a40a999 111
gregeric 0:b9444a40a999 112 /// HAL Active Channel Timer used for PWM1
gregeric 0:b9444a40a999 113 #define BSP_MOTOR_CONTROL_BOARD_HAL_ACT_CHAN_TIMER_PWM1 (HAL_TIM_ACTIVE_CHANNEL_2)
gregeric 0:b9444a40a999 114
gregeric 0:b9444a40a999 115 /// HAL Active Channel Timer used for PWM2
gregeric 0:b9444a40a999 116 #define BSP_MOTOR_CONTROL_BOARD_HAL_ACT_CHAN_TIMER_PWM2 (HAL_TIM_ACTIVE_CHANNEL_2)
gregeric 0:b9444a40a999 117
gregeric 0:b9444a40a999 118 /// HAL Active Channel Timer used for PWM3
gregeric 0:b9444a40a999 119 #define BSP_MOTOR_CONTROL_BOARD_HAL_ACT_CHAN_TIMER_PWM3 (HAL_TIM_ACTIVE_CHANNEL_1)
gregeric 0:b9444a40a999 120
gregeric 0:b9444a40a999 121 /// Timer Clock Enable for PWM1
gregeric 0:b9444a40a999 122 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM1_CLCK_ENABLE() __TIM22_CLK_ENABLE()
gregeric 0:b9444a40a999 123
gregeric 0:b9444a40a999 124 /// Timer Clock Enable for PWM2
gregeric 0:b9444a40a999 125 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM2_CLCK_ENABLE() __TIM2_CLK_ENABLE()
gregeric 0:b9444a40a999 126
gregeric 0:b9444a40a999 127 /// Timer Clock Enable for PWM1
gregeric 0:b9444a40a999 128 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM3_CLCK_ENABLE() __TIM21_CLK_ENABLE()
gregeric 0:b9444a40a999 129
gregeric 0:b9444a40a999 130 /// Timer Clock Disable for PWM1
gregeric 0:b9444a40a999 131 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM1_CLCK_DISABLE() __TIM22_CLK_DISABLE()
gregeric 0:b9444a40a999 132
gregeric 0:b9444a40a999 133 /// Timer Clock Disable for PWM2
gregeric 0:b9444a40a999 134 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM2_CLCK_DISABLE() __TIM2_CLK_DISABLE()
gregeric 0:b9444a40a999 135
gregeric 0:b9444a40a999 136 /// Timer Clock Disable for PWM3
gregeric 0:b9444a40a999 137 #define __BSP_MOTOR_CONTROL_BOARD_TIMER_PWM3_CLCK_DISABLE() __TIM21_CLK_DISABLE()
gregeric 0:b9444a40a999 138
gregeric 0:b9444a40a999 139 /// PWM1 global interrupt
gregeric 0:b9444a40a999 140 #define BSP_MOTOR_CONTROL_BOARD_PWM1_IRQn (TIM22_IRQn)
gregeric 0:b9444a40a999 141
gregeric 0:b9444a40a999 142 /// PWM2 global interrupt
gregeric 0:b9444a40a999 143 #define BSP_MOTOR_CONTROL_BOARD_PWM2_IRQn (TIM2_IRQn)
gregeric 0:b9444a40a999 144
gregeric 0:b9444a40a999 145 /// PWM3 global interrupt
gregeric 0:b9444a40a999 146 #define BSP_MOTOR_CONTROL_BOARD_PWM3_IRQn (TIM21_IRQn)
gregeric 0:b9444a40a999 147
gregeric 0:b9444a40a999 148 /// PWM1 GPIO alternate function
gregeric 0:b9444a40a999 149 #define BSP_MOTOR_CONTROL_BOARD_AFx_TIMx_PWM1 (GPIO_AF0_TIM22)
gregeric 0:b9444a40a999 150
gregeric 0:b9444a40a999 151 /// PWM2 GPIO alternate function
gregeric 0:b9444a40a999 152 #define BSP_MOTOR_CONTROL_BOARD_AFx_TIMx_PWM2 (GPIO_AF2_TIM2)
gregeric 0:b9444a40a999 153
gregeric 0:b9444a40a999 154 #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2
gregeric 0:b9444a40a999 155 /// SPI SCK AF
gregeric 0:b9444a40a999 156 #define SPIx_SCK_AF (GPIO_AF0_SPI1)
gregeric 0:b9444a40a999 157 #else /* #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2 */
gregeric 0:b9444a40a999 158 /// SPI SCK AF
gregeric 0:b9444a40a999 159 #define SPIx_SCK_AF (GPIO_AF0_SPI2)
gregeric 0:b9444a40a999 160 #endif /* #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2 */
gregeric 0:b9444a40a999 161
gregeric 0:b9444a40a999 162 /// PWM1 frequency rescaler (1 for HW PWM, 2 for SW PWM)
gregeric 0:b9444a40a999 163 #define BSP_MOTOR_CONTROL_BOARD_PWM1_FREQ_RESCALER (1)
gregeric 0:b9444a40a999 164 /// PWM2 frequency rescaler (1 for HW PWM, 2 for SW PWM)
gregeric 0:b9444a40a999 165 #define BSP_MOTOR_CONTROL_BOARD_PWM2_FREQ_RESCALER (1)
gregeric 0:b9444a40a999 166 /// PWM3 frequency rescaler (1 for HW PWM, 2 for SW PWM)
gregeric 0:b9444a40a999 167 #define BSP_MOTOR_CONTROL_BOARD_PWM3_FREQ_RESCALER (2)
gregeric 0:b9444a40a999 168
gregeric 0:b9444a40a999 169 /**
gregeric 0:b9444a40a999 170 * @}
gregeric 0:b9444a40a999 171 */
gregeric 0:b9444a40a999 172
gregeric 0:b9444a40a999 173 /******************************************************************************/
gregeric 0:b9444a40a999 174 /* Independent plateform definitions */
gregeric 0:b9444a40a999 175 /******************************************************************************/
gregeric 0:b9444a40a999 176
gregeric 0:b9444a40a999 177 /** @defgroup Constants_For_All_Nucleo_Platforms
gregeric 0:b9444a40a999 178 * @{
gregeric 0:b9444a40a999 179 */
gregeric 0:b9444a40a999 180
gregeric 0:b9444a40a999 181 /// GPIO Pin used for the L6474 flag pin
gregeric 0:b9444a40a999 182 #define BSP_MOTOR_CONTROL_BOARD_FLAG_PIN (GPIO_PIN_10)
gregeric 0:b9444a40a999 183 /// GPIO port used for the L6474 flag pin
gregeric 0:b9444a40a999 184 #define BSP_MOTOR_CONTROL_BOARD_FLAG_PORT (GPIOA)
gregeric 0:b9444a40a999 185
gregeric 0:b9444a40a999 186 /// GPIO Pin used for the L6474 step clock pin of device 0
gregeric 0:b9444a40a999 187 #define BSP_MOTOR_CONTROL_BOARD_PWM_1_PIN (GPIO_PIN_7)
gregeric 0:b9444a40a999 188 /// GPIO Port used for the L6474 step clock pin of device 0
gregeric 0:b9444a40a999 189 #define BSP_MOTOR_CONTROL_BOARD_PWM_1_PORT (GPIOC)
gregeric 0:b9444a40a999 190
gregeric 0:b9444a40a999 191 /// GPIO Pin used for the L6474 step clock pin of device 1
gregeric 0:b9444a40a999 192 #define BSP_MOTOR_CONTROL_BOARD_PWM_2_PIN (GPIO_PIN_3)
gregeric 0:b9444a40a999 193 /// GPIO port used for the L6474 step clock pin of device 1
gregeric 0:b9444a40a999 194 #define BSP_MOTOR_CONTROL_BOARD_PWM_2_PORT (GPIOB)
gregeric 0:b9444a40a999 195
gregeric 0:b9444a40a999 196 /// GPIO Pin used for the L6474 step clock pin of device 2
gregeric 0:b9444a40a999 197 #define BSP_MOTOR_CONTROL_BOARD_PWM_3_PIN (GPIO_PIN_10)
gregeric 0:b9444a40a999 198 /// GPIO port used for the L6474 step clock pin of device 2
gregeric 0:b9444a40a999 199 #define BSP_MOTOR_CONTROL_BOARD_PWM_3_PORT (GPIOB)
gregeric 0:b9444a40a999 200
gregeric 0:b9444a40a999 201 /// GPIO Pin used for the L6474 direction pin of device 0
gregeric 0:b9444a40a999 202 #define BSP_MOTOR_CONTROL_BOARD_DIR_1_PIN (GPIO_PIN_8)
gregeric 0:b9444a40a999 203 /// GPIO port used for the L6474 direction pin of device 0
gregeric 0:b9444a40a999 204 #define BSP_MOTOR_CONTROL_BOARD_DIR_1_PORT (GPIOA)
gregeric 0:b9444a40a999 205
gregeric 0:b9444a40a999 206 /// GPIO Pin used for the L6474 direction pin of device 1
gregeric 0:b9444a40a999 207 #define BSP_MOTOR_CONTROL_BOARD_DIR_2_PIN (GPIO_PIN_5)
gregeric 0:b9444a40a999 208 /// GPIO port used for the L6474 direction pin of device 1
gregeric 0:b9444a40a999 209 #define BSP_MOTOR_CONTROL_BOARD_DIR_2_PORT (GPIOB)
gregeric 0:b9444a40a999 210
gregeric 0:b9444a40a999 211 /// GPIO Pin used for the L6474 direction pin of device 2
gregeric 0:b9444a40a999 212 #define BSP_MOTOR_CONTROL_BOARD_DIR_3_PIN (GPIO_PIN_4)
gregeric 0:b9444a40a999 213 /// GPIO port used for the L6474 direction pin of device 2
gregeric 0:b9444a40a999 214 #define BSP_MOTOR_CONTROL_BOARD_DIR_3_PORT (GPIOB)
gregeric 0:b9444a40a999 215
gregeric 0:b9444a40a999 216 /// GPIO Pin used for the L6474 reset pin
gregeric 0:b9444a40a999 217 #define BSP_MOTOR_CONTROL_BOARD_RESET_PIN (GPIO_PIN_9)
gregeric 0:b9444a40a999 218 /// GPIO port used for the L6474 reset pin
gregeric 0:b9444a40a999 219 #define BSP_MOTOR_CONTROL_BOARD_RESET_PORT (GPIOA)
gregeric 0:b9444a40a999 220
gregeric 0:b9444a40a999 221 /// GPIO Pin used for the L6474 SPI chip select pin
gregeric 0:b9444a40a999 222 #define BSP_MOTOR_CONTROL_BOARD_CS_PIN (GPIO_PIN_6)
gregeric 0:b9444a40a999 223 /// GPIO port used for the L6474 SPI chip select pin
gregeric 0:b9444a40a999 224 #define BSP_MOTOR_CONTROL_BOARD_CS_PORT (GPIOB)
gregeric 0:b9444a40a999 225
gregeric 0:b9444a40a999 226 /* Definition for SPIx clock resources */
gregeric 0:b9444a40a999 227
gregeric 0:b9444a40a999 228 #ifndef BSP_MOTOR_CONTROL_BOARD_USE_SPI2
gregeric 0:b9444a40a999 229 /* Default SPI is SPI1 */
gregeric 0:b9444a40a999 230
gregeric 0:b9444a40a999 231 /// Used SPI
gregeric 0:b9444a40a999 232 #define SPIx (SPI1)
gregeric 0:b9444a40a999 233
gregeric 0:b9444a40a999 234 /// SPI clock enable
gregeric 0:b9444a40a999 235 #define SPIx_CLK_ENABLE() __SPI1_CLK_ENABLE()
gregeric 0:b9444a40a999 236
gregeric 0:b9444a40a999 237 /// SPI SCK enable
gregeric 0:b9444a40a999 238 #define SPIx_SCK_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
gregeric 0:b9444a40a999 239
gregeric 0:b9444a40a999 240 /// SPI MISO enable
gregeric 0:b9444a40a999 241 #define SPIx_MISO_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
gregeric 0:b9444a40a999 242
gregeric 0:b9444a40a999 243 /// SPI MOSI enable
gregeric 0:b9444a40a999 244 #define SPIx_MOSI_GPIO_CLK_ENABLE() __GPIOA_CLK_ENABLE()
gregeric 0:b9444a40a999 245
gregeric 0:b9444a40a999 246 /// SPI Force reset
gregeric 0:b9444a40a999 247 #define SPIx_FORCE_RESET() __SPI1_FORCE_RESET()
gregeric 0:b9444a40a999 248
gregeric 0:b9444a40a999 249 /// SPI Release reset
gregeric 0:b9444a40a999 250 #define SPIx_RELEASE_RESET() __SPI1_RELEASE_RESET()
gregeric 0:b9444a40a999 251
gregeric 0:b9444a40a999 252 /// SPI SCK pin
gregeric 0:b9444a40a999 253 #define SPIx_SCK_PIN (GPIO_PIN_5)
gregeric 0:b9444a40a999 254
gregeric 0:b9444a40a999 255 /// SPI SCK port
gregeric 0:b9444a40a999 256 #define SPIx_SCK_GPIO_PORT (GPIOA)
gregeric 0:b9444a40a999 257
gregeric 0:b9444a40a999 258
gregeric 0:b9444a40a999 259 /// SPI MISO pin
gregeric 0:b9444a40a999 260 #define SPIx_MISO_PIN (GPIO_PIN_6)
gregeric 0:b9444a40a999 261
gregeric 0:b9444a40a999 262 /// SPI MISO port
gregeric 0:b9444a40a999 263 #define SPIx_MISO_GPIO_PORT (GPIOA)
gregeric 0:b9444a40a999 264
gregeric 0:b9444a40a999 265 /// SPI MOSI pin
gregeric 0:b9444a40a999 266 #define SPIx_MOSI_PIN (GPIO_PIN_7)
gregeric 0:b9444a40a999 267
gregeric 0:b9444a40a999 268 /// SPI MOSI port
gregeric 0:b9444a40a999 269 #define SPIx_MOSI_GPIO_PORT (GPIOA)
gregeric 0:b9444a40a999 270
gregeric 0:b9444a40a999 271 #else /* USE SPI2 */
gregeric 0:b9444a40a999 272
gregeric 0:b9444a40a999 273 /// Used SPI
gregeric 0:b9444a40a999 274 #define SPIx (SPI2)
gregeric 0:b9444a40a999 275
gregeric 0:b9444a40a999 276 /// SPI clock enable
gregeric 0:b9444a40a999 277 #define SPIx_CLK_ENABLE() __SPI2_CLK_ENABLE()
gregeric 0:b9444a40a999 278
gregeric 0:b9444a40a999 279 /// SPI SCK enable
gregeric 0:b9444a40a999 280 #define SPIx_SCK_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE()
gregeric 0:b9444a40a999 281
gregeric 0:b9444a40a999 282 /// SPI MISO enable
gregeric 0:b9444a40a999 283 #define SPIx_MISO_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE()
gregeric 0:b9444a40a999 284
gregeric 0:b9444a40a999 285 /// SPI MOSI enable
gregeric 0:b9444a40a999 286 #define SPIx_MOSI_GPIO_CLK_ENABLE() __GPIOB_CLK_ENABLE()
gregeric 0:b9444a40a999 287
gregeric 0:b9444a40a999 288 /// SPI Force reset
gregeric 0:b9444a40a999 289 #define SPIx_FORCE_RESET() __SPI2_FORCE_RESET()
gregeric 0:b9444a40a999 290
gregeric 0:b9444a40a999 291 /// SPI Release reset
gregeric 0:b9444a40a999 292 #define SPIx_RELEASE_RESET() __SPI2_RELEASE_RESET()
gregeric 0:b9444a40a999 293
gregeric 0:b9444a40a999 294 /// SPI SCK pin
gregeric 0:b9444a40a999 295 #define SPIx_SCK_PIN (GPIO_PIN_13)
gregeric 0:b9444a40a999 296
gregeric 0:b9444a40a999 297 /// SPI SCK port
gregeric 0:b9444a40a999 298 #define SPIx_SCK_GPIO_PORT (GPIOB)
gregeric 0:b9444a40a999 299
gregeric 0:b9444a40a999 300 /// SPI MISO pin
gregeric 0:b9444a40a999 301 #define SPIx_MISO_PIN (GPIO_PIN_14)
gregeric 0:b9444a40a999 302
gregeric 0:b9444a40a999 303 /// SPI MISO port
gregeric 0:b9444a40a999 304 #define SPIx_MISO_GPIO_PORT (GPIOB)
gregeric 0:b9444a40a999 305
gregeric 0:b9444a40a999 306 /// SPI MISO AF
gregeric 0:b9444a40a999 307 #define SPIx_MISO_AF (SPIx_SCK_AF)
gregeric 0:b9444a40a999 308
gregeric 0:b9444a40a999 309 /// SPI MOSI pin
gregeric 0:b9444a40a999 310 #define SPIx_MOSI_PIN (GPIO_PIN_15)
gregeric 0:b9444a40a999 311
gregeric 0:b9444a40a999 312 /// SPI MOSI port
gregeric 0:b9444a40a999 313 #define SPIx_MOSI_GPIO_PORT (GPIOB)
gregeric 0:b9444a40a999 314
gregeric 0:b9444a40a999 315 #endif
gregeric 0:b9444a40a999 316
gregeric 0:b9444a40a999 317 /// SPI MISO AF
gregeric 0:b9444a40a999 318 #define SPIx_MISO_AF (SPIx_SCK_AF)
gregeric 0:b9444a40a999 319
gregeric 0:b9444a40a999 320 /// SPI MOSI AF
gregeric 0:b9444a40a999 321 #define SPIx_MOSI_AF (SPIx_SCK_AF)
gregeric 0:b9444a40a999 322
gregeric 0:b9444a40a999 323 /**
gregeric 0:b9444a40a999 324 * @}
gregeric 0:b9444a40a999 325 */
gregeric 0:b9444a40a999 326
gregeric 0:b9444a40a999 327 /**
gregeric 0:b9444a40a999 328 * @}
gregeric 0:b9444a40a999 329 */
gregeric 0:b9444a40a999 330
gregeric 0:b9444a40a999 331 #ifdef __cplusplus
gregeric 0:b9444a40a999 332 }
gregeric 0:b9444a40a999 333 #endif
gregeric 0:b9444a40a999 334
gregeric 0:b9444a40a999 335 #endif /* __STM32L0XX_NUCLEO_IHM01A1_H */
gregeric 0:b9444a40a999 336
gregeric 0:b9444a40a999 337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/