David Lowe / Mbed 2 deprecated Nucleo_BSP_IHM01A1

X-CUBE-SPN1-20150128 example source code for one motor compiled under mbed. Tested OK on Nucleo F401. l6474.cpp is modified from original with defines in l6474_target_config.h to select the original behaviour (motor de-energised when halted), or new mode to continue powering with a (reduced) current in the coils (braking/position hold capability). On F401 avoid using mbed's InterruptIn on pins 10-15 (any port). Beware of other conflicts! L0 & F0 are included but untested.

Dependencies:   mbed

IHM01A1/l6474_target_config.h@6:19c1b4a04c24, 2015-10-13 (annotated)

Committer:
gregeric
Date:
Tue Oct 13 10:46:01 2015 +0000
Revision:
6:19c1b4a04c24
Parent:
0:b9444a40a999 
Ensure bridge is disabled before resetting the L6474.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
gregeric 0:b9444a40a999 1 /**************************************************************************//**
gregeric 0:b9444a40a999 2 * @file l6474_target_config.h
gregeric 0:b9444a40a999 3 * @author IPC Rennes
gregeric 0:b9444a40a999 4 * @version V1.5.0
gregeric 0:b9444a40a999 5 * @date November 12, 2014
gregeric 0:b9444a40a999 6 * @brief Predefines values for the L6474 registers
gregeric 0:b9444a40a999 7 * and for the devices parameters
gregeric 0:b9444a40a999 8 * @note (C) COPYRIGHT 2014 STMicroelectronics
gregeric 0:b9444a40a999 9 ******************************************************************************
gregeric 0:b9444a40a999 10 * @attention
gregeric 0:b9444a40a999 11 *
gregeric 0:b9444a40a999 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
gregeric 0:b9444a40a999 13 *
gregeric 0:b9444a40a999 14 * Redistribution and use in source and binary forms, with or without modification,
gregeric 0:b9444a40a999 15 * are permitted provided that the following conditions are met:
gregeric 0:b9444a40a999 16 * 1. Redistributions of source code must retain the above copyright notice,
gregeric 0:b9444a40a999 17 * this list of conditions and the following disclaimer.
gregeric 0:b9444a40a999 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
gregeric 0:b9444a40a999 19 * this list of conditions and the following disclaimer in the documentation
gregeric 0:b9444a40a999 20 * and/or other materials provided with the distribution.
gregeric 0:b9444a40a999 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
gregeric 0:b9444a40a999 22 * may be used to endorse or promote products derived from this software
gregeric 0:b9444a40a999 23 * without specific prior written permission.
gregeric 0:b9444a40a999 24 *
gregeric 0:b9444a40a999 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
gregeric 0:b9444a40a999 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
gregeric 0:b9444a40a999 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
gregeric 0:b9444a40a999 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
gregeric 0:b9444a40a999 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
gregeric 0:b9444a40a999 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
gregeric 0:b9444a40a999 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
gregeric 0:b9444a40a999 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
gregeric 0:b9444a40a999 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
gregeric 0:b9444a40a999 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
gregeric 0:b9444a40a999 35 *
gregeric 0:b9444a40a999 36 ******************************************************************************
gregeric 0:b9444a40a999 37 */
gregeric 0:b9444a40a999 38
gregeric 0:b9444a40a999 39 /* Define to prevent recursive inclusion -------------------------------------*/
gregeric 0:b9444a40a999 40 #ifndef __L6474_TARGET_CONFIG_H
gregeric 0:b9444a40a999 41 #define __L6474_TARGET_CONFIG_H
gregeric 0:b9444a40a999 42
gregeric 0:b9444a40a999 43 #ifdef __cplusplus
gregeric 0:b9444a40a999 44 extern "C" {
gregeric 0:b9444a40a999 45 #endif
gregeric 0:b9444a40a999 46
gregeric 0:b9444a40a999 47 /** @addtogroup BSP
gregeric 0:b9444a40a999 48 * @{
gregeric 0:b9444a40a999 49 */
gregeric 0:b9444a40a999 50
gregeric 0:b9444a40a999 51 /** @addtogroup L6474
gregeric 0:b9444a40a999 52 * @{
gregeric 0:b9444a40a999 53 */
gregeric 0:b9444a40a999 54
gregeric 0:b9444a40a999 55 /** @addtogroup L6474_Exported_Constants
gregeric 0:b9444a40a999 56 * @{
gregeric 0:b9444a40a999 57 */
gregeric 0:b9444a40a999 58
gregeric 0:b9444a40a999 59 /** @defgroup Predefined_L6474_Registers_Values
gregeric 0:b9444a40a999 60 * @{
gregeric 0:b9444a40a999 61 */
gregeric 0:b9444a40a999 62
gregeric 0:b9444a40a999 63
gregeric 0:b9444a40a999 64 /// The maximum number of devices in the daisy chain
gregeric 0:b9444a40a999 65 #define MAX_NUMBER_OF_DEVICES (3)
gregeric 0:b9444a40a999 66
gregeric 0:b9444a40a999 67 /************** Motor Energised When Halted or Not ********************/
gregeric 0:b9444a40a999 68
gregeric 0:b9444a40a999 69 /// Switch behaviour: motors de-energised when halted, or energised/braked.
gregeric 0:b9444a40a999 70 #define L6474_CONF_BRAKE_WHEN_HALTED
gregeric 0:b9444a40a999 71 /// Reduced motor current, eg half power when halted.
gregeric 0:b9444a40a999 72 #define L6474_CONF_BRAKE_CURRENT_FACTOR (2)
gregeric 0:b9444a40a999 73
gregeric 0:b9444a40a999 74 /************************ Speed Profile *******************************/
gregeric 0:b9444a40a999 75
gregeric 0:b9444a40a999 76 /// Acceleration rate in step/s2 for device 0 (must be greater than 0)
gregeric 0:b9444a40a999 77 #define L6474_CONF_PARAM_ACC_DEVICE_0 (160)
gregeric 0:b9444a40a999 78 /// Acceleration rate in step/s2 for device 1 (must be greater than 0)
gregeric 0:b9444a40a999 79 #define L6474_CONF_PARAM_ACC_DEVICE_1 (160)
gregeric 0:b9444a40a999 80 /// Acceleration rate in step/s2 for device 2 (must be greater than 0)
gregeric 0:b9444a40a999 81 #define L6474_CONF_PARAM_ACC_DEVICE_2 (160)
gregeric 0:b9444a40a999 82
gregeric 0:b9444a40a999 83 /// Deceleration rate in step/s2 for device 0 (must be greater than 0)
gregeric 0:b9444a40a999 84 #define L6474_CONF_PARAM_DEC_DEVICE_0 (160)
gregeric 0:b9444a40a999 85 /// Deceleration rate in step/s2 for device 1 (must be greater than 0)
gregeric 0:b9444a40a999 86 #define L6474_CONF_PARAM_DEC_DEVICE_1 (160)
gregeric 0:b9444a40a999 87 /// Deceleration rate in step/s2 for device 2 (must be greater than 0)
gregeric 0:b9444a40a999 88 #define L6474_CONF_PARAM_DEC_DEVICE_2 (160)
gregeric 0:b9444a40a999 89
gregeric 0:b9444a40a999 90 /// Maximum speed in step/s for device 0 (30 step/s < Maximum speed <= 10 000 step/s )
gregeric 0:b9444a40a999 91 #define L6474_CONF_PARAM_MAX_SPEED_DEVICE_0 (1600)
gregeric 0:b9444a40a999 92 /// Maximum speed in step/s for device 1 (30 step/s < Maximum speed <= 10 000 step/s )
gregeric 0:b9444a40a999 93 #define L6474_CONF_PARAM_MAX_SPEED_DEVICE_1 (1600)
gregeric 0:b9444a40a999 94 /// Maximum speed in step/s for device 2 (30 step/s < Maximum speed <= 10 000 step/s )
gregeric 0:b9444a40a999 95 #define L6474_CONF_PARAM_MAX_SPEED_DEVICE_2 (1600)
gregeric 0:b9444a40a999 96
gregeric 0:b9444a40a999 97 /// Minimum speed in step/s for device 0 (30 step/s <= Minimum speed < 10 000 step/s)
gregeric 0:b9444a40a999 98 #define L6474_CONF_PARAM_MIN_SPEED_DEVICE_0 (800)
gregeric 0:b9444a40a999 99 /// Minimum speed in step/s for device 1 (30 step/s <= Minimum speed < 10 000 step/s)
gregeric 0:b9444a40a999 100 #define L6474_CONF_PARAM_MIN_SPEED_DEVICE_1 (800)
gregeric 0:b9444a40a999 101 /// Minimum speed in step/s for device 2 (30 step/s <= Minimum speed < 10 000 step/s)
gregeric 0:b9444a40a999 102 #define L6474_CONF_PARAM_MIN_SPEED_DEVICE_2 (800)
gregeric 0:b9444a40a999 103
gregeric 0:b9444a40a999 104
gregeric 0:b9444a40a999 105 /************************ Phase Current Control *******************************/
gregeric 0:b9444a40a999 106
gregeric 0:b9444a40a999 107 // Current value that is assigned to the torque regulation DAC
gregeric 0:b9444a40a999 108 /// TVAL register value for device 0 (range 31.25mA to 4000mA)
gregeric 0:b9444a40a999 109 #define L6474_CONF_PARAM_TVAL_DEVICE_0 (250)
gregeric 0:b9444a40a999 110 /// TVAL register value for device 1 (range 31.25mA to 4000mA)
gregeric 0:b9444a40a999 111 #define L6474_CONF_PARAM_TVAL_DEVICE_1 (250)
gregeric 0:b9444a40a999 112 /// TVAL register value for device 2 (range 31.25mA to 4000mA)
gregeric 0:b9444a40a999 113 #define L6474_CONF_PARAM_TVAL_DEVICE_2 (250)
gregeric 0:b9444a40a999 114
gregeric 0:b9444a40a999 115 /// Fall time value (T_FAST field of T_FAST register) for device 0 (range 2us to 32us)
gregeric 0:b9444a40a999 116 #define L6474_CONF_PARAM_FAST_STEP_DEVICE_0 (L6474_FAST_STEP_12us)
gregeric 0:b9444a40a999 117 /// Fall time value (T_FAST field of T_FAST register) for device 1 (range 2us to 32us)
gregeric 0:b9444a40a999 118 #define L6474_CONF_PARAM_FAST_STEP_DEVICE_1 (L6474_FAST_STEP_12us)
gregeric 0:b9444a40a999 119 /// Fall time value (T_FAST field of T_FAST register) for device 2 (range 2us to 32us)
gregeric 0:b9444a40a999 120 #define L6474_CONF_PARAM_FAST_STEP_DEVICE_2 (L6474_FAST_STEP_12us)
gregeric 0:b9444a40a999 121
gregeric 0:b9444a40a999 122 /// Maximum fast decay time (T_OFF field of T_FAST register) for device 0 (range 2us to 32us)
gregeric 0:b9444a40a999 123 #define L6474_CONF_PARAM_TOFF_FAST_DEVICE_0 (L6474_TOFF_FAST_8us)
gregeric 0:b9444a40a999 124 /// Maximum fast decay time (T_OFF field of T_FAST register) for device 1 (range 2us to 32us)
gregeric 0:b9444a40a999 125 #define L6474_CONF_PARAM_TOFF_FAST_DEVICE_1 (L6474_TOFF_FAST_8us)
gregeric 0:b9444a40a999 126 /// Maximum fast decay time (T_OFF field of T_FAST register) for device 2 (range 2us to 32us)
gregeric 0:b9444a40a999 127 #define L6474_CONF_PARAM_TOFF_FAST_DEVICE_2 (L6474_TOFF_FAST_8us)
gregeric 0:b9444a40a999 128
gregeric 0:b9444a40a999 129 /// Minimum ON time (TON_MIN register) for device 0 (range 0.5us to 64us)
gregeric 0:b9444a40a999 130 #define L6474_CONF_PARAM_TON_MIN_DEVICE_0 (3)
gregeric 0:b9444a40a999 131 /// Minimum ON time (TON_MIN register) for device 1 (range 0.5us to 64us)
gregeric 0:b9444a40a999 132 #define L6474_CONF_PARAM_TON_MIN_DEVICE_1 (3)
gregeric 0:b9444a40a999 133 /// Minimum ON time (TON_MIN register) for device 2 (range 0.5us to 64us)
gregeric 0:b9444a40a999 134 #define L6474_CONF_PARAM_TON_MIN_DEVICE_2 (3)
gregeric 0:b9444a40a999 135
gregeric 0:b9444a40a999 136 /// Minimum OFF time (TOFF_MIN register) for device 0 (range 0.5us to 64us)
gregeric 0:b9444a40a999 137 #define L6474_CONF_PARAM_TOFF_MIN_DEVICE_0 (21)
gregeric 0:b9444a40a999 138 /// Minimum OFF time (TOFF_MIN register) for device 1 (range 0.5us to 64us)
gregeric 0:b9444a40a999 139 #define L6474_CONF_PARAM_TOFF_MIN_DEVICE_1 (21)
gregeric 0:b9444a40a999 140 /// Minimum OFF time (TOFF_MIN register) for device 2 (range 0.5us to 64us)
gregeric 0:b9444a40a999 141 #define L6474_CONF_PARAM_TOFF_MIN_DEVICE_2 (21)
gregeric 0:b9444a40a999 142
gregeric 0:b9444a40a999 143 /******************************* Others ***************************************/
gregeric 0:b9444a40a999 144
gregeric 0:b9444a40a999 145 /// Overcurrent threshold settings for device 0 (OCD_TH register)
gregeric 0:b9444a40a999 146 #define L6474_CONF_PARAM_OCD_TH_DEVICE_0 (L6474_OCD_TH_750mA)
gregeric 0:b9444a40a999 147 /// Overcurrent threshold settings for device 1 (OCD_TH register)
gregeric 0:b9444a40a999 148 #define L6474_CONF_PARAM_OCD_TH_DEVICE_1 (L6474_OCD_TH_750mA)
gregeric 0:b9444a40a999 149 /// Overcurrent threshold settings for device 2 (OCD_TH register)
gregeric 0:b9444a40a999 150 #define L6474_CONF_PARAM_OCD_TH_DEVICE_2 (L6474_OCD_TH_750mA)
gregeric 0:b9444a40a999 151
gregeric 0:b9444a40a999 152 /// Alarm settings for device 0 (ALARM_EN register)
gregeric 0:b9444a40a999 153 #define L6474_CONF_PARAM_ALARM_EN_DEVICE_0 (L6474_ALARM_EN_OVERCURRENT |\
gregeric 0:b9444a40a999 154 L6474_ALARM_EN_THERMAL_SHUTDOWN |\
gregeric 0:b9444a40a999 155 L6474_ALARM_EN_THERMAL_WARNING |\
gregeric 0:b9444a40a999 156 L6474_ALARM_EN_UNDERVOLTAGE |\
gregeric 0:b9444a40a999 157 L6474_ALARM_EN_SW_TURN_ON |\
gregeric 0:b9444a40a999 158 L6474_ALARM_EN_WRONG_NPERF_CMD)
gregeric 0:b9444a40a999 159
gregeric 0:b9444a40a999 160 ///Alarm settings for device 1 (ALARM_EN register)
gregeric 0:b9444a40a999 161 #define L6474_CONF_PARAM_ALARM_EN_DEVICE_1 (L6474_ALARM_EN_OVERCURRENT |\
gregeric 0:b9444a40a999 162 L6474_ALARM_EN_THERMAL_SHUTDOWN |\
gregeric 0:b9444a40a999 163 L6474_ALARM_EN_THERMAL_WARNING |\
gregeric 0:b9444a40a999 164 L6474_ALARM_EN_UNDERVOLTAGE |\
gregeric 0:b9444a40a999 165 L6474_ALARM_EN_SW_TURN_ON |\
gregeric 0:b9444a40a999 166 L6474_ALARM_EN_WRONG_NPERF_CMD)
gregeric 0:b9444a40a999 167
gregeric 0:b9444a40a999 168 /// Alarm settings for device 2 (ALARM_EN register)
gregeric 0:b9444a40a999 169 #define L6474_CONF_PARAM_ALARM_EN_DEVICE_2 (L6474_ALARM_EN_OVERCURRENT |\
gregeric 0:b9444a40a999 170 L6474_ALARM_EN_THERMAL_SHUTDOWN |\
gregeric 0:b9444a40a999 171 L6474_ALARM_EN_THERMAL_WARNING |\
gregeric 0:b9444a40a999 172 L6474_ALARM_EN_UNDERVOLTAGE |\
gregeric 0:b9444a40a999 173 L6474_ALARM_EN_SW_TURN_ON |\
gregeric 0:b9444a40a999 174 L6474_ALARM_EN_WRONG_NPERF_CMD)
gregeric 0:b9444a40a999 175
gregeric 0:b9444a40a999 176 /// Step selection settings for device 0 (STEP_SEL field of STEP_MODE register)
gregeric 0:b9444a40a999 177 #define L6474_CONF_PARAM_STEP_SEL_DEVICE_0 (L6474_STEP_SEL_1_16)
gregeric 0:b9444a40a999 178 /// Step selection settings for device 1 (STEP_SEL field of STEP_MODE register)
gregeric 0:b9444a40a999 179 #define L6474_CONF_PARAM_STEP_SEL_DEVICE_1 (L6474_STEP_SEL_1_16)
gregeric 0:b9444a40a999 180 /// Step selection settings for device 2 (STEP_SEL field of STEP_MODE register)
gregeric 0:b9444a40a999 181 #define L6474_CONF_PARAM_STEP_SEL_DEVICE_2 (L6474_STEP_SEL_1_16)
gregeric 0:b9444a40a999 182
gregeric 0:b9444a40a999 183 /// Synch. selection settings for device 0 (SYNC_SEL field of STEP_MODE register)
gregeric 0:b9444a40a999 184 #define L6474_CONF_PARAM_SYNC_SEL_DEVICE_0 (L6474_SYNC_SEL_1_2)
gregeric 0:b9444a40a999 185 /// Synch. selection settings for device 1 (SYNC_SEL field of STEP_MODE register)
gregeric 0:b9444a40a999 186 #define L6474_CONF_PARAM_SYNC_SEL_DEVICE_1 (L6474_SYNC_SEL_1_2)
gregeric 0:b9444a40a999 187 /// Synch. selection settings for device 2 (SYNC_SEL field of STEP_MODE register)
gregeric 0:b9444a40a999 188 #define L6474_CONF_PARAM_SYNC_SEL_DEVICE_2 (L6474_SYNC_SEL_1_2)
gregeric 0:b9444a40a999 189
gregeric 0:b9444a40a999 190 /// Target Swicthing Period for device 0 (field TOFF of CONFIG register)
gregeric 0:b9444a40a999 191 #define L6474_CONF_PARAM_TOFF_DEVICE_0 (L6474_CONFIG_TOFF_044us)
gregeric 0:b9444a40a999 192 /// Target Swicthing Period for device 1 (field TOFF of CONFIG register)
gregeric 0:b9444a40a999 193 #define L6474_CONF_PARAM_TOFF_DEVICE_1 (L6474_CONFIG_TOFF_044us)
gregeric 0:b9444a40a999 194 /// Target Swicthing Period for device 2 (field TOFF of CONFIG register)
gregeric 0:b9444a40a999 195 #define L6474_CONF_PARAM_TOFF_DEVICE_2 (L6474_CONFIG_TOFF_044us)
gregeric 0:b9444a40a999 196
gregeric 0:b9444a40a999 197 /// Slew rate for device 0 (POW_SR field of CONFIG register)
gregeric 0:b9444a40a999 198 #define L6474_CONF_PARAM_SR_DEVICE_0 (L6474_CONFIG_SR_320V_us)
gregeric 0:b9444a40a999 199 /// Slew rate for device 1 (POW_SR field of CONFIG register)
gregeric 0:b9444a40a999 200 #define L6474_CONF_PARAM_SR_DEVICE_1 (L6474_CONFIG_SR_320V_us)
gregeric 0:b9444a40a999 201 /// Slew rate for device 2 (POW_SR field of CONFIG register)
gregeric 0:b9444a40a999 202 #define L6474_CONF_PARAM_SR_DEVICE_2 (L6474_CONFIG_SR_320V_us)
gregeric 0:b9444a40a999 203
gregeric 0:b9444a40a999 204 /// Over current shutwdown enabling for device 0 (OC_SD field of CONFIG register)
gregeric 0:b9444a40a999 205 #define L6474_CONF_PARAM_OC_SD_DEVICE_0 (L6474_CONFIG_OC_SD_ENABLE)
gregeric 0:b9444a40a999 206 /// Over current shutwdown enabling for device 1 (OC_SD field of CONFIG register)
gregeric 0:b9444a40a999 207 #define L6474_CONF_PARAM_OC_SD_DEVICE_1 (L6474_CONFIG_OC_SD_ENABLE)
gregeric 0:b9444a40a999 208 /// Over current shutwdown enabling for device 2 (OC_SD field of CONFIG register)
gregeric 0:b9444a40a999 209 #define L6474_CONF_PARAM_OC_SD_DEVICE_2 (L6474_CONFIG_OC_SD_ENABLE)
gregeric 0:b9444a40a999 210
gregeric 0:b9444a40a999 211 /// Torque regulation method for device 0 (EN_TQREG field of CONFIG register)
gregeric 0:b9444a40a999 212 #define L6474_CONF_PARAM_TQ_REG_DEVICE_0 (L6474_CONFIG_EN_TQREG_TVAL_USED)
gregeric 0:b9444a40a999 213 ///Torque regulation method for device 1 (EN_TQREG field of CONFIG register)
gregeric 0:b9444a40a999 214 #define L6474_CONF_PARAM_TQ_REG_DEVICE_1 (L6474_CONFIG_EN_TQREG_TVAL_USED)
gregeric 0:b9444a40a999 215 /// Torque regulation method for device 2 (EN_TQREG field of CONFIG register)
gregeric 0:b9444a40a999 216 #define L6474_CONF_PARAM_TQ_REG_DEVICE_2 (L6474_CONFIG_EN_TQREG_TVAL_USED)
gregeric 0:b9444a40a999 217
gregeric 0:b9444a40a999 218 /// Clock setting for device 0 (OSC_CLK_SEL field of CONFIG register)
gregeric 0:b9444a40a999 219 #define L6474_CONF_PARAM_CLOCK_SETTING_DEVICE_0 (L6474_CONFIG_INT_16MHZ)
gregeric 0:b9444a40a999 220 /// Clock setting for device 1 (OSC_CLK_SEL field of CONFIG register)
gregeric 0:b9444a40a999 221 #define L6474_CONF_PARAM_CLOCK_SETTING_DEVICE_1 (L6474_CONFIG_INT_16MHZ)
gregeric 0:b9444a40a999 222 /// Clock setting for device 2 (OSC_CLK_SEL field of CONFIG register)
gregeric 0:b9444a40a999 223 #define L6474_CONF_PARAM_CLOCK_SETTING_DEVICE_2 (L6474_CONFIG_INT_16MHZ)
gregeric 0:b9444a40a999 224
gregeric 0:b9444a40a999 225
gregeric 0:b9444a40a999 226 /**
gregeric 0:b9444a40a999 227 * @}
gregeric 0:b9444a40a999 228 */
gregeric 0:b9444a40a999 229
gregeric 0:b9444a40a999 230 /**
gregeric 0:b9444a40a999 231 * @}
gregeric 0:b9444a40a999 232 */
gregeric 0:b9444a40a999 233
gregeric 0:b9444a40a999 234 /**
gregeric 0:b9444a40a999 235 * @}
gregeric 0:b9444a40a999 236 */
gregeric 0:b9444a40a999 237
gregeric 0:b9444a40a999 238 /**
gregeric 0:b9444a40a999 239 * @}
gregeric 0:b9444a40a999 240 */
gregeric 0:b9444a40a999 241
gregeric 0:b9444a40a999 242 #ifdef __cplusplus
gregeric 0:b9444a40a999 243 }
gregeric 0:b9444a40a999 244 #endif
gregeric 0:b9444a40a999 245
gregeric 0:b9444a40a999 246 #endif /* __L6474_TARGET_CONFIG_H */