Janusz G / FXOS8700CQ

An in-development library to provide effective access to all features of the FXOS8700CQ on the FRDM-K64F mbed-enabled development board. As of 28 May 2014 1325EDT, the code should be generally usable and modifiable.

FXOS8700CQ.h@0:cf6299acfe98, 2014-05-28 (annotated)

Committer:
trm
Date:
Wed May 28 13:28:18 2014 +0000
Revision:
0:cf6299acfe98
Child:
1:3ec7e2676e48
Successful driver for FXOS8700CQ on FRDM-K64F. Configured for 2g accelerometer range, hybrid readings at 200Hz, data ready interrupts on INT2, auto-zero of the magnometer, full-data read. WARNING: data is swapped acc/magn and acc data is 4x large.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
trm 0:cf6299acfe98 1 #ifndef FXOS8700CQ_H
trm 0:cf6299acfe98 2 #define FXOS8700CQ_H
trm 0:cf6299acfe98 3
trm 0:cf6299acfe98 4 #include "mbed.h" // Building this for the mbed platform
trm 0:cf6299acfe98 5
trm 0:cf6299acfe98 6 #define I2C_400K 400000
trm 0:cf6299acfe98 7
trm 0:cf6299acfe98 8 // FXOS8700CQ I2C address
trm 0:cf6299acfe98 9 #define FXOS8700CQ_SLAVE_ADDR0 (0x1E<<1) // with pins SA0=0, SA1=0
trm 0:cf6299acfe98 10 #define FXOS8700CQ_SLAVE_ADDR1 (0x1D<<1) // with pins SA0=1, SA1=0
trm 0:cf6299acfe98 11 #define FXOS8700CQ_SLAVE_ADDR2 (0x1C<<1) // with pins SA0=0, SA1=1
trm 0:cf6299acfe98 12 #define FXOS8700CQ_SLAVE_ADDR3 (0x1F<<1) // with pins SA0=1, SA1=1
trm 0:cf6299acfe98 13
trm 0:cf6299acfe98 14 // FXOS8700CQ internal register addresses
trm 0:cf6299acfe98 15 #define FXOS8700CQ_STATUS 0x00
trm 0:cf6299acfe98 16 #define FXOS8700CQ_OUT_X_MSB 0x01
trm 0:cf6299acfe98 17 #define FXOS8700CQ_WHOAMI 0x0D
trm 0:cf6299acfe98 18 #define FXOS8700CQ_XYZ_DATA_CFG 0x0E
trm 0:cf6299acfe98 19 #define FXOS8700CQ_CTRL_REG1 0x2A
trm 0:cf6299acfe98 20 #define FXOS8700CQ_CTRL_REG2 0x2B
trm 0:cf6299acfe98 21 #define FXOS8700CQ_CTRL_REG3 0x2C
trm 0:cf6299acfe98 22 #define FXOS8700CQ_CTRL_REG4 0x2D
trm 0:cf6299acfe98 23 #define FXOS8700CQ_CTRL_REG5 0x2E
trm 0:cf6299acfe98 24
trm 0:cf6299acfe98 25 #define FXOS8700CQ_M_OUT_X_MSB 0x34
trm 0:cf6299acfe98 26
trm 0:cf6299acfe98 27 #define FXOS8700CQ_M_CTRL_REG1 0x5B
trm 0:cf6299acfe98 28 #define FXOS8700CQ_M_CTRL_REG2 0x5C
trm 0:cf6299acfe98 29 #define FXOS8700CQ_M_CTRL_REG3 0x5D
trm 0:cf6299acfe98 30
trm 0:cf6299acfe98 31 // FXOS8700CQ WHOAMI production register value
trm 0:cf6299acfe98 32 #define FXOS8700CQ_WHOAMI_VAL 0xC7
trm 0:cf6299acfe98 33
trm 0:cf6299acfe98 34 // 6 channels of two bytes = 12 bytes; read from FXOS8700CQ_OUT_X_MSB
trm 0:cf6299acfe98 35 #define FXOS8700CQ_READ_LEN 12
trm 0:cf6299acfe98 36
trm 0:cf6299acfe98 37 // From mbed I2C documentation for complete read/write transactions
trm 0:cf6299acfe98 38 #define I2C_SUCCESS 0
trm 0:cf6299acfe98 39 #define I2C_FAILURE 1
trm 0:cf6299acfe98 40
trm 0:cf6299acfe98 41 // For processing the accelerometer data to right-justified 2's complement
trm 0:cf6299acfe98 42 #define UINT14_MAX 16383
trm 0:cf6299acfe98 43
trm 0:cf6299acfe98 44 // TODO: struct to hold the data out of the sensor
trm 0:cf6299acfe98 45 typedef struct {
trm 0:cf6299acfe98 46 int16_t x;
trm 0:cf6299acfe98 47 int16_t y;
trm 0:cf6299acfe98 48 int16_t z;
trm 0:cf6299acfe98 49 } SRAWDATA;
trm 0:cf6299acfe98 50
trm 0:cf6299acfe98 51 class FXOS8700CQ
trm 0:cf6299acfe98 52 {
trm 0:cf6299acfe98 53 public:
trm 0:cf6299acfe98 54 /**
trm 0:cf6299acfe98 55 * FXOS8700CQ constructor
trm 0:cf6299acfe98 56 *
trm 0:cf6299acfe98 57 * @param sda SDA pin
trm 0:cf6299acfe98 58 * @param sdl SCL pin
trm 0:cf6299acfe98 59 * @param addr address of the I2C peripheral in (7-bit << 1) form
trm 0:cf6299acfe98 60 */
trm 0:cf6299acfe98 61
trm 0:cf6299acfe98 62 FXOS8700CQ(PinName sda, PinName scl, int addr);
trm 0:cf6299acfe98 63
trm 0:cf6299acfe98 64 /**
trm 0:cf6299acfe98 65 * FXOS8700CQ destructor
trm 0:cf6299acfe98 66 */
trm 0:cf6299acfe98 67 ~FXOS8700CQ();
trm 0:cf6299acfe98 68
trm 0:cf6299acfe98 69 void enable(void);
trm 0:cf6299acfe98 70 void disable(void);
trm 0:cf6299acfe98 71 uint8_t get_whoami(void);
trm 0:cf6299acfe98 72 uint8_t status(void);
trm 0:cf6299acfe98 73 void get_data(SRAWDATA *accel_data, SRAWDATA *magn_data);
trm 0:cf6299acfe98 74
trm 0:cf6299acfe98 75
trm 0:cf6299acfe98 76
trm 0:cf6299acfe98 77 private:
trm 0:cf6299acfe98 78 I2C dev_i2c; // instance of the mbed I2C class
trm 0:cf6299acfe98 79 uint8_t dev_addr; // Device I2C address, in (7-bit << 1) form
trm 0:cf6299acfe98 80
trm 0:cf6299acfe98 81 // I2C helper methods
trm 0:cf6299acfe98 82 void read_regs(int reg_addr, uint8_t* data, int len);
trm 0:cf6299acfe98 83 void write_regs(uint8_t* data, int len);
trm 0:cf6299acfe98 84
trm 0:cf6299acfe98 85 };
trm 0:cf6299acfe98 86
trm 0:cf6299acfe98 87 #endif