BBC Basic in Z80 emulation on the mbed, USB serial terminal output only. LOAD and SAVE work on the local file system but there is no error signalling.

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Show/hide line numbers cbops.h Source File

cbops.h

00001 /* Emulations of the CB/DD and FD operations of the Z80 instruction set.
00002  * Copyright (C) 1994 Ian Collier.
00003  *
00004  * This program is free software; you can redistribute it and/or modify
00005  * it under the terms of the GNU General Public License as published by
00006  * the Free Software Foundation; either version 2 of the License, or
00007  * (at your option) any later version.
00008  *
00009  * This program is distributed in the hope that it will be useful,
00010  * but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  * GNU General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License
00015  * along with this program; if not, write to the Free Software
00016  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
00017  */
00018 
00019 #define var_t   unsigned char t
00020 #define rlc(x)  (x=(x<<1)|(x>>7),rflags(x,x&1))
00021 #define rrc(x)  do{var_t=x&1;x=(x>>1)|(t<<7);rflags(x,t);}while(0)
00022 #define rl(x)   do{var_t=x>>7;x=(x<<1)|(f&1);rflags(x,t);}while(0)
00023 #define rr(x)   do{var_t=x&1;x=(x>>1)|(f<<7);rflags(x,t);}while(0)
00024 #define sla(x)  do{var_t=x>>7;x<<=1;rflags(x,t);}while(0)
00025 #define sra(x)  do{var_t=x&1;x=((signed char)x)>>1;rflags(x,t);}while(0)
00026 #define sll(x)  do{var_t=x>>7;x=(x<<1)|1;rflags(x,t);}while(0)
00027 #define srl(x)  do{var_t=x&1;x>>=1;rflags(x,t);}while(0)
00028 
00029 #define rflags(x,c) (f=(c)|(x&0xa8)|((!x)<<6)|parity(x))
00030 
00031 #define bit(n,x) (f=(f&1)|((x&(1<<n))?0x10:0x54)|(x&0x28))
00032 #define set(n,x) (x|=(1<<n))
00033 #define res(n,x) (x&=~(1<<n))
00034 
00035 {
00036    /* reg/val are initialised to stop gcc's (incorrect) warning,
00037     * and static to save initialising them every time.
00038     */
00039    static unsigned char reg=0,val=0;
00040    unsigned short addr;
00041    unsigned char op;
00042   if(ixoriy){
00043     // if IX or IY addressing add the '+d' part
00044      addr=(ixoriy==1?ix:iy)+(signed char)fetch(pc);
00045      pc++;
00046      op=fetch(pc);
00047      reg=op&7;
00048      op=(op&0xf8)|6;
00049   }
00050   else{
00051       op=fetch(pc);
00052       addr=hl;
00053   }
00054    pc++;
00055 
00056    if(op<64)switch(op){
00057    case  0: rlc(b); break;
00058    case  1: rlc(c); break;
00059    case  2: rlc(d); break;
00060    case  3: rlc(e); break;
00061    case  4: rlc(h); break;
00062    case  5: rlc(l); break;
00063    case  6: val=fetch(addr);rlc(val);store(addr,val);break;
00064    case  7: rlc(a); break;
00065    case  8: rrc(b); break;
00066    case  9: rrc(c); break;
00067    case 10: rrc(d); break;
00068    case 11: rrc(e); break;
00069    case 12: rrc(h); break;
00070    case 13: rrc(l); break;
00071    case 14: val=fetch(addr);rrc(val);store(addr,val);break;
00072    case 15: rrc(a); break;
00073    case 0x10: rl(b); break;
00074    case 0x11: rl(c); break;
00075    case 0x12: rl(d); break;
00076    case 0x13: rl(e); break;
00077    case 0x14: rl(h); break;
00078    case 0x15: rl(l); break;
00079    case 0x16: val=fetch(addr);rl(val);store(addr,val);break;
00080    case 0x17: rl(a); break;
00081    case 0x18: rr(b); break;
00082    case 0x19: rr(c); break;
00083    case 0x1a: rr(d); break;
00084    case 0x1b: rr(e); break;
00085    case 0x1c: rr(h); break;
00086    case 0x1d: rr(l); break;
00087    case 0x1e: val=fetch(addr);rr(val);store(addr,val);break;
00088    case 0x1f: rr(a); break;
00089    case 0x20: sla(b); break;
00090    case 0x21: sla(c); break;
00091    case 0x22: sla(d); break;
00092    case 0x23: sla(e); break;
00093    case 0x24: sla(h); break;
00094    case 0x25: sla(l); break;
00095    case 0x26: val=fetch(addr);sla(val);store(addr,val);break;
00096    case 0x27: sla(a); break;
00097    case 0x28: sra(b); break;
00098    case 0x29: sra(c); break;
00099    case 0x2a: sra(d); break;
00100    case 0x2b: sra(e); break;
00101    case 0x2c: sra(h); break;
00102    case 0x2d: sra(l); break;
00103    case 0x2e: val=fetch(addr);sra(val);store(addr,val);break;
00104    case 0x2f: sra(a); break;
00105    case 0x30: sll(b); break;
00106    case 0x31: sll(c); break;
00107    case 0x32: sll(d); break;
00108    case 0x33: sll(e); break;
00109    case 0x34: sll(h); break;
00110    case 0x35: sll(l); break;
00111    case 0x36: val=fetch(addr);sll(val);store(addr,val);break;
00112    case 0x37: sll(a); break;
00113    case 0x38: srl(b); break;
00114    case 0x39: srl(c); break;
00115    case 0x3a: srl(d); break;
00116    case 0x3b: srl(e); break;
00117    case 0x3c: srl(h); break;
00118    case 0x3d: srl(l); break;
00119    case 0x3e: val=fetch(addr);srl(val);store(addr,val);break;
00120    case 0x3f: srl(a); break;
00121    }
00122    else{
00123       unsigned char n=(op>>3)&7;
00124       switch(op&0xc7){
00125       case 0x40: bit(n,b); break;
00126       case 0x41: bit(n,c); break;
00127       case 0x42: bit(n,d); break;
00128       case 0x43: bit(n,e); break;
00129       case 0x44: bit(n,h); break;
00130       case 0x45: bit(n,l); break;
00131       case 0x46: val=fetch(addr);bit(n,val);break;
00132       case 0x47: bit(n,a); break;
00133       case 0x80: res(n,b); break;
00134       case 0x81: res(n,c); break;
00135       case 0x82: res(n,d); break;
00136       case 0x83: res(n,e); break;
00137       case 0x84: res(n,h); break;
00138       case 0x85: res(n,l); break;
00139       case 0x86: val=fetch(addr);res(n,val);store(addr,val);break;
00140       case 0x87: res(n,a); break;
00141       case 0xc0: set(n,b); break;
00142       case 0xc1: set(n,c); break;
00143       case 0xc2: set(n,d); break;
00144       case 0xc3: set(n,e); break;
00145       case 0xc4: set(n,h); break;
00146       case 0xc5: set(n,l); break;
00147       case 0xc6: val=fetch(addr);set(n,val);store(addr,val);break;
00148       case 0xc7: set(n,a); break;
00149       }
00150    }
00151    if(ixoriy)switch(reg){
00152       case 0:b=val; break;
00153       case 1:c=val; break;
00154       case 2:d=val; break;
00155       case 3:e=val; break;
00156       case 4:h=val; break;
00157       case 5:l=val; break;
00158       case 7:a=val; break;
00159    }
00160 }
00161 
00162 #undef var_t
00163 #undef rlc
00164 #undef rrc
00165 #undef rl
00166 #undef rr
00167 #undef sla
00168 #undef sra
00169 #undef sll
00170 #undef srl
00171 #undef rflags
00172 #undef bit
00173 #undef set
00174 #undef res