Mike Moore
/
RTOS_project_fork_01
embedded RTOS class project.
Fork of RTOS_project by
Diff: mmRTL/mux16x2.txt
- Revision:
- 0:8e898e1270d6
diff -r 000000000000 -r 8e898e1270d6 mmRTL/mux16x2.txt --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mmRTL/mux16x2.txt Tue Sep 17 19:42:49 2013 +0000 @@ -0,0 +1,65 @@ +/*----------------------------------copyright---------------------------------*/ +// licensed for personal and academic use. +// commercial use must be approved by the account-holder of +// gated.clock@gmail.com +/*-----------------------------------module-----------------------------------*/ + module mux16x2 + ( + iDin1, // data-input 1. + iDin0, // data-input 0. + iSel, // multiplexor select. + oDout // data-out. + ); +/*--------------------------------description----------------------------------- + a 16-bit-wide, 2-selection multiplexor. +-------------------------------------notes-------------------------------------- +------------------------------------defines-----------------------------------*/ +/*-----------------------------------ports------------------------------------*/ + input [15:0] iDin1; // data-input 1. + input [15:0] iDin0; // data-input 0. + input iSel; // multiplexor select. + output [15:0] oDout; // data-out. +/*-----------------------------------wires------------------------------------*/ + wire [15:0] iDin1; // data-input 1. + wire [15:0] iDin0; // data-input 0. + wire iSel; // multiplexor select. + wire [15:0] oDout; // data-out. +/*---------------------------------registers----------------------------------*/ + reg [15:0] rDout; // output register. +/*---------------------------------variables----------------------------------*/ +/*---------------------------------parameters---------------------------------*/ +/*-----------------------------------clocks-----------------------------------*/ +/*---------------------------------instances----------------------------------*/ +/*-----------------------------------logic------------------------------------*/ + always @ (iDin1 or iDin0 or iSel) + case (iSel) + 1 : rDout = iDin1; + 0 : rDout = iDin0; + endcase + + assign oDout = rDout; // propagate output. +/*-------------------------------*/endmodule/*--------------------------------*/ + + + + + + + + + + + + + + + + + + + + + + + +