Revision 3:659ffc90b59e, committed 2013-09-01

Comitter:

gatedClock

Date:

Sun Sep 01 02:53:39 2013 +0000

Parent:

2:08655e2bb776

Child:

4:92539904a4ad

Commit message:

add the project RTL files. the tab-formatting needs to be redone.

Changed in this revision

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/counter_08.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,115 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module counter_08
+        (
+         oCount,                // counter state.
+         iParallel7,                // parallel-input  data.
+         iParallel6,                // parallel-input  data.
+         iParallel5,                // parallel-input  data.
+         iParallel4,                // parallel-input  data.
+         iParallel3,                // parallel-input  data.
+         iParallel2,                // parallel-input  data.
+         iParallel1,                // parallel-input  data.
+         iParallel0,                // parallel-input  data.
+     iSel,                  // select the parallel input.
+     oSerial,               // serial-output data.
+     iSerial,               // serial-input data.
+     iLoadEnable,               // parallel-load-enable.
+     iShiftEnable,              // serial-shift-enable.
+     iCountEnable,              // count-increment enable.
+     iResetN,               // synchronous reset*.
+     iClk                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+    an 8-bit preloadable counter.
+-------------------------------------notes--------------------------------------
+    shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    output  [ 7:0]  oCount;         // counter state.
+    input   [ 7:0]  iParallel7;     // parallel-input  data.
+    input   [ 7:0]  iParallel6;     // parallel-input  data.
+    input   [ 7:0]  iParallel5;     // parallel-input  data.
+    input   [ 7:0]  iParallel4;     // parallel-input  data.
+    input   [ 7:0]  iParallel3;     // parallel-input  data.
+    input   [ 7:0]  iParallel2;     // parallel-input  data.
+    input   [ 7:0]  iParallel1;     // parallel-input  data.
+    input   [ 7:0]  iParallel0;     // parallel-input  data.
+    input   [ 2:0]  iSel;           // select the parallel input.
+    output          oSerial;        // serial-output data.
+    input           iSerial;        // serial-input data.
+    input           iLoadEnable;        // parallel-load-enable.
+    input           iShiftEnable;       // serial-shift-enable.
+    input           iCountEnable;       // count-increment enable.
+    input           iResetN;        // synchronous reset*.
+    input           iClk;           // module clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [ 7:0]  oCount;         // counter state.
+    wire    [ 7:0]  iParallel7;     // parallel-input  data.
+    wire    [ 7:0]  iParallel6;     // parallel-input  data.
+    wire    [ 7:0]  iParallel5;     // parallel-input  data.
+    wire    [ 7:0]  iParallel4;     // parallel-input  data.
+    wire    [ 7:0]  iParallel3;     // parallel-input  data.
+    wire    [ 7:0]  iParallel2;     // parallel-input  data.
+    wire    [ 7:0]  iParallel1;     // parallel-input  data.
+    wire    [ 7:0]  iParallel0;     // parallel-input  data.
+    wire    [ 2:0]  iSel;           // select the parallel input.
+    wire    [ 7:0]  wParallelIn;        // select the parallel input.
+    wire            oSerial;        // serial-output data.
+    wire            iSerial;        // serial-input data.
+    wire            iLoadEnable;        // parallel-load-enable.
+    wire            iShiftEnable;       // serial-shift-enable.
+    wire            iCountEnable;       // count-increment enable.
+    wire            iResetN;        // synchronous reset*.
+    wire            iClk;           // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rRegister;      // the counter state.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+    mux8x8 U01_mux8x8           // data-input selection.
+        (
+     .iDin7(iParallel7),
+     .iDin6(iParallel6),
+     .iDin5(iParallel5),
+     .iDin4(iParallel4),
+     .iDin3(iParallel3),
+     .iDin2(iParallel2),
+     .iDin1(iParallel1),
+     .iDin0(iParallel0),
+     .iSel (iSel),
+     .oDout(wParallelIn)
+        );
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iClk or negedge iResetN)
+    begin
+           if (!iResetN)     rRegister <= 8'h00;
+      else if (iLoadEnable)  rRegister <= wParallelIn;
+      else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+      else if (iCountEnable) rRegister <= rRegister + 1'b1;
+      else                   rRegister <= rRegister;
+    end
+
+    assign oCount    = rRegister;       // propagate counter state.
+    assign oSerial   = rRegister[7];    // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/cpu.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,514 @@
+/*----------------------------------copyright---//----------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----//----------------------------*/
+    module cpu
+        (
+      iMOSI,
+          oMISO,
+      iSPIclk,
+      iCPUclk,
+      iKEY,
+      iSW,
+      oLEDR,
+      oLEDG,
+      oDummyLoad
+        );
+/*--------------------------------description---//------------------------------
+    the demonstration cpu datapath.
+
+    the CPU consists of
+    R0 -  8-bit register and accumulator.
+    R1 -  8-bit register and main-memory address register.
+    R2 -  8-bit register and main-memory high data byte.
+    R3 -  8-bit register and main-memory low  data byte.
+    PC -  8-bit program counter.
+    IR - 16-bit instruction register.
+    ID -        combinatorial instruction decoder.
+    MM -        16-bit-wide x 256-address Main Memory.
+
+    the instruction words is sixteen bits long, and is comprised of
+    <15:13> = source resource.
+    <12:10> = destination resource.
+    <    9> = write-enable.
+    <    8> = program-counter-enable.
+    < 7: 0> = immediate data.
+
+    the registers (U00 through U05) have a iSel input which define the source.
+    the instruction decoder (U06) enables the loading of the destinations.
+
+    the SPI shadow registers (U19-U25) monitor the CPU state, and can
+    control the CPU state by asserting U19's bits 1 and 2.
+
+    U08 provides a shadow register load-enable pulse which
+        begins at the falling edge of a CPU clock and ends at
+        the falling edge of the next SPI clock, allowing the shadow
+            registers the ability to capture the state of the CPU.
+
+    U30 routes internal nets out to the green LED bank according
+        to the setting of switches SW<3:0>.
+
+-------------------------------------notes------//------------------------------
+
+    fpga board pin assignments.
+
+
+    project:
+    MOSI    P17
+    MISO    D15
+    SPIclk  E20
+    CPUclk  E14
+
+
+    key3    T21
+    key2    T22
+    key1    R21
+    key0    R22 iRstn
+
+    sw9 L2
+    sw8 M1
+    sw7 M2
+    sw6 U11
+    sw5 U12
+    sw4 W12
+    sw3 V12
+    sw2 M22
+    sw1 L21
+    sw0 L22
+
+    ledr9   R17
+    ledr8   R18
+    ledr7   U18
+    ledr6   Y18
+    ledr5   V19
+    ledr4   T18
+    ledr3   Y19
+    ledr2   U19
+    ledr1   R19
+    ledr0   R20
+
+    ledg7   Y21
+    ledg6   Y22
+    ledg5   W21
+    ledg4   W22
+    ledg3   V21
+    ledg2   V22
+    ledg1   U21
+    ledg0   U22
+------------------------------------defines-----//----------------------------*/
+/*-----------------------------------ports------//----------------------------*/
+    input           iMOSI;          // SPI input.
+    output          oMISO;          // SPI output.
+    input           iSPIclk;        // SPI clock.
+    input           iCPUclk;        // CPU clock.
+    input   [ 3:0]  iKEY;           // keypress.
+    input   [ 9:0]  iSW;            // slide-switches.
+    output  [ 9:0]  oLEDR;          // red   LED bank.
+    output  [ 7:0]  oLEDG;          // green LED bank.
+    output          oDummyLoad;     // anti-optimization.
+/*-----------------------------------wires------//----------------------------*/
+    wire            iMOSI;          // SPI input.
+    wire            oMISO;          // SPI output.
+    wire            iSPIclk;        // SPI clock.
+    wire            iCPUclk;        // CPU clock.
+    wire    [ 3:0]  iKEY;           // keypress.
+    wire    [ 9:0]  iSW;            // slide-switches.
+    wire    [ 9:0]  oLEDR;          // red   LED bank.
+    wire    [ 7:0]  oLEDG;          // green LED bank.
+
+    wire            wCEPC;          // program counter count-enable.
+    wire    [15:0]  wIR;            // instruction register.
+    wire            wLEIR;          // instruction register load-enable.
+    wire            wLEPC;          // program counter load-enable.
+    wire            wLER0;          // R0 load-enable.
+    wire            wLER1;          // R1 load-enable.
+    wire            wLER2;          // R2 load-enable.
+    wire            wLER3;          // R3 load-enable.
+    wire    [15:0]  wMMD;           // main-memory data-out.
+    wire    [15:0]  wMMI;           // main-memory instruction-out.
+    wire    [ 7:0]  wPC;            // program-counter.
+    wire    [ 7:0]  wR0;            // R0.
+    wire    [ 7:0]  wR1;            // R1.
+    wire    [ 7:0]  wR2;            // R2.
+    wire    [ 7:0]  wR3;            // R3.
+    wire            wRstn;          // system reset.
+    wire    [ 2:0]  wSel;           // common data-in selector.
+    wire    [ 7:0]  wShadow0;       // R0 shadow register.
+    wire    [ 7:0]  wShadow1;       // R1 shadow register.
+    wire    [ 7:0]  wShadow2;       // R2 shadow register.
+    wire    [ 7:0]  wShadow3;       // R3 shadow register.
+    wire    [15:0]  wShadowIR;      // instruction register shadow.
+    wire    [ 7:0]  wShadowPC;      // program counter shadow.
+    wire            wSIR;           // instruction register shadow shift-up.
+    wire            wSPC;           // program counter shadow shift-up.
+    wire            wSR0;           // R0 shadow shift-up.
+    wire            wSR1;           // R1 shadow shift-up.
+    wire            wSR2;           // R2 shadow shift-up.
+    wire            wSR3;           // R3 shadow shift-up.
+    wire            wWE;            // write-enable pulse.
+    wire    [ 7:0]  wImmediate;     // immediate data.
+    wire    [ 7:0]  wSpiControl;        // from spi control register.
+    wire            wSquelch;       // from spi control register.
+    wire            wBypassIR;      // from spi control register.
+    wire            wLoadShadows;       // shadow registers parallel load.
+
+                        // not currently used.
+    wire    [ 7:0]  wGreenLEDBus7;      // green LED bus.
+    wire    [ 7:0]  wGreenLEDBus6;      // green LED bus.
+    wire    [ 7:0]  wGreenLEDBus5;      // green LED bus.
+    wire    [ 7:0]  wGreenLEDBus4;      // green LED bus.
+    wire    [ 7:0]  wGreenLEDBus3;      // green LED bus.
+    wire    [ 7:0]  wGreenLEDBus2;      // green LED bus.
+    wire    [ 7:0]  wGreenLEDBus1;      // green LED bus.
+    wire    [ 7:0]  wGreenLEDBus0;      // green LED bus.
+    wire            oDummyLoad;     // anti-optimization.
+    wire    [ 3:0]  wTrigger;       // trigger control.
+/*---------------------------------registers----//----------------------------*/
+/*---------------------------------variables----//----------------------------*/
+/*---------------------------------parameters---//----------------------------*/
+/*-----------------------------------clocks-----//----------------------------*/
+/*---------------------------------instances----//----------------------------*/
+
+//---   begin regular CPU section.
+
+
+    reg_08 U00_R0               // CPU R0.      
+        (
+         .oParallel   (wR0),
+         .iParallel7  (wShadow0),
+         .iParallel6  (wR1 + wR2),      // adder.
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR0),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),            // needed for zero vector no-op.
+     .iSel        (wSel),
+     .oSerial     (),
+     .iSerial     (1'b0),
+     .iLoadEnable (wLER0),
+     .iShiftEnable(1'b0),
+     .iResetN     (wRstn),
+     .iClk        (iCPUclk)
+        );
+
+
+
+    reg_08 U01_R1               // CPU R1.      
+        (
+         .oParallel   (wR1),
+         .iParallel7  (wShadow1),
+         .iParallel6  (wMMD[7:0]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR1),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+     .iSel        (wSel),
+     .oSerial     (),
+     .iSerial     (1'b0),
+     .iLoadEnable (wLER1),
+     .iShiftEnable(1'b0),
+     .iResetN     (wRstn),
+     .iClk        (iCPUclk)
+        );
+
+
+
+    reg_08 U02_R2               // CPU R2.      
+        (
+         .oParallel   (wR2),
+         .iParallel7  (wShadow2),
+         .iParallel6  (wMMD[15:8]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR2),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+     .iSel        (wSel),
+     .oSerial     (),
+     .iSerial     (1'b0),
+     .iLoadEnable (wLER2),
+     .iShiftEnable(1'b0),
+     .iResetN     (wRstn),
+     .iClk        (iCPUclk)
+        );
+
+
+    reg_08 U03_R3               // CPU R3.      
+        (
+         .oParallel   (wR3),
+         .iParallel7  (wShadow3),
+         .iParallel6  (wMMD[7:0]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wR3),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+     .iSel        (wSel),
+     .oSerial     (),
+     .iSerial     (1'b0),
+     .iLoadEnable (wLER3),
+     .iShiftEnable(1'b0),
+     .iResetN     (wRstn),
+     .iClk        (iCPUclk)
+        );
+
+
+
+    counter_08 U04_PC           // CPU program counter.
+        (
+         .oCount      (wPC),
+         .iParallel7  (wShadowPC),
+         .iParallel6  (wMMD[7:0]),
+         .iParallel5  (wImmediate),
+         .iParallel4  (wPC),
+         .iParallel3  (wR3),
+         .iParallel2  (wR2),
+         .iParallel1  (wR1),
+         .iParallel0  (wR0),
+     .iSel        (wSel),
+     .oSerial     (),
+     .iSerial     (1'b0),
+     .iLoadEnable (wLEPC),
+     .iShiftEnable(1'b0),
+     .iCountEnable(wCEPC),
+     .iResetN     (wRstn),
+     .iClk        (iCPUclk)
+        );
+
+
+    reg_16 U05_IR               // CPU instruction register.
+        (
+         .oParallel   (wIR),            // IR state.
+         .iParallel1  (wShadowIR),      // IR shadow state.
+         .iParallel0  (wMMI),           // MM output.
+     .iSel        (wSpiControl[2]),     // special control.
+     .oSerial     (),
+     .iSerial     (1'b0),
+     .iLoadEnable (wLEIR),
+     .iShiftEnable(1'b0),
+     .iResetN     (wRstn),
+     .iClk        (iCPUclk)
+        );
+
+
+    instruction_decoder U06_ID      // instruction decoder.
+        (
+     .iSquelch  (wSquelch),         // squelch when writing to IR.
+     .iIR       (wIR),          // instruction register.
+     .iBypass   (wShadowIR),        // IR bypass from SPI.
+     .iBypassIR (wBypassIR),        // bypass the IR.
+     .oSel      (wSel),         // common data-in selector.
+     .oLER0     (wLER0),            // R0 load-enable.
+     .oLER1     (wLER1),            // R1 load-enable.
+     .oLER2     (wLER2),            // R2 load-enable.
+     .oLER3     (wLER3),            // R3 load-enable.
+     .oLEPC     (wLEPC),            // PC load-enable.
+     .oWE       (wWE),          // write-enable pulse.
+     .oCEPC     (wCEPC),            // PC count-enable.
+     .oImmediate(wImmediate)        // immediate data.
+        );
+
+
+
+                        // main memory:
+                        // the program counter reads from read-port-0.
+                        // the R2:R1 port reads from read-port-1.
+                        // the R2:R1 port writes to the write port.
+                        // the R2:R1 port reads/writes using address from R3.
+
+
+    main_memory U07_MM          // main-memory.
+        (
+     .iReadAddress1(wR3),           // from R3.
+     .iReadAddress0(wPC),           // from PC
+     .iWriteAddress(wR3),           // from R3
+     .oReadData1   (wMMD),          // to <R2:R1>
+     .oReadData0   (wMMI),          // to IR.
+     .iWriteData   ({wR2,wR1}),     // from <R2:R1>.
+     .iWE          (wWE),           // from the instruction decoder.
+     .iCPUclk      (iCPUclk)
+        );
+
+
+                        // load shadow-registers upon rising
+                        // edge of first SPI clock following
+                        // the falling edge of a CPU clock.
+    shadow_load_control U08_shadow_load // shadow-register load control.
+        (
+     .iCPUclk(iCPUclk),
+     .iSPIclk(iSPIclk),
+     .iRstn(wRstn), 
+     .oLoadEnable(wLoadShadows)
+        );
+
+
+//---   begin SPI shadow-scan section.
+
+
+                        // the SPI scan registers are generally
+                        // given the term 'shadow registers'.
+
+
+    scan_08 U19_spi_control         // top of SPI scan chain, used for control.
+        (
+         .oParallel   (wSpiControl),        // green LED select 7.
+         .iParallel   (wSpiControl),        // self-refresh.
+     .oSerial     (oMISO),
+     .iSerial     (wSR0),
+     .iLoadEnable (wLoadShadows),
+     .iShiftEnable(1'b1),
+     .iResetN     (wRstn),
+     .iClk        (iSPIclk)
+        );
+
+
+
+    scan_08 U20_shadowR0            // R0 shadow register.
+        (
+         .oParallel   (wShadow0),       // green LED select 6.
+         .iParallel   (wR0),
+     .oSerial     (wSR0),
+     .iSerial     (wSR1),
+     .iLoadEnable (wLoadShadows),
+     .iShiftEnable(1'b1),
+     .iResetN     (wRstn),
+     .iClk        (iSPIclk)
+        );
+
+    scan_08 U21_shadowR1            // R1 shadow register.
+        (
+         .oParallel   (wShadow1),       // green LED select 5.
+         .iParallel   (wR1),
+     .oSerial     (wSR1),
+     .iSerial     (wSR2),
+     .iLoadEnable (wLoadShadows),
+     .iShiftEnable(1'b1),
+     .iResetN     (wRstn),
+     .iClk        (iSPIclk)
+        );
+
+    scan_08 U22_shadowR2            // R2 shadow register.
+        (
+         .oParallel   (wShadow2),       // green LED select 4.
+         .iParallel   (wR2),
+     .oSerial     (wSR2),
+     .iSerial     (wSR3),
+     .iLoadEnable (wLoadShadows),
+     .iShiftEnable(1'b1),
+     .iResetN     (wRstn),
+     .iClk        (iSPIclk)
+        );
+
+    scan_08 U23_shadowR3            // R3 shadow register.
+        (
+         .oParallel   (wShadow3),       // green LED select 3.
+         .iParallel   (wR3),
+     .oSerial     (wSR3),
+     .iSerial     (wSPC),
+     .iLoadEnable (wLoadShadows),
+     .iShiftEnable(1'b1),
+     .iResetN     (wRstn),
+     .iClk        (iSPIclk)
+        );
+
+    scan_08 U24_shadowPC            // program-counter shadow register.
+        (
+         .oParallel   (wShadowPC),      // green LED select 2.
+         .iParallel   (wPC),
+     .oSerial     (wSPC),
+     .iSerial     (wSIR),
+     .iLoadEnable (wLoadShadows),
+     .iShiftEnable(1'b1),
+     .iResetN     (wRstn),
+     .iClk        (iSPIclk)
+        );
+
+    scan_16 U25_shadowIR            // instruction-register shadow register.
+        (
+         .oParallel   (wShadowIR),      // green LED select 1,0.
+         .iParallel   (wIR),
+     .oSerial     (wSIR),
+     .iSerial     (iMOSI),
+     .iLoadEnable (wLoadShadows),
+     .iShiftEnable(1'b1),
+     .iResetN     (wRstn),
+     .iClk        (iSPIclk)
+        );
+
+
+
+//---   begin green LED signal-monitoring section.
+
+
+
+    mux8x16 U30_green_led_mux       // green LED diagnostic mux.
+        (
+     .iDin15({wLER0,wLER1,wLER2,wLER3,wLEPC,wLEIR,wWE,wCEPC}),
+     .iDin14(wIR[15:8]),            // IR-H.
+     .iDin13(wIR[7:0]),         // IR-L.
+     .iDin12(wPC),              // PC.
+     .iDin11(wR3),              // R3.
+     .iDin10(wR2),              // R2.
+     .iDin9 (wR1),              // R1.
+     .iDin8 (wR0),              // R0.
+     .iDin7 (wSpiControl),          // SPI control.
+     .iDin6 (wShadowIR[15:8]),      // IR-H shadow.
+     .iDin5 (wShadowIR[7:0]),       // IR-L shadow.
+     .iDin4 (wShadowPC),            // PC   shadow.
+     .iDin3 (wShadow3),         // R3   shadow.
+     .iDin2 (wShadow2),         // R2   shadow.
+     .iDin1 (wShadow1),         // R1   shadow.
+     .iDin0 (wShadow0),         // R0   shadow.
+     .iSel  (iSW[3:0]),         // mux-select.
+     .oDout (oLEDG)             // to green LED bank.
+        );
+/*-----------------------------------logic------//----------------------------*/
+    assign wRstn     = iKEY[0];     // pushbutton system reset.
+    assign wSquelch  = wSpiControl[2];  // for python squelching ins. decode.
+    assign wBypassIR = wSpiControl[1];  // for python controlling CPU.
+    assign wTrigger  = wSpiControl[7:4];    // for signaltap triggering, not used.
+
+                        // load instruction register
+                        // if neither or both shadow
+                        // control signals asserted.
+    assign wLEIR     = !(wSquelch ^ wBypassIR);
+
+
+    assign oLEDR[9]  = 1'b0;        // red LED hookup.
+    assign oLEDR[8]  = 1'b0;
+    assign oLEDR[7]  = wSel[2];
+    assign oLEDR[6]  = wSel[1];
+    assign oLEDR[5]  = wSel[0];
+    assign oLEDR[4]  = wRstn;
+    assign oLEDR[3]  = iCPUclk;
+    assign oLEDR[2]  = oMISO;
+    assign oLEDR[1]  = iMOSI;
+    assign oLEDR[0]  = iSPIclk;
+
+
+                        // signals not to be optimized
+                        // out, place here.
+    assign oDummyLoad = (|wShadowIR) | wSIR | (|wSpiControl) | (|wTrigger);
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/instruction_decoder.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,185 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module instruction_decoder
+        (
+      iSquelch,             // disrupt output enables.
+      iIR,                  // instruction register.
+      iBypass,              // instruction from SPI.
+      iBypassIR,                // override the IR.
+      oSel,                 // common data-in selector.
+      oLER0,                // R0 load-enable.
+      oLER1,                // R1 load-enable.
+      oLER2,                // R2 load-enable.
+      oLER3,                // R3 load-enable.
+      oLEPC,                // PC load-enable.
+      oWE,                  // write-enable pulse.
+      oCEPC,                // PC count-enable.
+      oImmediate                // immediate data.
+        );
+/*--------------------------------description-----------------------------------
+    the instruction decoder.  
+-------------------------------------notes--------------------------------------
+    this instruction decoder operates in three different 'modes'.
+    1. nominal mode: the instruction word is decoded as per the CPU spec.
+    2. regular test mode: the instruction register is ignored, and instead
+           this decoder makes use of iBypass, which is the instruction pattern
+           provided by the instruction word shadow register (which is part of
+           the spi scan chain).  this allows the python code to take over the
+           operation of the CPU.
+    3. IR-write test mode: a special-case mode which occurs when python
+           writes to the instruction register.  in this case, the outputs of
+       this decoder which are used to provide load-enables to CPU 
+       resources, must be squelched.  this is because we don't want the
+           python-written instruction register content to be decoded and
+       the decoded signals sent into the CPU.  why?  because most likely
+           the python-write to the IR is only to check that it can be done,
+           and if the result of such a write were allowed to propagate, then
+           the other registers may be arbitrarily updated, confusing the
+           user at the python end.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input           iSquelch;       // disrupt output enables.
+    input   [15:0]  iIR;            // instruction register.
+    input   [15:0]  iBypass;        // instruction from SPI.
+    input           iBypassIR;      // override the IR.
+    output  [ 2:0]  oSel;           // common data-in selector.
+    output          oLER0;          // R0 load-enable.
+    output          oLER1;          // R1 load-enable.
+    output          oLER2;          // R2 load-enable.
+    output          oLER3;          // R3 load-enable.
+    output          oLEPC;          // PC load-enable.
+    output          oWE;            // write-enable pulse.
+    output          oCEPC;          // PC count-enable.
+    output  [ 7:0]  oImmediate;     // immediate data.
+/*-----------------------------------wires------------------------------------*/
+    wire            iSquelch;       // disrupt output enables.
+    wire    [15:0]  iIR;            // instruction register.
+    wire    [15:0]  iBypass;        // instruction from SPI.
+    wire            iBypassIR;      // override the IR.
+    wire    [ 2:0]  oSel;           // common data-in selector.
+    wire            oLER0;          // R0 load-enable.
+    wire            oLER1;          // R1 load-enable.
+    wire            oLER2;          // R2 load-enable.
+    wire            oLER3;          // R3 load-enable.
+    wire            oLEPC;          // PC load-enable.
+    wire            oWE;            // write-enable pulse.
+    wire            oCEPC;          // PC count-enable.
+    wire    [ 7:0]  oImmediate;     // immediate data.
+/*---------------------------------registers----------------------------------*/
+    reg     [15:0]  rIR;            // instruction.
+    reg             rLER0;          // R0 load-enable.
+    reg             rLER1;          // R1 load-enable.
+    reg             rLER2;          // R2 load-enable.
+    reg             rLER3;          // R3 load-enable.
+    reg             rLEPC;          // PC load-enable.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+
+
+    always @ (rIR)
+    case     (rIR[12:10])           // decode the load-enables.
+
+      7 : begin             // no register.
+            rLER0  = 1'b0;
+            rLER1  = 1'b0;
+            rLER2  = 1'b0;
+            rLER3  = 1'b0;
+            rLEPC  = 1'b0;
+              end
+
+      6 : begin             // no register.
+            rLER0  = 1'b0;
+            rLER1  = 1'b0;
+            rLER2  = 1'b0;
+            rLER3  = 1'b0;
+            rLEPC  = 1'b0;  
+              end
+
+      5 : begin             // no register.
+            rLER0  = 1'b0;
+            rLER1  = 1'b0;
+            rLER2  = 1'b0;
+            rLER3  = 1'b0;
+            rLEPC  = 1'b0;      
+              end
+
+      4 : begin             // PC
+            rLER0  = 1'b0;
+            rLER1  = 1'b0;
+            rLER2  = 1'b0;
+            rLER3  = 1'b0;
+            rLEPC  = 1'b1;          
+              end
+
+      3 : begin             // R3
+            rLER0  = 1'b0;
+            rLER1  = 1'b0;
+            rLER2  = 1'b0;
+            rLER3  = 1'b1;          
+            rLEPC  = 1'b0;
+              end
+
+      2 : begin             // R2
+            rLER0  = 1'b0;
+            rLER1  = 1'b0;
+            rLER2  = 1'b1;          
+            rLER3  = 1'b0;
+            rLEPC  = 1'b0;
+              end
+
+      1 : begin             // R1
+            rLER0  = 1'b0;
+            rLER1  = 1'b1;          
+            rLER2  = 1'b0;
+            rLER3  = 1'b0;
+            rLEPC  = 1'b0;
+              end
+
+      0 : begin             // R0
+            rLER0  = 1'b1;          
+            rLER1  = 1'b0;
+            rLER2  = 1'b0;
+            rLER3  = 1'b0;
+            rLEPC  = 1'b0;
+              end
+
+     
+    endcase
+
+    assign oSel       = rIR[15:13];     // pass-through.
+    assign oLER0      = rLER0 & !iSquelch;  // decode iIR[12:10].
+    assign oLER1      = rLER1 & !iSquelch;  // decode iIR[12:10].
+    assign oLER2      = rLER2 & !iSquelch;  // decode iIR[12:10].
+    assign oLER3      = rLER3 & !iSquelch;  // decode iIR[12:10].
+    assign oLEPC      = rLEPC & !iSquelch;  // decode iIR[12:10].
+    assign oWE        = rIR[9] & !iSquelch; // pass-through.
+    assign oCEPC      = rIR[8] & !iSquelch; // pass-through.
+    assign oImmediate = rIR[7:0];       // pass-through.
+
+
+    always @ (iIR or iBypass or iBypassIR)
+    if (iBypassIR) rIR = iBypass;
+    else rIR = iIR;
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/main_memory.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,74 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module main_memory
+        (
+     iReadAddress1,             // read-address 1.
+     iReadAddress0,             // read-address 0.
+     iWriteAddress,             // write-address.
+     oReadData1,                // read-data 1.
+     oReadData0,                // read-data 0.
+     iWriteData,                // write-data.
+     iWE,                   // write-enable.
+     iCPUclk                // cpu clock.
+        );
+/*--------------------------------description-----------------------------------
+    CPU main memory.
+    two read-ports, one write-port.
+-------------------------------------notes--------------------------------------
+    level-sensitive write-enable.
+    the memory needs to be sixteen bits wide in order to hold
+    immediate data for the instruction set.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input   [ 7:0]  iReadAddress1;      // read-address 1.
+    input   [ 7:0]  iReadAddress0;      // read-address 0.
+    input   [ 7:0]  iWriteAddress;      // write-address.
+    output  [15:0]  oReadData1;     // read-data 1.
+    output  [15:0]  oReadData0;     // read-data 0.
+    input   [15:0]  iWriteData;     // write-data.
+    input           iWE;            // write-enable.
+    input           iCPUclk;        // cpu clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [ 7:0]  iReadAddress1;      // read-address 1.
+    wire    [ 7:0]  iReadAddress0;      // read-address 0.
+    wire    [ 7:0]  iWriteAddress;      // write-address.
+    wire    [15:0]  oReadData1;     // read-data 1.
+    wire    [15:0]  oReadData0;     // read-data 0.
+    wire    [15:0]  iWriteData;     // write-data.
+    wire            iWE;            // write-enable.
+    wire            iCPUclk;        // cpu clock.
+/*---------------------------------registers----------------------------------*/
+    reg     [15:0] mem_bank [0:255];    // memory bank.
+    reg     [15:0] rData1;          // data-out-1 register.
+    reg     [15:0] rData0;          // data-out-0 register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iCPUclk) 
+    if (iWE) mem_bank[iWriteAddress] = iWriteData;
+    else     mem_bank[iWriteAddress] = mem_bank[iWriteAddress];
+
+    assign oReadData1 = mem_bank[iReadAddress1];
+    assign oReadData0 = mem_bank[iReadAddress0];
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/mux16x2.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,57 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module mux16x2
+        (
+      iDin1,                // data-input 1.
+      iDin0,                // data-input 0.
+      iSel,                 // multiplexor select.
+      oDout                 // data-out.
+        );
+/*--------------------------------description-----------------------------------
+    a 16-bit-wide, 2-selection multiplexor.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input   [15:0]  iDin1;          // data-input 1.
+    input   [15:0]  iDin0;          // data-input 0.
+    input           iSel;           // multiplexor select.
+    output  [15:0]  oDout;          // data-out.
+/*-----------------------------------wires------------------------------------*/
+    wire    [15:0]  iDin1;          // data-input 1.
+    wire    [15:0]  iDin0;          // data-input 0.
+    wire            iSel;           // multiplexor select.
+    wire    [15:0]  oDout;          // data-out.
+/*---------------------------------registers----------------------------------*/
+    reg     [15:0]  rDout;          // output register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (iDin1 or iDin0 or iSel)
+    case (iSel)
+    1 : rDout = iDin1;
+    0 : rDout = iDin0;
+    endcase
+
+    assign oDout = rDout;           // propagate output.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/mux8x16.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,117 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module mux8x16
+        (
+      iDin15,               // data-input 15.
+      iDin14,               // data-input 14.
+      iDin13,               // data-input 13.
+      iDin12,               // data-input 12.
+      iDin11,               // data-input 11.
+      iDin10,               // data-input 10.
+      iDin9,                // data-input 9.
+      iDin8,                // data-input 8.
+      iDin7,                // data-input 7.
+      iDin6,                // data-input 6.
+      iDin5,                // data-input 5.
+      iDin4,                // data-input 4.
+      iDin3,                // data-input 3.
+      iDin2,                // data-input 2.
+      iDin1,                // data-input 1.
+      iDin0,                // data-input 0.
+      iSel,                 // multiplexor select.
+      oDout                 // data-out.
+        );
+/*--------------------------------description-----------------------------------
+    a 8-bit-wide, 16-selection multiplexor.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input   [ 7:0]  iDin15;         // data-input 15.
+    input   [ 7:0]  iDin14;         // data-input 14.
+    input   [ 7:0]  iDin13;         // data-input 13.
+    input   [ 7:0]  iDin12;         // data-input 12.
+    input   [ 7:0]  iDin11;         // data-input 11.
+    input   [ 7:0]  iDin10;         // data-input 10.
+    input   [ 7:0]  iDin9;          // data-input 9.
+    input   [ 7:0]  iDin8;          // data-input 8.
+    input   [ 7:0]  iDin7;          // data-input 7.
+    input   [ 7:0]  iDin6;          // data-input 6.
+    input   [ 7:0]  iDin5;          // data-input 5.
+    input   [ 7:0]  iDin4;          // data-input 4.
+    input   [ 7:0]  iDin3;          // data-input 3.
+    input   [ 7:0]  iDin2;          // data-input 2.
+    input   [ 7:0]  iDin1;          // data-input 1.
+    input   [ 7:0]  iDin0;          // data-input 0.
+    input   [ 3:0]  iSel;           // multiplexor select.
+    output  [ 7:0]  oDout;          // data-out.
+/*-----------------------------------wires------------------------------------*/
+    wire    [ 7:0]  iDin15;         // data-input 15.
+    wire    [ 7:0]  iDin14;         // data-input 14.
+    wire    [ 7:0]  iDin13;         // data-input 13.
+    wire    [ 7:0]  iDin12;         // data-input 12.
+    wire    [ 7:0]  iDin11;         // data-input 11.
+    wire    [ 7:0]  iDin10;         // data-input 10.
+    wire    [ 7:0]  iDin9;          // data-input 9.
+    wire    [ 7:0]  iDin8;          // data-input 8.
+    wire    [ 7:0]  iDin7;          // data-input 7.
+    wire    [ 7:0]  iDin6;          // data-input 6.
+    wire    [ 7:0]  iDin5;          // data-input 5.
+    wire    [ 7:0]  iDin4;          // data-input 4.
+    wire    [ 7:0]  iDin3;          // data-input 3.
+    wire    [ 7:0]  iDin2;          // data-input 2.
+    wire    [ 7:0]  iDin1;          // data-input 1.
+    wire    [ 7:0]  iDin0;          // data-input 0.
+    wire    [ 3:0]  iSel;           // multiplexor select.
+    wire    [ 7:0]  oDout;          // data-out.
+/*---------------------------------registers----------------------------------*/
+    reg     [ 7:0]  rDout;          // output register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+
+    always @ (iDin15 or iDin14 or iDin13 or iDin12 or
+                  iDin11 or iDin10 or iDin9  or iDin8  or
+          iDin7  or iDin6  or iDin5  or iDin4  or
+          iDin3  or iDin2  or iDin1  or iDin0  or iSel)
+    case (iSel)
+    15 : rDout = iDin15;
+    14 : rDout = iDin14;
+    13 : rDout = iDin13;
+    12 : rDout = iDin12;
+    11 : rDout = iDin11;
+    10 : rDout = iDin10;
+     9 : rDout = iDin9;
+     8 : rDout = iDin8;
+     7 : rDout = iDin7;
+     6 : rDout = iDin6;
+     5 : rDout = iDin5;
+     4 : rDout = iDin4;
+     3 : rDout = iDin3;
+     2 : rDout = iDin2;
+     1 : rDout = iDin1;
+     0 : rDout = iDin0;
+    endcase
+
+    assign oDout = rDout;           // propagate output.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/mux8x8.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,82 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module mux8x8
+        (
+      iDin7,                // data-input 7.
+      iDin6,                // data-input 6.
+      iDin5,                // data-input 5.
+      iDin4,                // data-input 4.
+      iDin3,                // data-input 3.
+      iDin2,                // data-input 2.
+      iDin1,                // data-input 1.
+      iDin0,                // data-input 0.
+      iSel,                 // multiplexor select.
+      oDout                 // data-out.
+        );
+/*--------------------------------description-----------------------------------
+    an 8-bit-wide, 8-selection multiplexor.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input   [ 7:0]  iDin7;          // data-input 7.
+    input   [ 7:0]  iDin6;          // data-input 6.
+    input   [ 7:0]  iDin5;          // data-input 5.
+    input   [ 7:0]  iDin4;          // data-input 4.
+    input   [ 7:0]  iDin3;          // data-input 3.
+    input   [ 7:0]  iDin2;          // data-input 2.
+    input   [ 7:0]  iDin1;          // data-input 1.
+    input   [ 7:0]  iDin0;          // data-input 0.
+    input   [ 2:0]  iSel;           // multiplexor select.
+    output  [ 7:0]  oDout;          // data-out.
+/*-----------------------------------wires------------------------------------*/
+    wire    [ 7:0]  iDin7;          // data-input 7.
+    wire    [ 7:0]  iDin6;          // data-input 6.
+    wire    [ 7:0]  iDin5;          // data-input 5.
+    wire    [ 7:0]  iDin4;          // data-input 4.
+    wire    [ 7:0]  iDin3;          // data-input 3.
+    wire    [ 7:0]  iDin2;          // data-input 2.
+    wire    [ 7:0]  iDin1;          // data-input 1.
+    wire    [ 7:0]  iDin0;          // data-input 0.
+    wire    [ 2:0]  iSel;           // multiplexor select.
+    wire    [ 7:0]  oDout;          // data-out.
+/*---------------------------------registers----------------------------------*/
+    reg     [ 7:0]  rDout;          // output register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (iDin7 or iDin6 or iDin5 or iDin4 or
+                  iDin3 or iDin2 or iDin1 or iDin0 or iSel)
+    case (iSel)
+    7 : rDout = iDin7;
+    6 : rDout = iDin6;
+    5 : rDout = iDin5;
+    4 : rDout = iDin4;
+    3 : rDout = iDin3;
+    2 : rDout = iDin2;
+    1 : rDout = iDin1;
+    0 : rDout = iDin0;
+    endcase
+
+    assign oDout = rDout;           // propagate output.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/reg_08.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,111 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module reg_08
+        (
+         oParallel,             // parallel-output data.
+         iParallel7,                // parallel-input  data.
+         iParallel6,                // parallel-input  data.
+         iParallel5,                // parallel-input  data.
+         iParallel4,                // parallel-input  data.
+         iParallel3,                // parallel-input  data.
+         iParallel2,                // parallel-input  data.
+         iParallel1,                // parallel-input  data.
+         iParallel0,                // parallel-input  data.
+     iSel,                  // select the parallel input.
+     oSerial,               // serial-output data.
+     iSerial,               // serial-input data.
+     iLoadEnable,               // parallel-load-enable.
+     iShiftEnable,              // serial-shift-enable.
+     iResetN,               // synchronous reset*.
+     iClk                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+    an 8-bit parallel shift-register with 8 selectable input buses.
+-------------------------------------notes--------------------------------------
+    shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    output  [ 7:0]  oParallel;      // parallel-output data.
+    input   [ 7:0]  iParallel7;     // parallel-input  data.
+    input   [ 7:0]  iParallel6;     // parallel-input  data.
+    input   [ 7:0]  iParallel5;     // parallel-input  data.
+    input   [ 7:0]  iParallel4;     // parallel-input  data.
+    input   [ 7:0]  iParallel3;     // parallel-input  data.
+    input   [ 7:0]  iParallel2;     // parallel-input  data.
+    input   [ 7:0]  iParallel1;     // parallel-input  data.
+    input   [ 7:0]  iParallel0;     // parallel-input  data.
+    input   [ 2:0]  iSel;           // select the parallel input.
+    output          oSerial;        // serial-output data.
+    input           iSerial;        // serial-input data.
+    input           iLoadEnable;        // parallel-load-enable.
+    input           iShiftEnable;       // serial-shift-enable.
+    input           iResetN;        // synchronous reset*.
+    input           iClk;           // module clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [ 7:0]  oParallel;      // parallel-output data.
+    wire    [ 7:0]  iParallel7;     // parallel-input  data.
+    wire    [ 7:0]  iParallel6;     // parallel-input  data.
+    wire    [ 7:0]  iParallel5;     // parallel-input  data.
+    wire    [ 7:0]  iParallel4;     // parallel-input  data.
+    wire    [ 7:0]  iParallel3;     // parallel-input  data.
+    wire    [ 7:0]  iParallel2;     // parallel-input  data.
+    wire    [ 7:0]  iParallel1;     // parallel-input  data.
+    wire    [ 7:0]  iParallel0;     // parallel-input  data.
+    wire    [ 2:0]  iSel;           // select the parallel input.
+    wire    [ 7:0]  wParallelIn;        // select the parallel input.
+    wire            oSerial;        // serial-output data.
+    wire            iSerial;        // serial-input data.
+    wire            iLoadEnable;        // parallel-load-enable.
+    wire            iShiftEnable;       // serial-shift-enable.
+    wire            iResetN;        // synchronous reset*.
+    wire            iClk;           // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rRegister;      // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+    mux8x8 U01_mux8x8           // data-input selection.
+        (
+     .iDin7(iParallel7),
+     .iDin6(iParallel6),
+     .iDin5(iParallel5),
+     .iDin4(iParallel4),
+     .iDin3(iParallel3),
+     .iDin2(iParallel2),
+     .iDin1(iParallel1),
+     .iDin0(iParallel0),
+     .iSel (iSel),
+     .oDout(wParallelIn)
+        );
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iClk or negedge iResetN)
+    begin
+           if (!iResetN)     rRegister <= 8'h00;
+      else if (iLoadEnable)  rRegister <= wParallelIn;
+      else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+      else                   rRegister <= rRegister;
+    end
+
+    assign oParallel = rRegister;       // propagate parallel-out.
+    assign oSerial   = rRegister[7];    // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/reg_16.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,71 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module reg_16
+        (
+         oParallel,             // parallel-output data.
+         iParallel1,                // parallel-input  data.
+         iParallel0,                // parallel-input  data.
+     iSel,                  // select the parallel input.
+     oSerial,               // serial-output data.
+     iSerial,               // serial-input data.
+     iLoadEnable,               // parallel-load-enable.
+     iShiftEnable,              // serial-shift-enable.
+     iResetN,               // synchronous reset*.
+     iClk                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+    a 16-bit parallel shift-register with 2 selectable input buses.
+-------------------------------------notes--------------------------------------
+    shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    output  [15:0]  oParallel;      // parallel-output data.
+    input   [15:0]  iParallel1;     // parallel-input  data.
+    input   [15:0]  iParallel0;     // parallel-input  data.
+    input           iSel;           // select the parallel input.
+    output          oSerial;        // serial-output data.
+    input           iSerial;        // serial-input data.
+    input           iLoadEnable;        // parallel-load-enable.
+    input           iShiftEnable;       // serial-shift-enable.
+    input           iResetN;        // synchronous reset*.
+    input           iClk;           // module clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [15:0]  oParallel;      // parallel-output data.
+    wire    [15:0]  iParallel1;     // parallel-input  data.
+    wire    [15:0]  iParallel0;     // parallel-input  data.
+    wire            iSel;           // select the parallel input.
+    wire    [15:0]  wParallelIn;        // select the parallel input.
+    wire            oSerial;        // serial-output data.
+    wire            iSerial;        // serial-input data.
+    wire            iLoadEnable;        // parallel-load-enable.
+    wire            iShiftEnable;       // serial-shift-enable.
+    wire            iResetN;        // synchronous reset*.
+    wire            iClk;           // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rRegister;      // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+    mux16x2 U0_mux16x2          // data-input selection.
+        (
+     .iDin1(iParallel1),
+     .iDin0(iParallel0),
+     .iSel (iSel),
+     .oDout(wParallelIn)
+        );
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iClk or negedge iResetN)
+    begin
+           if (!iResetN)     rRegister <= 16'h0000;
+      else if (iLoadEnable)  rRegister <= wParallelIn;
+      else if (iShiftEnable) rRegister <= {rRegister[14:0], iSerial};
+      else                   rRegister <= rRegister;
+    end
+
+    assign oParallel = rRegister;       // propagate parallel-out.
+    assign oSerial   = rRegister[15];   // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/scan_08.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,58 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module scan_08              // shadow register.
+        (
+         oParallel,             // parallel-output data.
+         iParallel,             // parallel-input  data.
+     oSerial,               // serial-output data.
+     iSerial,               // serial-input data.
+     iLoadEnable,               // parallel-load-enable.
+     iShiftEnable,              // serial-shift-enable.
+     iResetN,               // synchronous reset*.
+     iClk                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+    an 8-bit parallel shift-register.
+-------------------------------------notes--------------------------------------
+    shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    output  [ 7:0]  oParallel;      // parallel-output data.
+    input   [ 7:0]  iParallel;      // parallel-input  data.
+    output          oSerial;        // serial-output data.
+    input           iSerial;        // serial-input data.
+    input           iLoadEnable;        // parallel-load-enable.
+    input           iShiftEnable;       // serial-shift-enable.
+    input           iResetN;        // synchronous reset*.
+    input           iClk;           // module clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [ 7:0]  oParallel;      // parallel-output data.
+    wire    [ 7:0]  iParallel;      // parallel-input  data.
+    wire    [ 7:0]  wParallelIn;        // select the parallel input.
+    wire            oSerial;        // serial-output data.
+    wire            iSerial;        // serial-input data.
+    wire            iLoadEnable;        // parallel-load-enable.
+    wire            iShiftEnable;       // serial-shift-enable.
+    wire            iResetN;        // synchronous reset*.
+    wire            iClk;           // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [ 7:0]  rRegister;      // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iClk or negedge iResetN)
+    begin
+           if (!iResetN)     rRegister <= 8'h00;
+      else if (iLoadEnable)  rRegister <= iParallel;
+      else if (iShiftEnable) rRegister <= {rRegister[6:0], iSerial};
+      else                   rRegister <= rRegister;
+    end
+
+    assign oParallel = rRegister;       // propagate parallel-out.
+    assign oSerial   = rRegister[7];    // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/scan_16.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,74 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module scan_16              // shadow register.
+        (
+         oParallel,             // parallel-output data.
+         iParallel,             // parallel-input  data.
+     oSerial,               // serial-output data.
+     iSerial,               // serial-input data.
+     iLoadEnable,               // parallel-load-enable.
+     iShiftEnable,              // serial-shift-enable.
+     iResetN,               // synchronous reset*.
+     iClk                   // module clock.
+        );
+/*--------------------------------description-----------------------------------
+    a 16-bit parallel shift-register.
+-------------------------------------notes--------------------------------------
+    shifting is LSB->MSB.
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    output  [15:0]  oParallel;      // parallel-output data.
+    input   [15:0]  iParallel;      // parallel-input  data.
+    output          oSerial;        // serial-output data.
+    input           iSerial;        // serial-input data.
+    input           iLoadEnable;        // parallel-load-enable.
+    input           iShiftEnable;       // serial-shift-enable.
+    input           iResetN;        // synchronous reset*.
+    input           iClk;           // module clock.
+/*-----------------------------------wires------------------------------------*/
+    wire    [15:0]  oParallel;      // parallel-output data.
+    wire    [15:0]  iParallel;      // parallel-input  data.
+    wire    [15:0]  wParallelIn;        // select the parallel input.
+    wire            oSerial;        // serial-output data.
+    wire            iSerial;        // serial-input data.
+    wire            iLoadEnable;        // parallel-load-enable.
+    wire            iShiftEnable;       // serial-shift-enable.
+    wire            iResetN;        // synchronous reset*.
+    wire            iClk;           // module clock.
+/*---------------------------------registers----------------------------------*/
+        reg     [15:0]  rRegister;      // the register.
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (posedge iClk or negedge iResetN)
+    begin
+           if (!iResetN)     rRegister[15:0] <= 16'h0000;
+      else if (iLoadEnable)  rRegister[15:0] <= iParallel[15:0];
+      else if (iShiftEnable) rRegister[15:0] <= {rRegister[14:0], iSerial};
+      else                   rRegister[15:0] <= rRegister[15:0];
+    end
+
+    assign oParallel[15:0] = rRegister[15:0];       // propagate parallel-out.
+    assign oSerial   = rRegister[15];   // propagate serial-out.
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/mmRTL/shadow_load_control.txt	Sun Sep 01 02:53:39 2013 +0000
@@ -0,0 +1,65 @@
+/*----------------------------------copyright---------------------------------*/
+//  licensed for personal and academic use.
+//  commercial use must be approved by the account-holder of
+//  gated.clock@gmail.com
+/*-----------------------------------module-----------------------------------*/
+    module shadow_load_control
+        (
+      iCPUclk,
+      iSPIclk,
+      iRstn,                // direct clear.
+      oLoadEnable               // shadow registers load enable.
+        );
+/*--------------------------------description-----------------------------------
+    when the CPU clock goes low, the CPU state is stable, and its time
+    for the SPI shadow registers to do a parallel load of the CPU state,
+    so its time to turn on the load-enable signal.
+
+    when the first SPI clock goes high, the parallel load completes and
+    its time to turn off the load-enable signal.
+-------------------------------------notes--------------------------------------
+------------------------------------defines-----------------------------------*/
+/*-----------------------------------ports------------------------------------*/
+    input           iCPUclk;
+    input           iSPIclk;
+    input           iRstn;          // direct clear.
+    output          oLoadEnable;        // shadow registers load enable.
+/*-----------------------------------wires------------------------------------*/
+    wire            iCPUclk;
+    wire            iSPIclk;
+    wire            iRstn;          // direct clear.
+    wire            oLoadEnable;        // shadow registers load enable.
+
+    wire            wOrClock;       // OR the clocks.
+/*---------------------------------registers----------------------------------*/
+    reg            rRegister;
+/*---------------------------------variables----------------------------------*/
+/*---------------------------------parameters---------------------------------*/
+/*-----------------------------------clocks-----------------------------------*/
+/*---------------------------------instances----------------------------------*/
+/*-----------------------------------logic------------------------------------*/
+    always @ (negedge wOrClock or negedge iRstn)
+    begin
+           if (!iRstn   ) rRegister <= 1'b0;
+      else if (!wOrClock) rRegister <= !iSPIclk;
+    end
+
+    assign wOrClock    =  iCPUclk | iSPIclk;
+    assign oLoadEnable =  rRegister;
+/*-------------------------------*/endmodule/*--------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+