Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32L1/sleep.c@153:9398a535854b, 2016-12-22 (annotated)

Committer:
fwndz
Date:
Thu Dec 22 05:12:40 2016 +0000
Revision:
153:9398a535854b
Parent:
149:156823d33999 
device target maximize

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 *******************************************************************************
<> 144:ef7eb2e8f9f7 3 * Copyright (c) 2014, STMicroelectronics
<> 144:ef7eb2e8f9f7 4 * All rights reserved.
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 * Redistribution and use in source and binary forms, with or without
<> 144:ef7eb2e8f9f7 7 * modification, are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 10 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 12 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 13 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 15 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 16 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 28 *******************************************************************************
<> 144:ef7eb2e8f9f7 29 */
<> 144:ef7eb2e8f9f7 30 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 31 #include "hal_tick.h"
<> 148:21d94c44109e 32 #include "rtc_api_hal.h"
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #if DEVICE_SLEEP
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 static TIM_HandleTypeDef TimMasterHandle;
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 void sleep(void) {
<> 144:ef7eb2e8f9f7 41 // Stop HAL systick
<> 144:ef7eb2e8f9f7 42 HAL_SuspendTick();
<> 144:ef7eb2e8f9f7 43 // Request to enter SLEEP mode
<> 144:ef7eb2e8f9f7 44 HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
<> 144:ef7eb2e8f9f7 45 // Restart HAL systick
<> 144:ef7eb2e8f9f7 46 HAL_ResumeTick();
<> 144:ef7eb2e8f9f7 47 }
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 void deepsleep(void)
<> 144:ef7eb2e8f9f7 51 {
<> 144:ef7eb2e8f9f7 52 #if defined(TARGET_MOTE_L152RC)
<> 144:ef7eb2e8f9f7 53 int8_t STOPEntry = PWR_STOPENTRY_WFI;
<> 144:ef7eb2e8f9f7 54 #endif
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 // Stop HAL systick
<> 144:ef7eb2e8f9f7 57 TimMasterHandle.Instance = TIM_MST;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 #if defined(TARGET_MOTE_L152RC)
<> 144:ef7eb2e8f9f7 60 /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
<> 144:ef7eb2e8f9f7 61 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), PWR_LOWPOWERREGULATOR_ON);
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Set SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 64 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 /* Select Stop mode entry --------------------------------------------------*/
<> 144:ef7eb2e8f9f7 67 if(STOPEntry == PWR_STOPENTRY_WFI)
<> 144:ef7eb2e8f9f7 68 {
<> 144:ef7eb2e8f9f7 69 /* Request Wait For Interrupt */
<> 144:ef7eb2e8f9f7 70 __WFI();
<> 144:ef7eb2e8f9f7 71 }
<> 144:ef7eb2e8f9f7 72 else
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 /* Request Wait For Event */
<> 144:ef7eb2e8f9f7 75 __SEV();
<> 144:ef7eb2e8f9f7 76 __WFE();
<> 144:ef7eb2e8f9f7 77 __WFE();
<> 144:ef7eb2e8f9f7 78 }
<> 144:ef7eb2e8f9f7 79 __NOP();
<> 144:ef7eb2e8f9f7 80 __NOP();
<> 144:ef7eb2e8f9f7 81 __NOP();
<> 144:ef7eb2e8f9f7 82 /* Reset SLEEPDEEP bit of Cortex System Control Register */
<> 144:ef7eb2e8f9f7 83 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
<> 144:ef7eb2e8f9f7 84 #else
<> 144:ef7eb2e8f9f7 85 // Request to enter STOP mode with regulator in low power mode
<> 144:ef7eb2e8f9f7 86 HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
<> 144:ef7eb2e8f9f7 87 #endif
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // After wake-up from STOP reconfigure the PLL
<> 144:ef7eb2e8f9f7 90 SetSysClock();
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 // Restart HAL systick
<> 144:ef7eb2e8f9f7 93 HAL_ResumeTick();
<> 148:21d94c44109e 94
<> 148:21d94c44109e 95 #if DEVICE_LOWPOWERTIMER
<> 148:21d94c44109e 96 rtc_synchronize();
<> 148:21d94c44109e 97 #endif
<> 144:ef7eb2e8f9f7 98 }
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #endif