Fawwaz Nadzmy / mbed-STM

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_ONSEMI/TARGET_NCS36510/rtc.c@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
Parent:
149:156823d33999 
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 *******************************************************************************
<> 149:156823d33999 3 * @file rtc.c
<> 149:156823d33999 4 * @brief Implementation of a Rtc driver
<> 149:156823d33999 5 * @internal
<> 149:156823d33999 6 * @author ON Semiconductor
<> 149:156823d33999 7 * $Rev: 3525 $
<> 149:156823d33999 8 * $Date: 2015-07-20 15:24:25 +0530 (Mon, 20 Jul 2015) $
<> 149:156823d33999 9 ******************************************************************************
<> 149:156823d33999 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 149:156823d33999 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 149:156823d33999 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 149:156823d33999 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 149:156823d33999 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 149:156823d33999 15 * if applicable the software license agreement. Do not use this software and/or
<> 149:156823d33999 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 149:156823d33999 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 149:156823d33999 18 * terms and conditions.
<> 149:156823d33999 19 *
<> 149:156823d33999 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 149:156823d33999 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 25 * @endinternal
<> 149:156823d33999 26 *
<> 149:156823d33999 27 * @ingroup rtc
<> 149:156823d33999 28 *
<> 149:156823d33999 29 * @details
<> 149:156823d33999 30 * A real-time clock (RTC) is a computer clock ,that keeps track of the current time. The heart of the RTC is a series of
<> 149:156823d33999 31 * freely running counters one for each time unit, The series of counters is linked as follows: a roll over event of
<> 149:156823d33999 32 * the seconds counter produces a minutes enable pulse; a roll over event of the minutes counter produces an hours
<> 149:156823d33999 33 * enable pulse, etc.Note that all Counter registers are in an undefined state on power-up.
<> 149:156823d33999 34 * Use the Reset bit in the Control Register to reset the counters to their default values.
<> 149:156823d33999 35 * DIVISOR is the register containing the value to divide the clock frequency to produce 1Hz strobe ; 1Hz strobe is used
<> 149:156823d33999 36 * internally to time the incrementing of the Seconds Counter.
<> 149:156823d33999 37 * There is a set of register to set the values in the counter for each time unit.from where time is start to increment.
<> 149:156823d33999 38 * There is another set of register to set the ALARM ...Each of the Alarm Registers can be programmed with a value that
<> 149:156823d33999 39 * is used to compare to a Counter Register in order to produce an alarm (an interrupt) when the values match.
<> 149:156823d33999 40 * There is a programmable bit in each Alarm Register that determines if the alarm occurs upon a value match, or
<> 149:156823d33999 41 * if the alarm occurs upon a Counter increment condition.
<> 149:156823d33999 42 *
<> 149:156823d33999 43 */
<> 149:156823d33999 44 #include "rtc.h"
<> 149:156823d33999 45 #include "mbed_assert.h"
<> 150:02e0a0aed4ec 46 #include "lp_ticker_api.h"
<> 149:156823d33999 47
<> 149:156823d33999 48 static uint16_t SubSecond;
<> 149:156823d33999 49 static uint64_t LastRtcTimeus;
<> 149:156823d33999 50
<> 149:156823d33999 51 /* See rtc.h for details */
<> 149:156823d33999 52 void fRtcInit(void)
<> 149:156823d33999 53 {
<> 149:156823d33999 54 CLOCK_ENABLE(CLOCK_RTC); /* enable rtc peripheral */
<> 149:156823d33999 55 CLOCKREG->CCR.BITS.RTCEN = True; /* Enable RTC clock 32K */
<> 149:156823d33999 56
<> 149:156823d33999 57 /* Reset RTC control register */
<> 149:156823d33999 58 RTCREG->CONTROL.WORD = False;
<> 149:156823d33999 59
<> 149:156823d33999 60 /* Initialize all counters */
<> 149:156823d33999 61 RTCREG->SECOND_COUNTER = False;
<> 149:156823d33999 62 RTCREG->SUB_SECOND_COUNTER = False;
<> 149:156823d33999 63 RTCREG->SECOND_ALARM = False;
<> 149:156823d33999 64 RTCREG->SUB_SECOND_ALARM = False;
<> 149:156823d33999 65 LastRtcTimeus = 0;
<> 149:156823d33999 66
<> 149:156823d33999 67 /* Reset RTC Status register */
<> 149:156823d33999 68 RTCREG->STATUS.WORD = False;
<> 149:156823d33999 69
<> 149:156823d33999 70 /* Clear interrupt status */
<> 149:156823d33999 71 RTCREG->INT_CLEAR.WORD = False;
<> 149:156823d33999 72
<> 149:156823d33999 73 /* Start sec & sub_sec counter */
<> 149:156823d33999 74 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True);/* Wait previous write to complete */
<> 149:156823d33999 75 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 76 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 77
<> 149:156823d33999 78 /* enable interruption associated with the rtc at NVIC level */
<> 149:156823d33999 79 NVIC_SetVector(Rtc_IRQn,(uint32_t)fRtcHandler); /* TODO define lp_ticker_isr */
<> 149:156823d33999 80 NVIC_ClearPendingIRQ(Rtc_IRQn);
<> 149:156823d33999 81 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 82
<> 149:156823d33999 83 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 84
<> 149:156823d33999 85 return;
<> 149:156823d33999 86 }
<> 149:156823d33999 87
<> 149:156823d33999 88 /* See rtc.h for details */
<> 149:156823d33999 89 void fRtcFree(void)
<> 149:156823d33999 90 {
<> 149:156823d33999 91 /* Reset RTC control register */
<> 149:156823d33999 92 RTCREG->CONTROL.WORD = False;
<> 149:156823d33999 93
<> 149:156823d33999 94 /* disable interruption associated with the rtc */
<> 149:156823d33999 95 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 96
<> 149:156823d33999 97 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 98 }
<> 149:156823d33999 99
<> 149:156823d33999 100 /* See rtc.h for details */
<> 149:156823d33999 101 void fRtcSetInterrupt(uint32_t timestamp)
<> 149:156823d33999 102 {
<> 149:156823d33999 103 SubSecond = False;
<> 150:02e0a0aed4ec 104 uint32_t Second = False, EnableInterrupt = False;
<> 149:156823d33999 105 uint8_t DividerAdjust = 1;
<> 149:156823d33999 106
<> 149:156823d33999 107 if(timestamp) {
<> 149:156823d33999 108 if(timestamp >= RTC_SEC_TO_US) {
<> 149:156823d33999 109 /* TimeStamp is big enough to set second alarm */
<> 149:156823d33999 110 Second = ((timestamp / RTC_SEC_TO_US) & RTC_SEC_MASK); /* Convert micro second to second */
<> 149:156823d33999 111 RTCREG->SECOND_ALARM = Second; /* Write to alarm register */
<> 149:156823d33999 112
<> 149:156823d33999 113 /* Enable second interrupt */
<> 150:02e0a0aed4ec 114 EnableInterrupt = True << RTC_CONTROL_SEC_CNT_INT_BIT_POS;
<> 149:156823d33999 115 }
<> 149:156823d33999 116 timestamp = timestamp - Second * RTC_SEC_TO_US; /* Take out micro second for sub second alarm */
<> 149:156823d33999 117 if(timestamp > False) {
<> 149:156823d33999 118 /* We have some thing for sub second */
<> 149:156823d33999 119
<> 149:156823d33999 120 /* Convert micro second to sub_seconds(each count = 30.5 us) */
<> 149:156823d33999 121 if(timestamp > 131000) {
<> 149:156823d33999 122 DividerAdjust = 100;
<> 149:156823d33999 123 }
<> 149:156823d33999 124
<> 149:156823d33999 125 volatile uint64_t Temp = (timestamp / DividerAdjust * RTC_CLOCK_HZ);
<> 149:156823d33999 126 Temp = (uint64_t)(Temp / RTC_SEC_TO_US * DividerAdjust);
<> 149:156823d33999 127 SubSecond = Temp & RTC_SUB_SEC_MASK;
<> 149:156823d33999 128
<> 149:156823d33999 129 if(SubSecond <= 5) {
<> 149:156823d33999 130 SubSecond = 0;
<> 149:156823d33999 131 }
<> 149:156823d33999 132
<> 149:156823d33999 133 if(SubSecond > False) {
<> 149:156823d33999 134 /* Second interrupt not enabled */
<> 149:156823d33999 135
<> 149:156823d33999 136 /* Set SUB SEC_ALARM */
<> 149:156823d33999 137 RTCREG->SUB_SECOND_ALARM = SubSecond; /* Write to sub second alarm */
<> 149:156823d33999 138
<> 149:156823d33999 139 /* Enable sub second interrupt */
<> 150:02e0a0aed4ec 140 EnableInterrupt |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 149:156823d33999 141 }
<> 149:156823d33999 142 }
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144 RTCREG->CONTROL.WORD |= EnableInterrupt;
<> 150:02e0a0aed4ec 145 /* Enable RTC interrupt */
<> 150:02e0a0aed4ec 146 NVIC_EnableIRQ(Rtc_IRQn);
<> 150:02e0a0aed4ec 147
<> 150:02e0a0aed4ec 148 /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 150:02e0a0aed4ec 149 while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
<> 150:02e0a0aed4ec 150 (True << RTC_STATUS_SEC_ALARM_WRT_BIT_POS) |
<> 150:02e0a0aed4ec 151 (True << RTC_STATUS_CONTROL_WRT_BIT_POS))) == True);
<> 149:156823d33999 152 }
<> 149:156823d33999 153 return;
<> 149:156823d33999 154 }
<> 149:156823d33999 155
<> 149:156823d33999 156 /* See rtc.h for details */
<> 149:156823d33999 157 void fRtcDisableInterrupt(void)
<> 149:156823d33999 158 {
<> 150:02e0a0aed4ec 159 /* Disable RTC interrupt */
<> 150:02e0a0aed4ec 160 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 161 }
<> 149:156823d33999 162
<> 149:156823d33999 163 /* See rtc.h for details */
<> 149:156823d33999 164 void fRtcEnableInterrupt(void)
<> 149:156823d33999 165 {
<> 150:02e0a0aed4ec 166 /* Enable RTC interrupt */
<> 150:02e0a0aed4ec 167 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 168 }
<> 149:156823d33999 169
<> 149:156823d33999 170 /* See rtc.h for details */
<> 149:156823d33999 171 void fRtcClearInterrupt(void)
<> 149:156823d33999 172 {
<> 149:156823d33999 173 /* Disable subsec/sec interrupt */
<> 149:156823d33999 174 /* Clear sec & sub_sec interrupts */
<> 149:156823d33999 175 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 149:156823d33999 176 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 150:02e0a0aed4ec 177
<> 150:02e0a0aed4ec 178 while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
<> 150:02e0a0aed4ec 179 (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS))) == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 180 }
<> 149:156823d33999 181
<> 149:156823d33999 182 /* See rtc.h for details */
<> 149:156823d33999 183 uint64_t fRtcRead(void)
<> 149:156823d33999 184 {
<> 149:156823d33999 185 uint32_t Second;
<> 149:156823d33999 186 uint16_t SubSecond;
<> 149:156823d33999 187
<> 149:156823d33999 188 /* Hardware Bug fix: The rollover of the sub-second counter initiates the increment of the second counter.
<> 149:156823d33999 189 * That means there is one cycle where the sub-second has rolled back to zero and the second counter has not incremented
<> 149:156823d33999 190 * and a read during that cycle will be incorrect. That will occur for one RTC cycle and that is about 31us of exposure.
<> 149:156823d33999 191 * If you read a zero in the sub-second counter then increment the second counter by 1.
<> 149:156823d33999 192 * Alternatively, subtract 1 from the Sub-seconds counter to align the Second and Sub-Second rollover.
<> 149:156823d33999 193 */
<> 149:156823d33999 194
<> 149:156823d33999 195 /* Read the Second and Sub-second counters, then read the Second counter again.
<> 149:156823d33999 196 * If it changed, then the Second rolled over while reading Sub-seconds, so go back and read them both again.
<> 149:156823d33999 197 */
<> 149:156823d33999 198
<> 149:156823d33999 199 do {
<> 150:02e0a0aed4ec 200 Second = RTCREG->SECOND_COUNTER; /* Get SEC_COUNTER reg value */
<> 150:02e0a0aed4ec 201 SubSecond = (RTCREG->SUB_SECOND_COUNTER - 1) & SUB_SEC_MASK; /* Get SUB_SEC_COUNTER reg value */
<> 150:02e0a0aed4ec 202 } while (Second != RTCREG->SECOND_COUNTER); /* Repeat if the second has changed */
<> 149:156823d33999 203
<> 149:156823d33999 204 //note: casting to float removed to avoid reduction in resolution
<> 149:156823d33999 205 uint64_t RtcTimeus = ((uint64_t)SubSecond * RTC_SEC_TO_US / RTC_CLOCK_HZ) + ((uint64_t)Second * RTC_SEC_TO_US);
<> 149:156823d33999 206
<> 149:156823d33999 207 /*check that the time did not go backwards */
<> 149:156823d33999 208 MBED_ASSERT(RtcTimeus >= LastRtcTimeus);
<> 149:156823d33999 209 LastRtcTimeus = RtcTimeus;
<> 149:156823d33999 210
<> 149:156823d33999 211 return RtcTimeus;
<> 149:156823d33999 212 }
<> 149:156823d33999 213
<> 149:156823d33999 214 /* See rtc.h for details */
<> 149:156823d33999 215 void fRtcWrite(uint64_t RtcTimeus)
<> 149:156823d33999 216 {
<> 150:02e0a0aed4ec 217 uint32_t Second = False;
<> 150:02e0a0aed4ec 218 uint16_t SubSecond = False;
<> 149:156823d33999 219 /* Stop RTC */
<> 149:156823d33999 220 RTCREG->CONTROL.WORD &= ~((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 221 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 222
<> 149:156823d33999 223 if(RtcTimeus > RTC_SEC_TO_US) {
<> 149:156823d33999 224 /* TimeStamp is big enough to set second counter */
<> 149:156823d33999 225 Second = ((RtcTimeus / RTC_SEC_TO_US) & RTC_SEC_MASK);
<> 149:156823d33999 226 }
<> 149:156823d33999 227 RTCREG->SECOND_COUNTER = Second;
<> 149:156823d33999 228 RtcTimeus = RtcTimeus - (Second * RTC_SEC_TO_US);
<> 149:156823d33999 229 if(RtcTimeus > False) {
<> 149:156823d33999 230 /* Convert TimeStamp to sub_seconds */
<> 149:156823d33999 231 SubSecond = (uint16_t)((float)(RtcTimeus * RTC_CLOCK_HZ / RTC_SEC_TO_US)) & RTC_SUB_SEC_MASK;
<> 149:156823d33999 232 }
<> 149:156823d33999 233 /* Set SUB_SEC_ALARM */
<> 149:156823d33999 234 RTCREG->SUB_SECOND_COUNTER = SubSecond;
<> 149:156823d33999 235
<> 149:156823d33999 236 while(RTCREG->STATUS.BITS.BSY_CTRL_REG_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 237 /* Start RTC */
<> 149:156823d33999 238 RTCREG->CONTROL.WORD |= ((True << RTC_CONTROL_SUBSEC_CNT_START_BIT_POS) |
<> 149:156823d33999 239 (True << RTC_CONTROL_SEC_CNT_START_BIT_POS));
<> 149:156823d33999 240
<> 149:156823d33999 241 while(RTCREG->STATUS.BITS.BSY_ANY_WRT == True); /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 149:156823d33999 242 }
<> 149:156823d33999 243
<> 149:156823d33999 244 /* See rtc.h for details */
<> 149:156823d33999 245 void fRtcHandler(void)
<> 149:156823d33999 246 {
<> 149:156823d33999 247 /* SUB_SECOND/SECOND interrupt occured */
<> 149:156823d33999 248 volatile uint32_t TempStatus = RTCREG->STATUS.WORD;
<> 149:156823d33999 249
<> 149:156823d33999 250 /* Disable RTC interrupt */
<> 149:156823d33999 251 NVIC_DisableIRQ(Rtc_IRQn);
<> 149:156823d33999 252
<> 149:156823d33999 253 /* Clear sec & sub_sec interrupts */
<> 149:156823d33999 254 RTCREG->INT_CLEAR.WORD = ((True << RTC_INT_CLR_SUB_SEC_BIT_POS) |
<> 149:156823d33999 255 (True << RTC_INT_CLR_SEC_BIT_POS));
<> 149:156823d33999 256
<> 149:156823d33999 257 /* TODO ANDing SUB_SEC & SEC interrupt - work around for RTC issue - will be resolved in REV G */
<> 149:156823d33999 258 if(TempStatus & RTC_SEC_INT_STATUS_MASK) {
<> 149:156823d33999 259 /* Second interrupt occured */
<> 149:156823d33999 260 if(SubSecond > False) {
<> 149:156823d33999 261 /* Set SUB SEC_ALARM */
<> 149:156823d33999 262 RTCREG->SUB_SECOND_ALARM = SubSecond + RTCREG->SUB_SECOND_COUNTER;
<> 149:156823d33999 263 /* Enable sub second interrupt */
<> 149:156823d33999 264 RTCREG->CONTROL.WORD |= (True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS);
<> 149:156823d33999 265 } else {
<> 149:156823d33999 266 /* We reach here after second interrupt is occured */
<> 149:156823d33999 267 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 149:156823d33999 268 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 149:156823d33999 269 }
<> 149:156823d33999 270 } else {
<> 149:156823d33999 271 /* We reach here after sub_second or (Sub second + second) interrupt occured */
<> 149:156823d33999 272 /* Disable Second and sub_second interrupt */
<> 149:156823d33999 273 RTCREG->CONTROL.WORD &= ~(True << RTC_CONTROL_SUBSEC_CNT_INT_BIT_POS) |
<> 149:156823d33999 274 (True << RTC_CONTROL_SEC_CNT_INT_BIT_POS);
<> 149:156823d33999 275 }
<> 149:156823d33999 276
<> 149:156823d33999 277 NVIC_EnableIRQ(Rtc_IRQn);
<> 149:156823d33999 278
<> 150:02e0a0aed4ec 279 /* Wait for RTC to finish writing register - RTC operates on 32K clock as compared to 32M core*/
<> 150:02e0a0aed4ec 280 while((RTCREG->STATUS.WORD & ((True << RTC_STATUS_SUB_SEC_ALARM_WRT_BIT_POS) |
<> 150:02e0a0aed4ec 281 (True << RTC_STATUS_CONTROL_WRT_BIT_POS) |
<> 150:02e0a0aed4ec 282 (True << RTC_STATUS_SUB_SEC_INT_CLR_WRT_BIT_POS) |
<> 150:02e0a0aed4ec 283 (True << RTC_STATUS_SEC_INT_CLR_WRT_BIT_POS))) == True);
<> 149:156823d33999 284
<> 149:156823d33999 285 lp_ticker_irq_handler();
<> 149:156823d33999 286 }
<> 149:156823d33999 287
<> 149:156823d33999 288 boolean fIsRtcEnabled(void)
<> 149:156823d33999 289 {
<> 149:156823d33999 290 if(RTCREG->CONTROL.BITS.SUB_SEC_COUNTER_EN | RTCREG->CONTROL.BITS.SEC_COUNTER_EN) {
<> 149:156823d33999 291 return True;
<> 149:156823d33999 292 } else {
<> 149:156823d33999 293 return False;
<> 149:156823d33999 294 }
<> 149:156823d33999 295 }