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mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32630/mxc/gpio.h@162:16168a1438f3, 2017-04-08 (annotated)

Committer:
funshine
Date:
Sat Apr 08 17:03:55 2017 +0000
Revision:
162:16168a1438f3
Parent:
157:ff67d9f36b67 
add code to handle serial port rx error in uart_irq()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24659 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _GPIO_H_
<> 157:ff67d9f36b67 44 #define _GPIO_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* **** Includes **** */
<> 157:ff67d9f36b67 47 #include "mxc_config.h"
<> 157:ff67d9f36b67 48 #include "gpio_regs.h"
<> 157:ff67d9f36b67 49
<> 157:ff67d9f36b67 50 #ifdef __cplusplus
<> 157:ff67d9f36b67 51 extern "C" {
<> 157:ff67d9f36b67 52 #endif
<> 157:ff67d9f36b67 53
<> 157:ff67d9f36b67 54 // Doxy group definition for this peripheral module
<> 157:ff67d9f36b67 55 /**
<> 157:ff67d9f36b67 56 * @ingroup periphlibs
<> 157:ff67d9f36b67 57 * @defgroup gpio General-Purpose Input/Output (GPIO)
<> 157:ff67d9f36b67 58 * @{
<> 157:ff67d9f36b67 59 */
<> 157:ff67d9f36b67 60
<> 157:ff67d9f36b67 61 /* **** Definitions **** */
<> 157:ff67d9f36b67 62 /**
<> 157:ff67d9f36b67 63 * @defgroup gpio_port_pin Port and Pin Definitions
<> 157:ff67d9f36b67 64 * @ingroup gpio
<> 157:ff67d9f36b67 65 * @{
<> 157:ff67d9f36b67 66 * @defgroup gpio_port Port Definitions
<> 157:ff67d9f36b67 67 * @ingroup gpio_port_pin
<> 157:ff67d9f36b67 68 * @{
<> 157:ff67d9f36b67 69 */
<> 157:ff67d9f36b67 70 #define PORT_0 (0) /**< Port 0 Define*/
<> 157:ff67d9f36b67 71 #define PORT_1 (1) /**< Port 1 Define*/
<> 157:ff67d9f36b67 72 #define PORT_2 (2) /**< Port 2 Define*/
<> 157:ff67d9f36b67 73 #define PORT_3 (3) /**< Port 3 Define*/
<> 157:ff67d9f36b67 74 #define PORT_4 (4) /**< Port 4 Define*/
<> 157:ff67d9f36b67 75 #define PORT_5 (5) /**< Port 5 Define*/
<> 157:ff67d9f36b67 76 #define PORT_6 (6) /**< Port 6 Define*/
<> 157:ff67d9f36b67 77 #define PORT_7 (7) /**< Port 7 Define*/
<> 157:ff67d9f36b67 78 #define PORT_8 (8) /**< Port 8 Define*/
<> 157:ff67d9f36b67 79 #define PORT_9 (9) /**< Port 9 Define*/
<> 157:ff67d9f36b67 80 #define PORT_10 (10) /**< Port 10 Define*/
<> 157:ff67d9f36b67 81 #define PORT_11 (11) /**< Port 11 Define*/
<> 157:ff67d9f36b67 82 #define PORT_12 (12) /**< Port 12 Define*/
<> 157:ff67d9f36b67 83 #define PORT_13 (13) /**< Port 13 Define*/
<> 157:ff67d9f36b67 84 #define PORT_14 (14) /**< Port 14 Define*/
<> 157:ff67d9f36b67 85 #define PORT_15 (15) /**< Port 15 Define*/
<> 157:ff67d9f36b67 86 /**@} end of gpio_port group*/
<> 157:ff67d9f36b67 87 /**
<> 157:ff67d9f36b67 88 * @defgroup gpio_pin Pin Definitions
<> 157:ff67d9f36b67 89 * @ingroup gpio_port_pin
<> 157:ff67d9f36b67 90 * @{
<> 157:ff67d9f36b67 91 */
<> 157:ff67d9f36b67 92 #define PIN_0 (1 << 0) /**< Pin 0 Define */
<> 157:ff67d9f36b67 93 #define PIN_1 (1 << 1) /**< Pin 1 Define */
<> 157:ff67d9f36b67 94 #define PIN_2 (1 << 2) /**< Pin 2 Define */
<> 157:ff67d9f36b67 95 #define PIN_3 (1 << 3) /**< Pin 3 Define */
<> 157:ff67d9f36b67 96 #define PIN_4 (1 << 4) /**< Pin 4 Define */
<> 157:ff67d9f36b67 97 #define PIN_5 (1 << 5) /**< Pin 5 Define */
<> 157:ff67d9f36b67 98 #define PIN_6 (1 << 6) /**< Pin 6 Define */
<> 157:ff67d9f36b67 99 #define PIN_7 (1 << 7) /**< Pin 7 Define */
<> 157:ff67d9f36b67 100 /**@} end of gpio_pin group */
<> 157:ff67d9f36b67 101 /**@} end of gpio_port_pin group */
<> 157:ff67d9f36b67 102
<> 157:ff67d9f36b67 103 /**
<> 157:ff67d9f36b67 104 * Enumeration type for the GPIO Function Type
<> 157:ff67d9f36b67 105 */
<> 157:ff67d9f36b67 106 typedef enum {
<> 157:ff67d9f36b67 107 GPIO_FUNC_GPIO = MXC_V_GPIO_FUNC_SEL_MODE_GPIO, /**< GPIO Function Selection */
<> 157:ff67d9f36b67 108 GPIO_FUNC_PT = MXC_V_GPIO_FUNC_SEL_MODE_PT, /**< Pulse Train Function Selection */
<> 157:ff67d9f36b67 109 GPIO_FUNC_TMR = MXC_V_GPIO_FUNC_SEL_MODE_TMR /**< Timer Function Selection */
<> 157:ff67d9f36b67 110 }
<> 157:ff67d9f36b67 111 gpio_func_t;
<> 157:ff67d9f36b67 112
<> 157:ff67d9f36b67 113 /**
<> 157:ff67d9f36b67 114 * Enumeration type for the type of GPIO pad on a given pin.
<> 157:ff67d9f36b67 115 */
<> 157:ff67d9f36b67 116 typedef enum {
<> 157:ff67d9f36b67 117 GPIO_PAD_INPUT_PULLUP = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP, /**< Set pad to high impedance, weak pull-up */
<> 157:ff67d9f36b67 118 GPIO_PAD_OPEN_DRAIN = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN, /**< Set pad to open-drain with high impedance with input buffer */
<> 157:ff67d9f36b67 119 GPIO_PAD_OPEN_DRAIN_PULLUP = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP, /**< Set pad to open-drain with weak pull-up */
<> 157:ff67d9f36b67 120 GPIO_PAD_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, /**< Set pad to high impednace, input buffer enabled */
<> 157:ff67d9f36b67 121 GPIO_PAD_NORMAL = MXC_V_GPIO_OUT_MODE_NORMAL, /**< Set pad to normal drive mode for high an low output */
<> 157:ff67d9f36b67 122 GPIO_PAD_SLOW = MXC_V_GPIO_OUT_MODE_SLOW_DRIVE, /**< Set pad to slow drive mode, which is normal mode with negative feedback to slow edge transitions */
<> 157:ff67d9f36b67 123 GPIO_PAD_FAST = MXC_V_GPIO_OUT_MODE_FAST_DRIVE, /**< Set pad to fash drive mode, which is normal mode with a transistor drive to drive fast high and low */
<> 157:ff67d9f36b67 124 GPIO_PAD_INPUT_PULLDOWN = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN, /**< Set pad to weak pulldown mode */
<> 157:ff67d9f36b67 125 GPIO_PAD_OPEN_SOURCE = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE, /**< Set pad to open source mode, transistor drive to high */
<> 157:ff67d9f36b67 126 GPIO_PAD_OPEN_SOURCE_PULLDOWN = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN /**< Set pad to open source with weak pulldown mode, transistor drive to high, weak pulldown to GND for low */
<> 157:ff67d9f36b67 127 } gpio_pad_t;
<> 157:ff67d9f36b67 128
<> 157:ff67d9f36b67 129 /**
<> 157:ff67d9f36b67 130 * Structure type for configuring a GPIO port.
<> 157:ff67d9f36b67 131 */
<> 157:ff67d9f36b67 132 typedef struct {
<> 157:ff67d9f36b67 133 uint32_t port; /// Index of GPIO port
<> 157:ff67d9f36b67 134 uint32_t mask; /// Pin mask. Multiple bits can be set.
<> 157:ff67d9f36b67 135 gpio_func_t func; /// Function type
<> 157:ff67d9f36b67 136 gpio_pad_t pad; /// Pad type
<> 157:ff67d9f36b67 137 } gpio_cfg_t;
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 /**
<> 157:ff67d9f36b67 140 * Enumeration type for the interrupt type on a GPIO port.
<> 157:ff67d9f36b67 141 */
<> 157:ff67d9f36b67 142 typedef enum {
<> 157:ff67d9f36b67 143 GPIO_INT_DISABLE = MXC_V_GPIO_INT_MODE_DISABLE, /**< Disable interrupts */
<> 157:ff67d9f36b67 144 GPIO_INT_FALLING_EDGE = MXC_V_GPIO_INT_MODE_FALLING_EDGE, /**< Interrupt on Falling Edge */
<> 157:ff67d9f36b67 145 GPIO_INT_RISING_EDGE = MXC_V_GPIO_INT_MODE_RISING_EDGE, /**< Interrupt on Rising Edge */
<> 157:ff67d9f36b67 146 GPIO_INT_ANY_EDGE = MXC_V_GPIO_INT_MODE_ANY_EDGE, /**< Interrupt on Falling or Rising Edge */
<> 157:ff67d9f36b67 147 GPIO_INT_LOW_LEVEL = MXC_V_GPIO_INT_MODE_LOW_LVL, /**< Interrupt on a low level input detection */
<> 157:ff67d9f36b67 148 GPIO_INT_HIGH_LEVEL = MXC_V_GPIO_INT_MODE_HIGH_LVL /**< Interrupt on a high level input detection */
<> 157:ff67d9f36b67 149 } gpio_int_mode_t;
<> 157:ff67d9f36b67 150
<> 157:ff67d9f36b67 151 /* **** Function Prototypes **** */
<> 157:ff67d9f36b67 152
<> 157:ff67d9f36b67 153 /**
<> 157:ff67d9f36b67 154 * @brief Configure GPIO pin(s).
<> 157:ff67d9f36b67 155 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 156 *
<> 157:ff67d9f36b67 157 * @return #E_NO_ERROR if everything is successful.
<> 157:ff67d9f36b67 158 *
<> 157:ff67d9f36b67 159 */
<> 157:ff67d9f36b67 160 int GPIO_Config(const gpio_cfg_t *cfg);
<> 157:ff67d9f36b67 161
<> 157:ff67d9f36b67 162 /**
<> 157:ff67d9f36b67 163 * @brief Gets the pin(s) input state.
<> 157:ff67d9f36b67 164 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 165 *
<> 157:ff67d9f36b67 166 * @return The requested pin state.
<> 157:ff67d9f36b67 167 *
<> 157:ff67d9f36b67 168 */
<> 157:ff67d9f36b67 169 __STATIC_INLINE uint32_t GPIO_InGet(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 170 {
<> 157:ff67d9f36b67 171 return (MXC_GPIO->in_val[cfg->port] & cfg->mask);
<> 157:ff67d9f36b67 172 }
<> 157:ff67d9f36b67 173
<> 157:ff67d9f36b67 174 /**
<> 157:ff67d9f36b67 175 * @brief Sets the pin(s) to a high level output.
<> 157:ff67d9f36b67 176 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 177 *
<> 157:ff67d9f36b67 178 */
<> 157:ff67d9f36b67 179 __STATIC_INLINE void GPIO_OutSet(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 180 {
<> 157:ff67d9f36b67 181 MXC_GPIO->out_val[cfg->port] |= cfg->mask;
<> 157:ff67d9f36b67 182 }
<> 157:ff67d9f36b67 183
<> 157:ff67d9f36b67 184 /**
<> 157:ff67d9f36b67 185 * @brief Clears the pin(s) to a low level output.
<> 157:ff67d9f36b67 186 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 187 *
<> 157:ff67d9f36b67 188 */
<> 157:ff67d9f36b67 189 __STATIC_INLINE void GPIO_OutClr(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 190 {
<> 157:ff67d9f36b67 191 MXC_GPIO->out_val[cfg->port] &= ~(cfg->mask);
<> 157:ff67d9f36b67 192 }
<> 157:ff67d9f36b67 193
<> 157:ff67d9f36b67 194 /**
<> 157:ff67d9f36b67 195 * @brief Gets the pin(s) output state.
<> 157:ff67d9f36b67 196 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 197 *
<> 157:ff67d9f36b67 198 * @return The state of the requested pin.
<> 157:ff67d9f36b67 199 *
<> 157:ff67d9f36b67 200 */
<> 157:ff67d9f36b67 201 __STATIC_INLINE uint32_t GPIO_OutGet(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 202 {
<> 157:ff67d9f36b67 203 return (MXC_GPIO->out_val[cfg->port] & cfg->mask);
<> 157:ff67d9f36b67 204 }
<> 157:ff67d9f36b67 205
<> 157:ff67d9f36b67 206 /**
<> 157:ff67d9f36b67 207 * @brief Write the pin(s) to a desired output level.
<> 157:ff67d9f36b67 208 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 209 * @param val Desired output level of the pin(s). This will be masked
<> 157:ff67d9f36b67 210 * with the configuration mask.
<> 157:ff67d9f36b67 211 *
<> 157:ff67d9f36b67 212 */
<> 157:ff67d9f36b67 213 __STATIC_INLINE void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val)
<> 157:ff67d9f36b67 214 {
<> 157:ff67d9f36b67 215 MXC_GPIO->out_val[cfg->port] = (MXC_GPIO->out_val[cfg->port] & ~cfg->mask) | (val & cfg->mask);
<> 157:ff67d9f36b67 216 }
<> 157:ff67d9f36b67 217
<> 157:ff67d9f36b67 218 /**
<> 157:ff67d9f36b67 219 * @brief Toggles the the pin(s) output level.
<> 157:ff67d9f36b67 220 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 221 *
<> 157:ff67d9f36b67 222 */
<> 157:ff67d9f36b67 223 __STATIC_INLINE void GPIO_OutToggle(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 224 {
<> 157:ff67d9f36b67 225 MXC_GPIO->out_val[cfg->port] ^= cfg->mask;
<> 157:ff67d9f36b67 226 }
<> 157:ff67d9f36b67 227
<> 157:ff67d9f36b67 228 /**
<> 157:ff67d9f36b67 229 * @brief Configure GPIO interrupt(s)
<> 157:ff67d9f36b67 230 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 231 * @param mode Requested interrupt mode.
<> 157:ff67d9f36b67 232 *
<> 157:ff67d9f36b67 233 */
<> 157:ff67d9f36b67 234 void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode);
<> 157:ff67d9f36b67 235
<> 157:ff67d9f36b67 236 /**
<> 157:ff67d9f36b67 237 * @brief Enables the specified GPIO interrupt
<> 157:ff67d9f36b67 238 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 239 *
<> 157:ff67d9f36b67 240 */
<> 157:ff67d9f36b67 241 __STATIC_INLINE void GPIO_IntEnable(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 242 {
<> 157:ff67d9f36b67 243 MXC_GPIO->inten[cfg->port] |= cfg->mask;
<> 157:ff67d9f36b67 244 }
<> 157:ff67d9f36b67 245
<> 157:ff67d9f36b67 246 /**
<> 157:ff67d9f36b67 247 * @brief Disables the specified GPIO interrupt.
<> 157:ff67d9f36b67 248 * @param cfg Pointer to configuration structure describing the pin.
<> 157:ff67d9f36b67 249 *
<> 157:ff67d9f36b67 250 */
<> 157:ff67d9f36b67 251 __STATIC_INLINE void GPIO_IntDisable(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 252 {
<> 157:ff67d9f36b67 253 MXC_GPIO->inten[cfg->port] &= ~cfg->mask;
<> 157:ff67d9f36b67 254 }
<> 157:ff67d9f36b67 255
<> 157:ff67d9f36b67 256 /**
<> 157:ff67d9f36b67 257 * @brief Gets the interrupt(s) status on a GPIO pin.
<> 157:ff67d9f36b67 258 * @param cfg Pointer to configuration structure describing the pin
<> 157:ff67d9f36b67 259 * for which the status is being requested.
<> 157:ff67d9f36b67 260 *
<> 157:ff67d9f36b67 261 * @return The requested interrupt status.
<> 157:ff67d9f36b67 262 *
<> 157:ff67d9f36b67 263 */
<> 157:ff67d9f36b67 264 __STATIC_INLINE uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 265 {
<> 157:ff67d9f36b67 266 return (MXC_GPIO->intfl[cfg->port] & cfg->mask);
<> 157:ff67d9f36b67 267 }
<> 157:ff67d9f36b67 268
<> 157:ff67d9f36b67 269 /**
<> 157:ff67d9f36b67 270 * @brief Clears the interrupt(s) status on a GPIO pin.
<> 157:ff67d9f36b67 271 * @param cfg Pointer to configuration structure describing the pin
<> 157:ff67d9f36b67 272 * to clear the interrupt state of.
<> 157:ff67d9f36b67 273 *
<> 157:ff67d9f36b67 274 */
<> 157:ff67d9f36b67 275 __STATIC_INLINE void GPIO_IntClr(const gpio_cfg_t *cfg)
<> 157:ff67d9f36b67 276 {
<> 157:ff67d9f36b67 277 MXC_GPIO->intfl[cfg->port] = cfg->mask;
<> 157:ff67d9f36b67 278 }
<> 157:ff67d9f36b67 279
<> 157:ff67d9f36b67 280 /**
<> 157:ff67d9f36b67 281 * @brief Type alias for a GPIO callback function with prototype:
<> 157:ff67d9f36b67 282 * @code
<> 157:ff67d9f36b67 283 * void callback_fn(void *cbdata);
<> 157:ff67d9f36b67 284 * @endcode
<> 157:ff67d9f36b67 285 * @param cbdata A void pointer to the data type as registered when
<> 157:ff67d9f36b67 286 * @c GPIO_RegisterCallback() was called.
<> 157:ff67d9f36b67 287 *
<> 157:ff67d9f36b67 288 */
<> 157:ff67d9f36b67 289 typedef void (*gpio_callback_fn)(void *cbdata);
<> 157:ff67d9f36b67 290
<> 157:ff67d9f36b67 291 /**
<> 157:ff67d9f36b67 292 * @brief Registers a callback for the interrupt on a given port and pin.
<> 157:ff67d9f36b67 293 * @param cfg Pointer to configuration structure describing the pin
<> 157:ff67d9f36b67 294 * @param callback A pointer to a function of type #gpio_callback_fn.
<> 157:ff67d9f36b67 295 * @param cbdata The parameter to be passed to the callback function, #gpio_callback_fn, when an interrupt occurs.
<> 157:ff67d9f36b67 296 *
<> 157:ff67d9f36b67 297 */
<> 157:ff67d9f36b67 298 void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
<> 157:ff67d9f36b67 299
<> 157:ff67d9f36b67 300 /**
<> 157:ff67d9f36b67 301 * @brief GPIO IRQ Handler. @note If a callback is registered for a given
<> 157:ff67d9f36b67 302 * interrupt, the callback function will be called.
<> 157:ff67d9f36b67 303 *
<> 157:ff67d9f36b67 304 * @param port number of the port that generated the interrupt service routine.
<> 157:ff67d9f36b67 305 *
<> 157:ff67d9f36b67 306 */
<> 157:ff67d9f36b67 307 void GPIO_Handler(unsigned int port);
<> 157:ff67d9f36b67 308
<> 157:ff67d9f36b67 309 /**@} end of group gpio */
<> 157:ff67d9f36b67 310
<> 157:ff67d9f36b67 311 #ifdef __cplusplus
<> 157:ff67d9f36b67 312 }
<> 157:ff67d9f36b67 313 #endif
<> 157:ff67d9f36b67 314
<> 157:ff67d9f36b67 315 #endif /* _GPIO_H_ */