Frank Vannieuwkerke / Mbed 2 deprecated LPC1768_Mini-DK_EasyWeb_DM9161

LPC1768 Mini-DK EasyWeb application with SPI TFT output. Started from EasyWebCR and modified for DM9161 PHY support.

Dependencies:   Mini-DK mbed

This is a very basic EasyWeb application.

No error checking is performed during initialisation.

Information

If the webpage is not reachable or the 'Webserver running' message does not appear, press the reset button on the Mini-DK and wait until the message 'Webserver running' appears.
This happens sometimes when powering up the Mini-DK because the DM9161 reset pin is NOT controlled by the LPC1768, it is directly connected to the reset button.

IP adress/mask/gateway in tcpip.h : 192.168.0.200 / 255.255.255.0 / 192.168.0.1

MAC address in ethmac.h : 6-5-4-3-2-1

ethmac.h@8:4c3db9231e3f, 2013-01-15 (annotated)

Committer:
frankvnk
Date:
Tue Jan 15 06:43:51 2013 +0000
Revision:
8:4c3db9231e3f
Parent:
0:636056c0b5e1 
DM9161_BMSR - bit 13 define modified

Who changed what in which revision?

UserRevisionLine numberNew contents of line
frankvnk 0:636056c0b5e1 1 /******************************************************************
frankvnk 0:636056c0b5e1 2 ***** *****
frankvnk 0:636056c0b5e1 3 ***** Name: ethmac.h *****
frankvnk 0:636056c0b5e1 4 ***** Ver.: 1.0 *****
frankvnk 0:636056c0b5e1 5 ***** Date: 17/12/2012 *****
frankvnk 0:636056c0b5e1 6 ***** Auth: Frank Vannieuwkerke *****
frankvnk 0:636056c0b5e1 7 ***** Func: header-file for ethmac.c *****
frankvnk 0:636056c0b5e1 8 ***** Rewrite from Andreas Dannenberg *****
frankvnk 0:636056c0b5e1 9 ***** HTWK Leipzig *****
frankvnk 0:636056c0b5e1 10 ***** university of applied sciences *****
frankvnk 0:636056c0b5e1 11 ***** Germany *****
frankvnk 0:636056c0b5e1 12 ***** adannenb@et.htwk-leipzig.de *****
frankvnk 0:636056c0b5e1 13 ***** *****
frankvnk 0:636056c0b5e1 14 ******************************************************************/
frankvnk 0:636056c0b5e1 15
frankvnk 0:636056c0b5e1 16 #ifndef __ETHMAC_H
frankvnk 0:636056c0b5e1 17 #define __ETHMAC_H
frankvnk 0:636056c0b5e1 18
frankvnk 0:636056c0b5e1 19 // Ethernet power/clock control bit in PCONP register
frankvnk 0:636056c0b5e1 20 #define PCENET 0x40000000
frankvnk 0:636056c0b5e1 21 // Ethernet configuration for PINSEL2, as per user guide section 5.3
frankvnk 0:636056c0b5e1 22 #define ENET_PINSEL2_CONFIG 0x50150105
frankvnk 0:636056c0b5e1 23 // Ethernet configuration for PINSEL3, as per user guide section 5.4
frankvnk 0:636056c0b5e1 24 #define ENET_PINSEL3_CONFIG 0x00000005
frankvnk 0:636056c0b5e1 25 // Only bottom byte of PINSEL3 relevant to Ethernet
frankvnk 0:636056c0b5e1 26 #define ENET_PINSEL3_MASK 0x0000000F
frankvnk 0:636056c0b5e1 27
frankvnk 0:636056c0b5e1 28 #define MYMAC_1 1 // our ethernet (MAC) address
frankvnk 0:636056c0b5e1 29 #define MYMAC_2 2 // (MUST be unique in LAN!)
frankvnk 0:636056c0b5e1 30 #define MYMAC_3 3
frankvnk 0:636056c0b5e1 31 #define MYMAC_4 4
frankvnk 0:636056c0b5e1 32 #define MYMAC_5 5
frankvnk 0:636056c0b5e1 33 #define MYMAC_6 6
frankvnk 0:636056c0b5e1 34
frankvnk 0:636056c0b5e1 35 // *******
frankvnk 0:636056c0b5e1 36 // defines for LPC1768 ethernet
frankvnk 0:636056c0b5e1 37 // *******
frankvnk 0:636056c0b5e1 38
frankvnk 0:636056c0b5e1 39 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
frankvnk 0:636056c0b5e1 40 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
frankvnk 0:636056c0b5e1 41 #define NUM_TX_FRAG 2 /* Num.of TX Fragments 3*1536= 4.6kB */
frankvnk 0:636056c0b5e1 42 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
frankvnk 0:636056c0b5e1 43
frankvnk 0:636056c0b5e1 44 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
frankvnk 0:636056c0b5e1 45
frankvnk 0:636056c0b5e1 46 /* EMAC variables located in AHB SRAM bank 1*/
frankvnk 0:636056c0b5e1 47 #define RX_DESC_BASE 0x20080000
frankvnk 0:636056c0b5e1 48 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
frankvnk 0:636056c0b5e1 49 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
frankvnk 0:636056c0b5e1 50 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
frankvnk 0:636056c0b5e1 51 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
frankvnk 0:636056c0b5e1 52 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
frankvnk 0:636056c0b5e1 53
frankvnk 0:636056c0b5e1 54 /* RX and TX descriptor and status definitions. */
frankvnk 0:636056c0b5e1 55 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
frankvnk 0:636056c0b5e1 56 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
frankvnk 0:636056c0b5e1 57 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
frankvnk 0:636056c0b5e1 58 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
frankvnk 0:636056c0b5e1 59 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
frankvnk 0:636056c0b5e1 60 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
frankvnk 0:636056c0b5e1 61 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
frankvnk 0:636056c0b5e1 62 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
frankvnk 0:636056c0b5e1 63 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
frankvnk 0:636056c0b5e1 64
frankvnk 0:636056c0b5e1 65 /* MAC Configuration Register 1 */
frankvnk 0:636056c0b5e1 66 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
frankvnk 0:636056c0b5e1 67 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
frankvnk 0:636056c0b5e1 68 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
frankvnk 0:636056c0b5e1 69 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
frankvnk 0:636056c0b5e1 70 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
frankvnk 0:636056c0b5e1 71 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
frankvnk 0:636056c0b5e1 72 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
frankvnk 0:636056c0b5e1 73 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
frankvnk 0:636056c0b5e1 74 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
frankvnk 0:636056c0b5e1 75 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
frankvnk 0:636056c0b5e1 76 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
frankvnk 0:636056c0b5e1 77
frankvnk 0:636056c0b5e1 78 /* MAC Configuration Register 2 */
frankvnk 0:636056c0b5e1 79 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
frankvnk 0:636056c0b5e1 80 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
frankvnk 0:636056c0b5e1 81 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
frankvnk 0:636056c0b5e1 82 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
frankvnk 0:636056c0b5e1 83 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
frankvnk 0:636056c0b5e1 84 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
frankvnk 0:636056c0b5e1 85 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
frankvnk 0:636056c0b5e1 86 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
frankvnk 0:636056c0b5e1 87 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
frankvnk 0:636056c0b5e1 88 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
frankvnk 0:636056c0b5e1 89 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
frankvnk 0:636056c0b5e1 90 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
frankvnk 0:636056c0b5e1 91 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
frankvnk 0:636056c0b5e1 92
frankvnk 0:636056c0b5e1 93 /* Back-to-Back Inter-Packet-Gap Register */
frankvnk 0:636056c0b5e1 94 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
frankvnk 0:636056c0b5e1 95 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
frankvnk 0:636056c0b5e1 96
frankvnk 0:636056c0b5e1 97 /* Non Back-to-Back Inter-Packet-Gap Register */
frankvnk 0:636056c0b5e1 98 #define IPGR_DEF 0x00000012 /* Recommended value */
frankvnk 0:636056c0b5e1 99
frankvnk 0:636056c0b5e1 100 /* Collision Window/Retry Register */
frankvnk 0:636056c0b5e1 101 #define CLRT_DEF 0x0000370F /* Default value */
frankvnk 0:636056c0b5e1 102
frankvnk 0:636056c0b5e1 103 /* PHY Support Register */
frankvnk 0:636056c0b5e1 104 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
frankvnk 0:636056c0b5e1 105 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
frankvnk 0:636056c0b5e1 106
frankvnk 0:636056c0b5e1 107 /* Test Register */
frankvnk 0:636056c0b5e1 108 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
frankvnk 0:636056c0b5e1 109 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
frankvnk 0:636056c0b5e1 110 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
frankvnk 0:636056c0b5e1 111
frankvnk 0:636056c0b5e1 112 /* MII Management Configuration Register */
frankvnk 0:636056c0b5e1 113 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
frankvnk 0:636056c0b5e1 114 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
frankvnk 0:636056c0b5e1 115 #define MCFG_CLK_SEL(n) ((n&0x0F)<<2)/* Clock Select Mask */
frankvnk 0:636056c0b5e1 116 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
frankvnk 0:636056c0b5e1 117 #define MCFG_MII_MAXCLK 2500000UL /* MII Clock max */
frankvnk 0:636056c0b5e1 118
frankvnk 0:636056c0b5e1 119 /* MII Management Command Register */
frankvnk 0:636056c0b5e1 120 #define MCMD_READ 0x00000001 /* MII Read */
frankvnk 0:636056c0b5e1 121 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
frankvnk 0:636056c0b5e1 122
frankvnk 0:636056c0b5e1 123 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
frankvnk 0:636056c0b5e1 124 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
frankvnk 0:636056c0b5e1 125
frankvnk 0:636056c0b5e1 126 /* MII Management Address Register */
frankvnk 0:636056c0b5e1 127 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
frankvnk 0:636056c0b5e1 128 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
frankvnk 0:636056c0b5e1 129
frankvnk 0:636056c0b5e1 130 /* MII Management Indicators Register */
frankvnk 0:636056c0b5e1 131 #define MIND_BUSY 0x00000001 /* MII is Busy */
frankvnk 0:636056c0b5e1 132 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
frankvnk 0:636056c0b5e1 133 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
frankvnk 0:636056c0b5e1 134 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
frankvnk 0:636056c0b5e1 135
frankvnk 0:636056c0b5e1 136 /* Command Register */
frankvnk 0:636056c0b5e1 137 #define CR_RX_EN 0x00000001 /* Enable Receive */
frankvnk 0:636056c0b5e1 138 #define CR_TX_EN 0x00000002 /* Enable Transmit */
frankvnk 0:636056c0b5e1 139 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
frankvnk 0:636056c0b5e1 140 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
frankvnk 0:636056c0b5e1 141 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
frankvnk 0:636056c0b5e1 142 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
frankvnk 0:636056c0b5e1 143 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
frankvnk 0:636056c0b5e1 144 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
frankvnk 0:636056c0b5e1 145 #define CR_RMII 0x00000200 /* Reduced MII Interface */
frankvnk 0:636056c0b5e1 146 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
frankvnk 0:636056c0b5e1 147
frankvnk 0:636056c0b5e1 148 /* Status Register */
frankvnk 0:636056c0b5e1 149 #define SR_RX_EN 0x00000001 /* Enable Receive */
frankvnk 0:636056c0b5e1 150 #define SR_TX_EN 0x00000002 /* Enable Transmit */
frankvnk 0:636056c0b5e1 151
frankvnk 0:636056c0b5e1 152 /* Transmit Status Vector 0 Register */
frankvnk 0:636056c0b5e1 153 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
frankvnk 0:636056c0b5e1 154 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
frankvnk 0:636056c0b5e1 155 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
frankvnk 0:636056c0b5e1 156 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
frankvnk 0:636056c0b5e1 157 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
frankvnk 0:636056c0b5e1 158 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
frankvnk 0:636056c0b5e1 159 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
frankvnk 0:636056c0b5e1 160 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
frankvnk 0:636056c0b5e1 161 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
frankvnk 0:636056c0b5e1 162 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
frankvnk 0:636056c0b5e1 163 #define TSV0_GIANT 0x00000400 /* Giant Frame */
frankvnk 0:636056c0b5e1 164 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
frankvnk 0:636056c0b5e1 165 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
frankvnk 0:636056c0b5e1 166 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
frankvnk 0:636056c0b5e1 167 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
frankvnk 0:636056c0b5e1 168 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
frankvnk 0:636056c0b5e1 169 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
frankvnk 0:636056c0b5e1 170
frankvnk 0:636056c0b5e1 171 /* Transmit Status Vector 1 Register */
frankvnk 0:636056c0b5e1 172 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
frankvnk 0:636056c0b5e1 173 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
frankvnk 0:636056c0b5e1 174
frankvnk 0:636056c0b5e1 175 /* Receive Status Vector Register */
frankvnk 0:636056c0b5e1 176 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
frankvnk 0:636056c0b5e1 177 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
frankvnk 0:636056c0b5e1 178 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
frankvnk 0:636056c0b5e1 179 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
frankvnk 0:636056c0b5e1 180 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
frankvnk 0:636056c0b5e1 181 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
frankvnk 0:636056c0b5e1 182 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
frankvnk 0:636056c0b5e1 183 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
frankvnk 0:636056c0b5e1 184 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
frankvnk 0:636056c0b5e1 185 #define RSV_MCAST 0x01000000 /* Multicast Frame */
frankvnk 0:636056c0b5e1 186 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
frankvnk 0:636056c0b5e1 187 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
frankvnk 0:636056c0b5e1 188 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
frankvnk 0:636056c0b5e1 189 #define RSV_PAUSE 0x10000000 /* Pause Frame */
frankvnk 0:636056c0b5e1 190 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
frankvnk 0:636056c0b5e1 191 #define RSV_VLAN 0x40000000 /* VLAN Frame */
frankvnk 0:636056c0b5e1 192
frankvnk 0:636056c0b5e1 193 /* Flow Control Counter Register */
frankvnk 0:636056c0b5e1 194 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
frankvnk 0:636056c0b5e1 195 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
frankvnk 0:636056c0b5e1 196
frankvnk 0:636056c0b5e1 197 /* Flow Control Status Register */
frankvnk 0:636056c0b5e1 198 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
frankvnk 0:636056c0b5e1 199
frankvnk 0:636056c0b5e1 200 /* Receive Filter Control Register */
frankvnk 0:636056c0b5e1 201 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
frankvnk 0:636056c0b5e1 202 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
frankvnk 0:636056c0b5e1 203 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
frankvnk 0:636056c0b5e1 204 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
frankvnk 0:636056c0b5e1 205 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
frankvnk 0:636056c0b5e1 206 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
frankvnk 0:636056c0b5e1 207 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
frankvnk 0:636056c0b5e1 208 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
frankvnk 0:636056c0b5e1 209
frankvnk 0:636056c0b5e1 210 /* Receive Filter WoL Status/Clear Registers */
frankvnk 0:636056c0b5e1 211 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
frankvnk 0:636056c0b5e1 212 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
frankvnk 0:636056c0b5e1 213 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
frankvnk 0:636056c0b5e1 214 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
frankvnk 0:636056c0b5e1 215 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
frankvnk 0:636056c0b5e1 216 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
frankvnk 0:636056c0b5e1 217 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
frankvnk 0:636056c0b5e1 218 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
frankvnk 0:636056c0b5e1 219
frankvnk 0:636056c0b5e1 220 /* Interrupt Status/Enable/Clear/Set Registers */
frankvnk 0:636056c0b5e1 221 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
frankvnk 0:636056c0b5e1 222 #define INT_RX_ERR 0x00000002 /* Receive Error */
frankvnk 0:636056c0b5e1 223 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
frankvnk 0:636056c0b5e1 224 #define INT_RX_DONE 0x00000008 /* Receive Done */
frankvnk 0:636056c0b5e1 225 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
frankvnk 0:636056c0b5e1 226 #define INT_TX_ERR 0x00000020 /* Transmit Error */
frankvnk 0:636056c0b5e1 227 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
frankvnk 0:636056c0b5e1 228 #define INT_TX_DONE 0x00000080 /* Transmit Done */
frankvnk 0:636056c0b5e1 229 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
frankvnk 0:636056c0b5e1 230 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
frankvnk 0:636056c0b5e1 231
frankvnk 0:636056c0b5e1 232 /* Power Down Register */
frankvnk 0:636056c0b5e1 233 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
frankvnk 0:636056c0b5e1 234
frankvnk 0:636056c0b5e1 235 /* RX Descriptor Control Word */
frankvnk 0:636056c0b5e1 236 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
frankvnk 0:636056c0b5e1 237 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
frankvnk 0:636056c0b5e1 238
frankvnk 0:636056c0b5e1 239 /* RX Status Hash CRC Word */
frankvnk 0:636056c0b5e1 240 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
frankvnk 0:636056c0b5e1 241 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
frankvnk 0:636056c0b5e1 242
frankvnk 0:636056c0b5e1 243 /* RX Status Information Word */
frankvnk 0:636056c0b5e1 244 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
frankvnk 0:636056c0b5e1 245 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
frankvnk 0:636056c0b5e1 246 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
frankvnk 0:636056c0b5e1 247 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
frankvnk 0:636056c0b5e1 248 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
frankvnk 0:636056c0b5e1 249 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
frankvnk 0:636056c0b5e1 250 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
frankvnk 0:636056c0b5e1 251 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
frankvnk 0:636056c0b5e1 252 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
frankvnk 0:636056c0b5e1 253 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
frankvnk 0:636056c0b5e1 254 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
frankvnk 0:636056c0b5e1 255 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
frankvnk 0:636056c0b5e1 256 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
frankvnk 0:636056c0b5e1 257 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
frankvnk 0:636056c0b5e1 258 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
frankvnk 0:636056c0b5e1 259
frankvnk 0:636056c0b5e1 260 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
frankvnk 0:636056c0b5e1 261 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
frankvnk 0:636056c0b5e1 262
frankvnk 0:636056c0b5e1 263 /* TX Descriptor Control Word */
frankvnk 0:636056c0b5e1 264 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
frankvnk 0:636056c0b5e1 265 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
frankvnk 0:636056c0b5e1 266 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
frankvnk 0:636056c0b5e1 267 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
frankvnk 0:636056c0b5e1 268 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
frankvnk 0:636056c0b5e1 269 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
frankvnk 0:636056c0b5e1 270 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
frankvnk 0:636056c0b5e1 271
frankvnk 0:636056c0b5e1 272 /* TX Status Information Word */
frankvnk 0:636056c0b5e1 273 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
frankvnk 0:636056c0b5e1 274 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
frankvnk 0:636056c0b5e1 275 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
frankvnk 0:636056c0b5e1 276 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
frankvnk 0:636056c0b5e1 277 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
frankvnk 0:636056c0b5e1 278 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
frankvnk 0:636056c0b5e1 279 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
frankvnk 0:636056c0b5e1 280 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
frankvnk 0:636056c0b5e1 281
frankvnk 0:636056c0b5e1 282 /* ENET Device Revision ID */
frankvnk 0:636056c0b5e1 283 #define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */
frankvnk 0:636056c0b5e1 284
frankvnk 0:636056c0b5e1 285 /** PHY device reset time out definition */
frankvnk 0:636056c0b5e1 286 #define PHY_RESP_TOUT 0x100000UL
frankvnk 0:636056c0b5e1 287
frankvnk 0:636056c0b5e1 288 /* DM9161 PHY Registers */
frankvnk 0:636056c0b5e1 289 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
frankvnk 0:636056c0b5e1 290 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
frankvnk 0:636056c0b5e1 291 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
frankvnk 0:636056c0b5e1 292 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
frankvnk 0:636056c0b5e1 293 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
frankvnk 0:636056c0b5e1 294 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
frankvnk 0:636056c0b5e1 295 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
frankvnk 0:636056c0b5e1 296
frankvnk 0:636056c0b5e1 297 /* PHY Extended Registers */
frankvnk 0:636056c0b5e1 298 #define PHY_REG_DSCR 0x10 /* Specified Configuration Register */
frankvnk 0:636056c0b5e1 299 #define PHY_REG_DSCSR 0x11 /* Specified Configuration and Status Register */
frankvnk 0:636056c0b5e1 300 #define PHY_REG_10BTCSR 0x12 /* 10BASE-T Configuration and Satus Register */
frankvnk 0:636056c0b5e1 301 #define PHY_REG_MDINTR 0x15 /* Specified Interrupt Register */
frankvnk 0:636056c0b5e1 302 #define PHY_REG_RECR 0x16 /* Specified Receive Error Counter Register */
frankvnk 0:636056c0b5e1 303 #define PHY_REG_DISCR 0x17 /* Specified Disconnect Counter Register */
frankvnk 0:636056c0b5e1 304 #define PHY_REG_RLSR 0x18 /* Hardware Reset Latch State Register */
frankvnk 0:636056c0b5e1 305
frankvnk 0:636056c0b5e1 306 //--Bit definitions: DM9161_BMCR
frankvnk 0:636056c0b5e1 307 #define DM9161_RESET (1 << 15) // 1=Software Reset; 0=Normal Operation
frankvnk 0:636056c0b5e1 308 #define DM9161_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
frankvnk 0:636056c0b5e1 309 #define DM9161_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
frankvnk 0:636056c0b5e1 310 #define DM9161_AUTONEG (1 << 12) // 1=Auto negotiation enabled. Bit8 and bit13 will be in auto negotiation Status.
frankvnk 0:636056c0b5e1 311 #define DM9161_POWER_DOWN (1 << 11)
frankvnk 0:636056c0b5e1 312 #define DM9161_ISOLATE (1 << 10)
frankvnk 0:636056c0b5e1 313 #define DM9161_RESTART_AUTONEG (1 << 9 )
frankvnk 0:636056c0b5e1 314 #define DM9161_DUPLEX_MODE (1 << 8 )
frankvnk 0:636056c0b5e1 315 #define DM9161_COLLISION_TEST (1 << 7 )
frankvnk 0:636056c0b5e1 316
frankvnk 0:636056c0b5e1 317 //--Bit definitions: DM9161_BMSR
frankvnk 0:636056c0b5e1 318 #define DM9161_100BASE_T4 (1 << 15)
frankvnk 0:636056c0b5e1 319 #define DM9161_100BASE_TX_FD (1 << 14)
frankvnk 8:4c3db9231e3f 320 #define DM9161_100BASE_TX_HD (1 << 13)
frankvnk 0:636056c0b5e1 321 #define DM9161_10BASE_T_FD (1 << 12)
frankvnk 0:636056c0b5e1 322 #define DM9161_10BASE_T_HD (1 << 11)
frankvnk 0:636056c0b5e1 323 #define DM9161_MF_PREAMB_SUPPR (1 << 6 )
frankvnk 0:636056c0b5e1 324 #define DM9161_AUTONEG_COMP (1 << 5 )
frankvnk 0:636056c0b5e1 325 #define DM9161_REMOTE_FAULT (1 << 4 )
frankvnk 0:636056c0b5e1 326 #define DM9161_AUTONEG_ABILITY (1 << 3 )
frankvnk 0:636056c0b5e1 327 #define DM9161_LINK_STATUS (1 << 2 )
frankvnk 0:636056c0b5e1 328 #define DM9161_JABBER_DETECT (1 << 1 )
frankvnk 0:636056c0b5e1 329 #define DM9161_EXTEND_CAPAB (1 << 0 )
frankvnk 0:636056c0b5e1 330
frankvnk 0:636056c0b5e1 331 //--Bit definitions: DM9161_ANAR, DM9161_ANLPAR
frankvnk 0:636056c0b5e1 332 #define DM9161_NP (1 << 15)
frankvnk 0:636056c0b5e1 333 #define DM9161_ACK (1 << 14)
frankvnk 0:636056c0b5e1 334 #define DM9161_RF (1 << 13)
frankvnk 0:636056c0b5e1 335 #define DM9161_FCS (1 << 10)
frankvnk 0:636056c0b5e1 336 #define DM9161_T4 (1 << 9 )
frankvnk 0:636056c0b5e1 337 #define DM9161_TX_FDX (1 << 8 )
frankvnk 0:636056c0b5e1 338 #define DM9161_TX_HDX (1 << 7 )
frankvnk 0:636056c0b5e1 339 #define DM9161_10_FDX (1 << 6 )
frankvnk 0:636056c0b5e1 340 #define DM9161_10_HDX (1 << 5 )
frankvnk 0:636056c0b5e1 341 #define DM9161_AN_IEEE_802_3 0x0001
frankvnk 0:636056c0b5e1 342
frankvnk 0:636056c0b5e1 343 //--Bit definitions: DM9161_ANER
frankvnk 0:636056c0b5e1 344 #define DM9161_PDF (1 << 4 )
frankvnk 0:636056c0b5e1 345 #define DM9161_LP_NP_ABLE (1 << 3 )
frankvnk 0:636056c0b5e1 346 #define DM9161_NP_ABLE (1 << 2 )
frankvnk 0:636056c0b5e1 347 #define DM9161_PAGE_RX (1 << 1 )
frankvnk 0:636056c0b5e1 348 #define DM9161_LP_AN_ABLE (1 << 0 )
frankvnk 0:636056c0b5e1 349
frankvnk 0:636056c0b5e1 350 //--Bit definitions: DM9161_DSCR
frankvnk 0:636056c0b5e1 351 #define DM9161_BP4B5B (1 << 15)
frankvnk 0:636056c0b5e1 352 #define DM9161_BP_SCR (1 << 14)
frankvnk 0:636056c0b5e1 353 #define DM9161_BP_ALIGN (1 << 13)
frankvnk 0:636056c0b5e1 354 #define DM9161_BP_ADPOK (1 << 12)
frankvnk 0:636056c0b5e1 355 #define DM9161_REPEATER (1 << 11)
frankvnk 0:636056c0b5e1 356 #define DM9161_TX (1 << 10)
frankvnk 0:636056c0b5e1 357 #define DM9161_RMII_ENABLE (1 << 8 )
frankvnk 0:636056c0b5e1 358 #define DM9161_F_LINK_100 (1 << 7 )
frankvnk 0:636056c0b5e1 359 #define DM9161_SPLED_CTL (1 << 6 )
frankvnk 0:636056c0b5e1 360 #define DM9161_COLLED_CTL (1 << 5 )
frankvnk 0:636056c0b5e1 361 #define DM9161_RPDCTR_EN (1 << 4 )
frankvnk 0:636056c0b5e1 362 #define DM9161_SM_RST (1 << 3 )
frankvnk 0:636056c0b5e1 363 #define DM9161_MFP SC (1 << 2 )
frankvnk 0:636056c0b5e1 364 #define DM9161_SLEEP (1 << 1 )
frankvnk 0:636056c0b5e1 365 #define DM9161_RLOUT (1 << 0 )
frankvnk 0:636056c0b5e1 366
frankvnk 0:636056c0b5e1 367 //--Bit definitions: DM9161_DSCSR
frankvnk 0:636056c0b5e1 368 #define DM9161_100FDX (1 << 15)
frankvnk 0:636056c0b5e1 369 #define DM9161_100HDX (1 << 14)
frankvnk 0:636056c0b5e1 370 #define DM9161_10FDX (1 << 13)
frankvnk 0:636056c0b5e1 371 #define DM9161_10HDX (1 << 12)
frankvnk 0:636056c0b5e1 372
frankvnk 0:636056c0b5e1 373 //--Bit definitions: DM9161_10BTCSR
frankvnk 0:636056c0b5e1 374 #define DM9161_LP_EN (1 << 14)
frankvnk 0:636056c0b5e1 375 #define DM9161_HBE (1 << 13)
frankvnk 0:636056c0b5e1 376 #define DM9161_SQUELCH (1 << 12)
frankvnk 0:636056c0b5e1 377 #define DM9161_JABEN (1 << 11)
frankvnk 0:636056c0b5e1 378 #define DM9161_10BT_SER (1 << 10)
frankvnk 0:636056c0b5e1 379 #define DM9161_POLR (1 << 0 )
frankvnk 0:636056c0b5e1 380
frankvnk 0:636056c0b5e1 381 //--Bit definitions: DM9161_MDINTR
frankvnk 0:636056c0b5e1 382 #define DM9161_INTR_PEND (1 << 15)
frankvnk 0:636056c0b5e1 383 #define DM9161_FDX_MASK (1 << 11)
frankvnk 0:636056c0b5e1 384 #define DM9161_SPD_MASK (1 << 10)
frankvnk 0:636056c0b5e1 385 #define DM9161_LINK_MASK (1 << 9 )
frankvnk 0:636056c0b5e1 386 #define DM9161_INTR_MASK (1 << 8 )
frankvnk 0:636056c0b5e1 387 #define DM9161_FDX_CHANGE (1 << 4 )
frankvnk 0:636056c0b5e1 388 #define DM9161_SPD_CHANGE (1 << 3 )
frankvnk 0:636056c0b5e1 389 #define DM9161_LINK_CHANGE (1 << 2 )
frankvnk 0:636056c0b5e1 390 #define DM9161_INTR_STATUS (1 << 0 )
frankvnk 0:636056c0b5e1 391
frankvnk 0:636056c0b5e1 392
frankvnk 0:636056c0b5e1 393 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
frankvnk 0:636056c0b5e1 394 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
frankvnk 0:636056c0b5e1 395 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
frankvnk 0:636056c0b5e1 396 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
frankvnk 0:636056c0b5e1 397 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
frankvnk 0:636056c0b5e1 398
frankvnk 0:636056c0b5e1 399 #define DM9161_DEF_ADR 0x1300 /* Default PHY device address DM9161 */
frankvnk 0:636056c0b5e1 400 #define DM9161_ID 0x0181B8A0 /* DM9161 PHY Identifier */
frankvnk 0:636056c0b5e1 401
frankvnk 0:636056c0b5e1 402
frankvnk 0:636056c0b5e1 403
frankvnk 0:636056c0b5e1 404 void Init_EthMAC(void);
frankvnk 0:636056c0b5e1 405 unsigned short ReadFrameBE_EthMAC(void);
frankvnk 0:636056c0b5e1 406 void CopyToFrame_EthMAC(void *Source, unsigned int Size);
frankvnk 0:636056c0b5e1 407 void CopyFromFrame_EthMAC(void *Dest, unsigned short Size);
frankvnk 0:636056c0b5e1 408 void DummyReadFrame_EthMAC(unsigned short Size);
frankvnk 0:636056c0b5e1 409 void RequestSend(unsigned short FrameSize);
frankvnk 0:636056c0b5e1 410 unsigned int Rdy4Tx(void);
frankvnk 0:636056c0b5e1 411 unsigned short StartReadingFrame(void);
frankvnk 0:636056c0b5e1 412 void StopReadingFrame(void);
frankvnk 0:636056c0b5e1 413 unsigned int CheckIfFrameReceived(void);
frankvnk 0:636056c0b5e1 414
frankvnk 0:636056c0b5e1 415 #endif
frankvnk 0:636056c0b5e1 416