Diff: rtx/TARGET_CORTEX_A/RTX_Conf_CA.c

Revision:

68:d3d0e710b443

Parent:

66:721c3a93a7b8

Child:

69:94c39314568d

--- a/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c	Fri Feb 27 10:00:40 2015 +0000
+++ b/rtx/TARGET_CORTEX_A/RTX_Conf_CA.c	Thu Mar 12 14:31:19 2015 +0000
@@ -15,19 +15,19 @@
  *  - Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- *  - Neither the name of ARM  nor the names of its contributors may be used 
- *    to endorse or promote products derived from this software without 
+ *  - Neither the name of ARM  nor the names of its contributors may be used
+ *    to endorse or promote products derived from this software without
  *    specific prior written permission.
  *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *---------------------------------------------------------------------------*/
@@ -85,8 +85,8 @@
  #define OS_STKCHECK    1
 #endif
 
-// <o>Processor mode for thread execution 
-//   <0=> Unprivileged mode 
+// <o>Processor mode for thread execution
+//   <0=> Unprivileged mode
 //   <1=> Privileged mode
 // <i> Default: Privileged mode
 #ifndef OS_RUNPRIV
@@ -195,7 +195,7 @@
 
 // Standard library system mutexes
 // ===============================
-//  Define max. number system mutexes that are used to protect 
+//  Define max. number system mutexes that are used to protect
 //  the arm standard runtime library. For microlib they are not used.
 #ifndef OS_MUTEXCNT
  #define OS_MUTEXCNT    12
@@ -251,7 +251,7 @@
 #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
 #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
 
-typedef enum 
+typedef enum
 {
     IRQ_SGI0       = 0,
     IRQ_OSTMI0TINT = 134
@@ -269,7 +269,7 @@
 int os_tick_init (void) {
 #ifdef TARGET_RZ_A1H
   CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */
-  
+
   OSTM0TT   = 0x1;    /* Stop the counter and clears the OSTM0TE bit.     */
   OSTM0CTL  = 0x1;    /* Interval timer mode. Interrupt enabled  */