Thomas Byrne / mbed-src-stm32f030k6

Public fork of mbed-src to add generic stm32f030k6 target

Fork of mbed-src by mbed official

targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c@489:119543c9f674, 2015-03-12 (annotated)

Committer:
mbed_official
Date:
Thu Mar 12 14:30:49 2015 +0000
Revision:
489:119543c9f674
Parent:
445:3312ed629f01
Child:
499:d0e9408fd176
Synchronized with git revision 051854181516992fb498d51f9ee6e70cbad9e083



Full URL: https://github.com/mbedmicro/mbed/commit/051854181516992fb498d51f9ee6e70cbad9e083/



Fix ksdk mcu HAL - stopbit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 445:3312ed629f01 1 /* mbed Microcontroller Library
mbed_official 445:3312ed629f01 2 * Copyright (c) 2006-2015 ARM Limited
mbed_official 445:3312ed629f01 3 *
mbed_official 445:3312ed629f01 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 445:3312ed629f01 5 * you may not use this file except in compliance with the License.
mbed_official 445:3312ed629f01 6 * You may obtain a copy of the License at
mbed_official 445:3312ed629f01 7 *
mbed_official 445:3312ed629f01 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 445:3312ed629f01 9 *
mbed_official 445:3312ed629f01 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 445:3312ed629f01 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 445:3312ed629f01 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 445:3312ed629f01 13 * See the License for the specific language governing permissions and
mbed_official 445:3312ed629f01 14 * limitations under the License.
mbed_official 445:3312ed629f01 15 */
mbed_official 445:3312ed629f01 16 #include "sleep_api.h"
mbed_official 445:3312ed629f01 17 #include "cmsis.h"
mbed_official 445:3312ed629f01 18
mbed_official 445:3312ed629f01 19 //Normal wait mode
mbed_official 445:3312ed629f01 20 void sleep(void)
mbed_official 445:3312ed629f01 21 {
mbed_official 445:3312ed629f01 22 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
mbed_official 445:3312ed629f01 23
mbed_official 445:3312ed629f01 24 //Normal sleep mode for ARM core:
mbed_official 445:3312ed629f01 25 SCB->SCR = 0;
mbed_official 445:3312ed629f01 26 __WFI();
mbed_official 445:3312ed629f01 27 }
mbed_official 445:3312ed629f01 28
mbed_official 445:3312ed629f01 29 //Very low-power stop mode
mbed_official 445:3312ed629f01 30 void deepsleep(void)
mbed_official 445:3312ed629f01 31 {
mbed_official 445:3312ed629f01 32 //Check if PLL/FLL is enabled:
mbed_official 445:3312ed629f01 33 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
mbed_official 445:3312ed629f01 34
mbed_official 445:3312ed629f01 35 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
mbed_official 445:3312ed629f01 36 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
mbed_official 445:3312ed629f01 37
mbed_official 445:3312ed629f01 38 //Deep sleep for ARM core:
mbed_official 445:3312ed629f01 39 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
mbed_official 445:3312ed629f01 40
mbed_official 445:3312ed629f01 41 __WFI();
mbed_official 445:3312ed629f01 42 //Switch back to PLL as clock source if needed
mbed_official 445:3312ed629f01 43 //The interrupt that woke up the device will run at reduced speed
mbed_official 445:3312ed629f01 44 if (PLL_FLL_en) {
mbed_official 489:119543c9f674 45
mbed_official 489:119543c9f674 46 #if defined (TARGET_K20D50M)
mbed_official 445:3312ed629f01 47 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
mbed_official 445:3312ed629f01 48 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
mbed_official 445:3312ed629f01 49 MCG->C1 &= ~MCG_C1_CLKS_MASK;
mbed_official 489:119543c9f674 50 #else
mbed_official 489:119543c9f674 51 // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0
mbed_official 489:119543c9f674 52 MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK;
mbed_official 489:119543c9f674 53 // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0
mbed_official 489:119543c9f674 54 MCG->C6 = MCG_C6_VDIV0(0);
mbed_official 489:119543c9f674 55 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running
mbed_official 489:119543c9f674 56 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
mbed_official 489:119543c9f674 57 // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3
mbed_official 489:119543c9f674 58 MCG->C5 = MCG_C5_PRDIV0(5);
mbed_official 489:119543c9f674 59 // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3
mbed_official 489:119543c9f674 60 MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3);
mbed_official 489:119543c9f674 61 while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output
mbed_official 489:119543c9f674 62 while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL
mbed_official 489:119543c9f674 63 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
mbed_official 489:119543c9f674 64 // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0
mbed_official 489:119543c9f674 65 MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;;
mbed_official 489:119543c9f674 66 while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected
mbed_official 489:119543c9f674 67 while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked
mbed_official 489:119543c9f674 68 #endif
mbed_official 445:3312ed629f01 69 }
mbed_official 445:3312ed629f01 70 }