Emilio Monti
/
mbed-KL25Z
Important changes to repositories hosted on mbed.com
Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.
To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.
It is also possible to export all your personal repositories from the account settings page.
Embed:
(wiki syntax)
Show/hide line numbers
core_cm0plus.h
Go to the documentation of this file.
00001 /**************************************************************************//** 00002 * @file core_cm0plus.h 00003 * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File 00004 * @version V3.02 00005 * @date 05. November 2012 00006 * 00007 * @note 00008 * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 00009 * 00010 * @par 00011 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00012 * processor based microcontrollers. This file can be freely distributed 00013 * within development tools that are supporting such ARM based processors. 00014 * 00015 * @par 00016 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00017 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00018 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00019 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00020 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00021 * 00022 ******************************************************************************/ 00023 #if defined ( __ICCARM__ ) 00024 #pragma system_include /* treat file as system include file for MISRA check */ 00025 #endif 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 #ifndef __CORE_CM0PLUS_H_GENERIC 00032 #define __CORE_CM0PLUS_H_GENERIC 00033 00034 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00035 CMSIS violates the following MISRA-C:2004 rules: 00036 00037 \li Required Rule 8.5, object/function definition in header file.<br> 00038 Function definitions in header files are used to allow 'inlining'. 00039 00040 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00041 Unions are used for effective representation of core registers. 00042 00043 \li Advisory Rule 19.7, Function-like macro defined.<br> 00044 Function-like macros are used to allow more efficient code. 00045 */ 00046 00047 00048 /******************************************************************************* 00049 * CMSIS definitions 00050 ******************************************************************************/ 00051 /** \ingroup Cortex-M0+ 00052 @{ 00053 */ 00054 00055 /* CMSIS CM0P definitions */ 00056 #define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00057 #define __CM0PLUS_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ 00058 #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ 00059 __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ 00060 00061 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00062 00063 00064 #if defined ( __CC_ARM ) 00065 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00066 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00067 #define __STATIC_INLINE static __inline 00068 00069 #elif defined ( __ICCARM__ ) 00070 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00071 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00072 #define __STATIC_INLINE static inline 00073 00074 #elif defined ( __GNUC__ ) 00075 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00076 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00077 #define __STATIC_INLINE static inline 00078 00079 #elif defined ( __TASKING__ ) 00080 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00081 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00082 #define __STATIC_INLINE static inline 00083 00084 #endif 00085 00086 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00087 */ 00088 #define __FPU_USED 0 00089 00090 #if defined ( __CC_ARM ) 00091 #if defined __TARGET_FPU_VFP 00092 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00093 #endif 00094 00095 #elif defined ( __ICCARM__ ) 00096 #if defined __ARMVFP__ 00097 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00098 #endif 00099 00100 #elif defined ( __GNUC__ ) 00101 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00103 #endif 00104 00105 #elif defined ( __TASKING__ ) 00106 #if defined __FPU_VFP__ 00107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00108 #endif 00109 #endif 00110 00111 #include <stdint.h> /* standard types definitions */ 00112 #include <core_cmInstr.h> /* Core Instruction Access */ 00113 #include <core_cmFunc.h> /* Core Function Access */ 00114 00115 #endif /* __CORE_CM0PLUS_H_GENERIC */ 00116 00117 #ifndef __CMSIS_GENERIC 00118 00119 #ifndef __CORE_CM0PLUS_H_DEPENDANT 00120 #define __CORE_CM0PLUS_H_DEPENDANT 00121 00122 /* check device defines and use defaults */ 00123 #if defined __CHECK_DEVICE_DEFINES 00124 #ifndef __CM0PLUS_REV 00125 #define __CM0PLUS_REV 0x0000 00126 #warning "__CM0PLUS_REV not defined in device header file; using default!" 00127 #endif 00128 00129 #ifndef __MPU_PRESENT 00130 #define __MPU_PRESENT 0 00131 #warning "__MPU_PRESENT not defined in device header file; using default!" 00132 #endif 00133 00134 #ifndef __VTOR_PRESENT 00135 #define __VTOR_PRESENT 0 00136 #warning "__VTOR_PRESENT not defined in device header file; using default!" 00137 #endif 00138 00139 #ifndef __NVIC_PRIO_BITS 00140 #define __NVIC_PRIO_BITS 2 00141 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00142 #endif 00143 00144 #ifndef __Vendor_SysTickConfig 00145 #define __Vendor_SysTickConfig 0 00146 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00147 #endif 00148 #endif 00149 00150 /* IO definitions (access restrictions to peripheral registers) */ 00151 /** 00152 \defgroup CMSIS_glob_defs CMSIS Global Defines 00153 00154 <strong>IO Type Qualifiers</strong> are used 00155 \li to specify the access to peripheral variables. 00156 \li for automatic generation of peripheral register debug information. 00157 */ 00158 #ifdef __cplusplus 00159 #define __I volatile /*!< Defines 'read only' permissions */ 00160 #else 00161 #define __I volatile const /*!< Defines 'read only' permissions */ 00162 #endif 00163 #define __O volatile /*!< Defines 'write only' permissions */ 00164 #define __IO volatile /*!< Defines 'read / write' permissions */ 00165 00166 /*@} end of group Cortex-M0+ */ 00167 00168 00169 00170 /******************************************************************************* 00171 * Register Abstraction 00172 Core Register contain: 00173 - Core Register 00174 - Core NVIC Register 00175 - Core SCB Register 00176 - Core SysTick Register 00177 - Core MPU Register 00178 ******************************************************************************/ 00179 /** \defgroup CMSIS_core_register Defines and Type Definitions 00180 \brief Type definitions and defines for Cortex-M processor based devices. 00181 */ 00182 00183 /** \ingroup CMSIS_core_register 00184 \defgroup CMSIS_CORE Status and Control Registers 00185 \brief Core Register type definitions. 00186 @{ 00187 */ 00188 00189 /** \brief Union type to access the Application Program Status Register (APSR). 00190 */ 00191 typedef union 00192 { 00193 struct 00194 { 00195 #if (__CORTEX_M != 0x04) 00196 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00197 #else 00198 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00199 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00200 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00201 #endif 00202 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00203 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00204 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00205 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00206 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00207 } b; /*!< Structure used for bit access */ 00208 uint32_t w ; /*!< Type used for word access */ 00209 } APSR_Type; 00210 00211 00212 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00213 */ 00214 typedef union 00215 { 00216 struct 00217 { 00218 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00219 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00220 } b; /*!< Structure used for bit access */ 00221 uint32_t w ; /*!< Type used for word access */ 00222 } IPSR_Type; 00223 00224 00225 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00226 */ 00227 typedef union 00228 { 00229 struct 00230 { 00231 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00232 #if (__CORTEX_M != 0x04) 00233 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00234 #else 00235 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00236 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00237 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00238 #endif 00239 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00240 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00241 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00242 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00243 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00244 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00245 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00246 } b; /*!< Structure used for bit access */ 00247 uint32_t w ; /*!< Type used for word access */ 00248 } xPSR_Type; 00249 00250 00251 /** \brief Union type to access the Control Registers (CONTROL). 00252 */ 00253 typedef union 00254 { 00255 struct 00256 { 00257 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00258 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00259 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00260 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00261 } b; /*!< Structure used for bit access */ 00262 uint32_t w ; /*!< Type used for word access */ 00263 } CONTROL_Type; 00264 00265 /*@} end of group CMSIS_CORE */ 00266 00267 00268 /** \ingroup CMSIS_core_register 00269 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00270 \brief Type definitions for the NVIC Registers 00271 @{ 00272 */ 00273 00274 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00275 */ 00276 typedef struct 00277 { 00278 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00279 uint32_t RESERVED0[31]; 00280 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00281 uint32_t RSERVED1[31]; 00282 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00283 uint32_t RESERVED2[31]; 00284 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00285 uint32_t RESERVED3[31]; 00286 uint32_t RESERVED4[64]; 00287 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00288 } NVIC_Type; 00289 00290 /*@} end of group CMSIS_NVIC */ 00291 00292 00293 /** \ingroup CMSIS_core_register 00294 \defgroup CMSIS_SCB System Control Block (SCB) 00295 \brief Type definitions for the System Control Block Registers 00296 @{ 00297 */ 00298 00299 /** \brief Structure type to access the System Control Block (SCB). 00300 */ 00301 typedef struct 00302 { 00303 __I uint32_t CPUID ; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00304 __IO uint32_t ICSR ; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00305 #if (__VTOR_PRESENT == 1) 00306 __IO uint32_t VTOR ; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00307 #else 00308 uint32_t RESERVED0; 00309 #endif 00310 __IO uint32_t AIRCR ; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00311 __IO uint32_t SCR ; /*!< Offset: 0x010 (R/W) System Control Register */ 00312 __IO uint32_t CCR ; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00313 uint32_t RESERVED1; 00314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00315 __IO uint32_t SHCSR ; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00316 } SCB_Type; 00317 00318 /* SCB CPUID Register Definitions */ 00319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00321 00322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00324 00325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00327 00328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00330 00331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00333 00334 /* SCB Interrupt Control State Register Definitions */ 00335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00337 00338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00340 00341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00343 00344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00346 00347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00349 00350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00352 00353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00355 00356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00358 00359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00361 00362 #if (__VTOR_PRESENT == 1) 00363 /* SCB Interrupt Control State Register Definitions */ 00364 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00365 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00366 #endif 00367 00368 /* SCB Application Interrupt and Reset Control Register Definitions */ 00369 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00370 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00371 00372 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00373 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00374 00375 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00376 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00377 00378 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00379 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00380 00381 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00382 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00383 00384 /* SCB System Control Register Definitions */ 00385 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00386 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00387 00388 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00389 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00390 00391 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00392 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00393 00394 /* SCB Configuration Control Register Definitions */ 00395 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00396 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00397 00398 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00399 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00400 00401 /* SCB System Handler Control and State Register Definitions */ 00402 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00403 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00404 00405 /*@} end of group CMSIS_SCB */ 00406 00407 00408 /** \ingroup CMSIS_core_register 00409 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00410 \brief Type definitions for the System Timer Registers. 00411 @{ 00412 */ 00413 00414 /** \brief Structure type to access the System Timer (SysTick). 00415 */ 00416 typedef struct 00417 { 00418 __IO uint32_t CTRL ; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00419 __IO uint32_t LOAD ; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00420 __IO uint32_t VAL ; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00421 __I uint32_t CALIB ; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00422 } SysTick_Type; 00423 00424 /* SysTick Control / Status Register Definitions */ 00425 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00426 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00427 00428 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00429 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00430 00431 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00432 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00433 00434 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00435 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00436 00437 /* SysTick Reload Register Definitions */ 00438 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00439 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00440 00441 /* SysTick Current Register Definitions */ 00442 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00443 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00444 00445 /* SysTick Calibration Register Definitions */ 00446 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00447 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00448 00449 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00450 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00451 00452 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00453 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ 00454 00455 /*@} end of group CMSIS_SysTick */ 00456 00457 #if (__MPU_PRESENT == 1) 00458 /** \ingroup CMSIS_core_register 00459 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00460 \brief Type definitions for the Memory Protection Unit (MPU) 00461 @{ 00462 */ 00463 00464 /** \brief Structure type to access the Memory Protection Unit (MPU). 00465 */ 00466 typedef struct 00467 { 00468 __I uint32_t TYPE ; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00469 __IO uint32_t CTRL ; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00470 __IO uint32_t RNR ; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00471 __IO uint32_t RBAR ; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00472 __IO uint32_t RASR ; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00473 } MPU_Type; 00474 00475 /* MPU Type Register */ 00476 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 00477 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00478 00479 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 00480 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00481 00482 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 00483 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 00484 00485 /* MPU Control Register */ 00486 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 00487 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00488 00489 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 00490 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00491 00492 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 00493 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 00494 00495 /* MPU Region Number Register */ 00496 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 00497 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 00498 00499 /* MPU Region Base Address Register */ 00500 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 00501 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00502 00503 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 00504 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00505 00506 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 00507 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 00508 00509 /* MPU Region Attribute and Size Register */ 00510 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 00511 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00512 00513 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 00514 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00515 00516 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 00517 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00518 00519 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 00520 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00521 00522 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 00523 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00524 00525 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 00526 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00527 00528 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 00529 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00530 00531 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 00532 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00533 00534 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 00535 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00536 00537 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 00538 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 00539 00540 /*@} end of group CMSIS_MPU */ 00541 #endif 00542 00543 00544 /** \ingroup CMSIS_core_register 00545 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00546 \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) 00547 are only accessible over DAP and not via processor. Therefore 00548 they are not covered by the Cortex-M0 header file. 00549 @{ 00550 */ 00551 /*@} end of group CMSIS_CoreDebug */ 00552 00553 00554 /** \ingroup CMSIS_core_register 00555 \defgroup CMSIS_core_base Core Definitions 00556 \brief Definitions for base addresses, unions, and structures. 00557 @{ 00558 */ 00559 00560 /* Memory mapping of Cortex-M0+ Hardware */ 00561 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00562 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00563 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00564 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00565 00566 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00567 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00568 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00569 00570 #if (__MPU_PRESENT == 1) 00571 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00572 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00573 #endif 00574 00575 /*@} */ 00576 00577 00578 00579 /******************************************************************************* 00580 * Hardware Abstraction Layer 00581 Core Function Interface contains: 00582 - Core NVIC Functions 00583 - Core SysTick Functions 00584 - Core Register Access Functions 00585 ******************************************************************************/ 00586 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00587 */ 00588 00589 00590 00591 /* ########################## NVIC functions #################################### */ 00592 /** \ingroup CMSIS_Core_FunctionInterface 00593 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00594 \brief Functions that manage interrupts and exceptions via the NVIC. 00595 @{ 00596 */ 00597 00598 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00599 /* The following MACROS handle generation of the register offset and byte masks */ 00600 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00601 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00602 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00603 00604 00605 /** \brief Enable External Interrupt 00606 00607 The function enables a device-specific interrupt in the NVIC interrupt controller. 00608 00609 \param [in] IRQn External interrupt number. Value cannot be negative. 00610 */ 00611 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00612 { 00613 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00614 } 00615 00616 00617 /** \brief Disable External Interrupt 00618 00619 The function disables a device-specific interrupt in the NVIC interrupt controller. 00620 00621 \param [in] IRQn External interrupt number. Value cannot be negative. 00622 */ 00623 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00624 { 00625 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00626 } 00627 00628 00629 /** \brief Get Pending Interrupt 00630 00631 The function reads the pending register in the NVIC and returns the pending bit 00632 for the specified interrupt. 00633 00634 \param [in] IRQn Interrupt number. 00635 00636 \return 0 Interrupt status is not pending. 00637 \return 1 Interrupt status is pending. 00638 */ 00639 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00640 { 00641 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00642 } 00643 00644 00645 /** \brief Set Pending Interrupt 00646 00647 The function sets the pending bit of an external interrupt. 00648 00649 \param [in] IRQn Interrupt number. Value cannot be negative. 00650 */ 00651 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00652 { 00653 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00654 } 00655 00656 00657 /** \brief Clear Pending Interrupt 00658 00659 The function clears the pending bit of an external interrupt. 00660 00661 \param [in] IRQn External interrupt number. Value cannot be negative. 00662 */ 00663 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00664 { 00665 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00666 } 00667 00668 00669 /** \brief Set Interrupt Priority 00670 00671 The function sets the priority of an interrupt. 00672 00673 \note The priority cannot be set for every core interrupt. 00674 00675 \param [in] IRQn Interrupt number. 00676 \param [in] priority Priority to set. 00677 */ 00678 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00679 { 00680 if(IRQn < 0) { 00681 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00682 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00683 else { 00684 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00685 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00686 } 00687 00688 00689 /** \brief Get Interrupt Priority 00690 00691 The function reads the priority of an interrupt. The interrupt 00692 number can be positive to specify an external (device specific) 00693 interrupt, or negative to specify an internal (core) interrupt. 00694 00695 00696 \param [in] IRQn Interrupt number. 00697 \return Interrupt Priority. Value is aligned automatically to the implemented 00698 priority bits of the microcontroller. 00699 */ 00700 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00701 { 00702 00703 if(IRQn < 0) { 00704 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00705 else { 00706 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00707 } 00708 00709 00710 /** \brief System Reset 00711 00712 The function initiates a system reset request to reset the MCU. 00713 */ 00714 __STATIC_INLINE void NVIC_SystemReset(void) 00715 { 00716 __DSB(); /* Ensure all outstanding memory accesses included 00717 buffered write are completed before reset */ 00718 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00719 SCB_AIRCR_SYSRESETREQ_Msk); 00720 __DSB(); /* Ensure completion of memory access */ 00721 while(1); /* wait until reset */ 00722 } 00723 00724 /*@} end of CMSIS_Core_NVICFunctions */ 00725 00726 00727 00728 /* ################################## SysTick function ############################################ */ 00729 /** \ingroup CMSIS_Core_FunctionInterface 00730 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00731 \brief Functions that configure the System. 00732 @{ 00733 */ 00734 00735 #if (__Vendor_SysTickConfig == 0) 00736 00737 /** \brief System Tick Configuration 00738 00739 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00740 Counter is in free running mode to generate periodic interrupts. 00741 00742 \param [in] ticks Number of ticks between two interrupts. 00743 00744 \return 0 Function succeeded. 00745 \return 1 Function failed. 00746 00747 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00748 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00749 must contain a vendor-specific implementation of this function. 00750 00751 */ 00752 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00753 { 00754 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00755 00756 SysTick->LOAD = ticks - 1; /* set reload register */ 00757 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00758 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00759 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00760 SysTick_CTRL_TICKINT_Msk | 00761 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00762 return (0); /* Function successful */ 00763 } 00764 00765 #endif 00766 00767 /*@} end of CMSIS_Core_SysTickFunctions */ 00768 00769 00770 00771 00772 #endif /* __CORE_CM0PLUS_H_DEPENDANT */ 00773 00774 #endif /* __CMSIS_GENERIC */ 00775 00776 #ifdef __cplusplus 00777 } 00778 #endif
Generated on Wed Jul 13 2022 13:18:34 by
1.7.2