Eli Hughes
V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
SCB_Type Struct Reference
[System Control Block (SCB)]
Structure type to access the System Control Block (SCB). More...
#include <core_cm0.h>
Data Fields | |
| __I uint32_t | CPUID |
| __IO uint32_t | ICSR |
| __IO uint32_t | AIRCR |
| __IO uint32_t | SCR |
| __IO uint32_t | CCR |
| __IO uint32_t | SHP [2] |
| __IO uint32_t | SHCSR |
Detailed Description
Structure type to access the System Control Block (SCB).
Definition at line 325 of file core_cm0.h.
Field Documentation
| __IO uint32_t AIRCR |
Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
Definition at line 330 of file core_cm0.h.
| __IO uint32_t CCR |
Offset: 0x014 (R/W) Configuration Control Register
Definition at line 332 of file core_cm0.h.
| __I uint32_t CPUID |
Offset: 0x000 (R/ ) CPUID Base Register
Definition at line 327 of file core_cm0.h.
| __IO uint32_t ICSR |
Offset: 0x004 (R/W) Interrupt Control and State Register
Definition at line 328 of file core_cm0.h.
| __IO uint32_t SCR |
Offset: 0x010 (R/W) System Control Register
Definition at line 331 of file core_cm0.h.
| __IO uint32_t SHCSR |
Offset: 0x024 (R/W) System Handler Control and State Register
Definition at line 335 of file core_cm0.h.
| __IO uint32_t SHP[2] |
Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED
Definition at line 334 of file core_cm0.h.
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