Eli Hughes
V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
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core_sc000.h
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00001 /**************************************************************************//** 00002 * @file core_sc000.h 00003 * @brief CMSIS SC000 Core Peripheral Access Layer Header File 00004 * @version V3.30 00005 * @date 06. May 2014 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2014 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #if defined ( __ICCARM__ ) 00039 #pragma system_include /* treat file as system include file for MISRA check */ 00040 #endif 00041 00042 #ifndef __CORE_SC000_H_GENERIC 00043 #define __CORE_SC000_H_GENERIC 00044 00045 #ifdef __cplusplus 00046 extern "C" { 00047 #endif 00048 00049 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00050 CMSIS violates the following MISRA-C:2004 rules: 00051 00052 \li Required Rule 8.5, object/function definition in header file.<br> 00053 Function definitions in header files are used to allow 'inlining'. 00054 00055 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00056 Unions are used for effective representation of core registers. 00057 00058 \li Advisory Rule 19.7, Function-like macro defined.<br> 00059 Function-like macros are used to allow more efficient code. 00060 */ 00061 00062 00063 /******************************************************************************* 00064 * CMSIS definitions 00065 ******************************************************************************/ 00066 /** \ingroup SC000 00067 @{ 00068 */ 00069 00070 /* CMSIS SC000 definitions */ 00071 #define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00072 #define __SC000_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ 00073 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ 00074 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00075 00076 #define __CORTEX_SC (000) /*!< Cortex secure core */ 00077 00078 00079 #if defined ( __CC_ARM ) 00080 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00081 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00082 #define __STATIC_INLINE static __inline 00083 00084 #elif defined ( __GNUC__ ) 00085 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00086 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00087 #define __STATIC_INLINE static inline 00088 00089 #elif defined ( __ICCARM__ ) 00090 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00091 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00092 #define __STATIC_INLINE static inline 00093 00094 #elif defined ( __TMS470__ ) 00095 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ 00096 #define __STATIC_INLINE static inline 00097 00098 #elif defined ( __TASKING__ ) 00099 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00101 #define __STATIC_INLINE static inline 00102 00103 #elif defined ( __CSMC__ ) /* Cosmic */ 00104 #define __packed 00105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ 00106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ 00107 #define __STATIC_INLINE static inline 00108 00109 #endif 00110 00111 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00112 */ 00113 #define __FPU_USED 0 00114 00115 #if defined ( __CC_ARM ) 00116 #if defined __TARGET_FPU_VFP 00117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00118 #endif 00119 00120 #elif defined ( __GNUC__ ) 00121 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00122 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00123 #endif 00124 00125 #elif defined ( __ICCARM__ ) 00126 #if defined __ARMVFP__ 00127 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00128 #endif 00129 00130 #elif defined ( __TMS470__ ) 00131 #if defined __TI__VFP_SUPPORT____ 00132 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00133 #endif 00134 00135 #elif defined ( __TASKING__ ) 00136 #if defined __FPU_VFP__ 00137 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00138 #endif 00139 00140 #elif defined ( __CSMC__ ) /* Cosmic */ 00141 #if ( __CSMC__ & 0x400) // FPU present for parser 00142 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00143 #endif 00144 #endif 00145 00146 #include <stdint.h> /* standard types definitions */ 00147 #include <core_cmInstr.h> /* Core Instruction Access */ 00148 #include <core_cmFunc.h> /* Core Function Access */ 00149 00150 #endif /* __CORE_SC000_H_GENERIC */ 00151 00152 #ifndef __CMSIS_GENERIC 00153 00154 #ifndef __CORE_SC000_H_DEPENDANT 00155 #define __CORE_SC000_H_DEPENDANT 00156 00157 /* check device defines and use defaults */ 00158 #if defined __CHECK_DEVICE_DEFINES 00159 #ifndef __SC000_REV 00160 #define __SC000_REV 0x0000 00161 #warning "__SC000_REV not defined in device header file; using default!" 00162 #endif 00163 00164 #ifndef __MPU_PRESENT 00165 #define __MPU_PRESENT 0 00166 #warning "__MPU_PRESENT not defined in device header file; using default!" 00167 #endif 00168 00169 #ifndef __NVIC_PRIO_BITS 00170 #define __NVIC_PRIO_BITS 2 00171 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00172 #endif 00173 00174 #ifndef __Vendor_SysTickConfig 00175 #define __Vendor_SysTickConfig 0 00176 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00177 #endif 00178 #endif 00179 00180 /* IO definitions (access restrictions to peripheral registers) */ 00181 /** 00182 \defgroup CMSIS_glob_defs CMSIS Global Defines 00183 00184 <strong>IO Type Qualifiers</strong> are used 00185 \li to specify the access to peripheral variables. 00186 \li for automatic generation of peripheral register debug information. 00187 */ 00188 #ifdef __cplusplus 00189 #define __I volatile /*!< Defines 'read only' permissions */ 00190 #else 00191 #define __I volatile const /*!< Defines 'read only' permissions */ 00192 #endif 00193 #define __O volatile /*!< Defines 'write only' permissions */ 00194 #define __IO volatile /*!< Defines 'read / write' permissions */ 00195 00196 /*@} end of group SC000 */ 00197 00198 00199 00200 /******************************************************************************* 00201 * Register Abstraction 00202 Core Register contain: 00203 - Core Register 00204 - Core NVIC Register 00205 - Core SCB Register 00206 - Core SysTick Register 00207 - Core MPU Register 00208 ******************************************************************************/ 00209 /** \defgroup CMSIS_core_register Defines and Type Definitions 00210 \brief Type definitions and defines for Cortex-M processor based devices. 00211 */ 00212 00213 /** \ingroup CMSIS_core_register 00214 \defgroup CMSIS_CORE Status and Control Registers 00215 \brief Core Register type definitions. 00216 @{ 00217 */ 00218 00219 /** \brief Union type to access the Application Program Status Register (APSR). 00220 */ 00221 typedef union 00222 { 00223 struct 00224 { 00225 #if (__CORTEX_M != 0x04) 00226 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00227 #else 00228 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00229 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00230 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00231 #endif 00232 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00233 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00234 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00235 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00236 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00237 } b; /*!< Structure used for bit access */ 00238 uint32_t w; /*!< Type used for word access */ 00239 } APSR_Type; 00240 00241 00242 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00243 */ 00244 typedef union 00245 { 00246 struct 00247 { 00248 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00249 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00250 } b; /*!< Structure used for bit access */ 00251 uint32_t w; /*!< Type used for word access */ 00252 } IPSR_Type; 00253 00254 00255 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00256 */ 00257 typedef union 00258 { 00259 struct 00260 { 00261 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00262 #if (__CORTEX_M != 0x04) 00263 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00264 #else 00265 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00266 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00267 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00268 #endif 00269 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00270 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00271 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00272 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00273 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00274 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00275 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00276 } b; /*!< Structure used for bit access */ 00277 uint32_t w; /*!< Type used for word access */ 00278 } xPSR_Type; 00279 00280 00281 /** \brief Union type to access the Control Registers (CONTROL). 00282 */ 00283 typedef union 00284 { 00285 struct 00286 { 00287 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00288 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00289 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00290 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00291 } b; /*!< Structure used for bit access */ 00292 uint32_t w; /*!< Type used for word access */ 00293 } CONTROL_Type; 00294 00295 /*@} end of group CMSIS_CORE */ 00296 00297 00298 /** \ingroup CMSIS_core_register 00299 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00300 \brief Type definitions for the NVIC Registers 00301 @{ 00302 */ 00303 00304 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00305 */ 00306 typedef struct 00307 { 00308 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00309 uint32_t RESERVED0[31]; 00310 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00311 uint32_t RSERVED1[31]; 00312 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00313 uint32_t RESERVED2[31]; 00314 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00315 uint32_t RESERVED3[31]; 00316 uint32_t RESERVED4[64]; 00317 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00318 } NVIC_Type; 00319 00320 /*@} end of group CMSIS_NVIC */ 00321 00322 00323 /** \ingroup CMSIS_core_register 00324 \defgroup CMSIS_SCB System Control Block (SCB) 00325 \brief Type definitions for the System Control Block Registers 00326 @{ 00327 */ 00328 00329 /** \brief Structure type to access the System Control Block (SCB). 00330 */ 00331 typedef struct 00332 { 00333 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00334 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00335 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ 00336 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00337 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00338 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00339 uint32_t RESERVED0[1]; 00340 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00341 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00342 uint32_t RESERVED1[154]; 00343 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ 00344 } SCB_Type; 00345 00346 /* SCB CPUID Register Definitions */ 00347 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00348 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00349 00350 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00351 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00352 00353 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00354 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00355 00356 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00357 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00358 00359 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00360 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00361 00362 /* SCB Interrupt Control State Register Definitions */ 00363 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00364 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00365 00366 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00367 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00368 00369 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00370 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00371 00372 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00373 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00374 00375 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00376 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00377 00378 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00379 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00380 00381 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00382 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00383 00384 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00385 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00386 00387 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00388 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00389 00390 /* SCB Interrupt Control State Register Definitions */ 00391 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ 00392 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ 00393 00394 /* SCB Application Interrupt and Reset Control Register Definitions */ 00395 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00396 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00397 00398 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00399 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00400 00401 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00402 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00403 00404 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00405 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00406 00407 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00408 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00409 00410 /* SCB System Control Register Definitions */ 00411 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00412 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00413 00414 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00415 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00416 00417 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00418 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00419 00420 /* SCB Configuration Control Register Definitions */ 00421 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00422 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00423 00424 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00425 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00426 00427 /* SCB System Handler Control and State Register Definitions */ 00428 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00429 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00430 00431 /* SCB Security Features Register Definitions */ 00432 #define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ 00433 #define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ 00434 00435 #define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ 00436 #define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ 00437 00438 /*@} end of group CMSIS_SCB */ 00439 00440 00441 /** \ingroup CMSIS_core_register 00442 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) 00443 \brief Type definitions for the System Control and ID Register not in the SCB 00444 @{ 00445 */ 00446 00447 /** \brief Structure type to access the System Control and ID Register not in the SCB. 00448 */ 00449 typedef struct 00450 { 00451 uint32_t RESERVED0[2]; 00452 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ 00453 } SCnSCB_Type; 00454 00455 /* Auxiliary Control Register Definitions */ 00456 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ 00457 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ 00458 00459 /*@} end of group CMSIS_SCnotSCB */ 00460 00461 00462 /** \ingroup CMSIS_core_register 00463 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00464 \brief Type definitions for the System Timer Registers. 00465 @{ 00466 */ 00467 00468 /** \brief Structure type to access the System Timer (SysTick). 00469 */ 00470 typedef struct 00471 { 00472 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00473 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00474 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00475 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00476 } SysTick_Type; 00477 00478 /* SysTick Control / Status Register Definitions */ 00479 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00480 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00481 00482 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00483 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00484 00485 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00486 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00487 00488 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00489 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00490 00491 /* SysTick Reload Register Definitions */ 00492 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00493 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00494 00495 /* SysTick Current Register Definitions */ 00496 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00497 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00498 00499 /* SysTick Calibration Register Definitions */ 00500 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00501 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00502 00503 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00504 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00505 00506 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00507 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ 00508 00509 /*@} end of group CMSIS_SysTick */ 00510 00511 #if (__MPU_PRESENT == 1) 00512 /** \ingroup CMSIS_core_register 00513 \defgroup CMSIS_MPU Memory Protection Unit (MPU) 00514 \brief Type definitions for the Memory Protection Unit (MPU) 00515 @{ 00516 */ 00517 00518 /** \brief Structure type to access the Memory Protection Unit (MPU). 00519 */ 00520 typedef struct 00521 { 00522 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ 00523 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ 00524 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ 00525 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ 00526 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ 00527 } MPU_Type; 00528 00529 /* MPU Type Register */ 00530 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ 00531 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ 00532 00533 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ 00534 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ 00535 00536 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ 00537 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ 00538 00539 /* MPU Control Register */ 00540 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ 00541 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ 00542 00543 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ 00544 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ 00545 00546 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ 00547 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ 00548 00549 /* MPU Region Number Register */ 00550 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ 00551 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ 00552 00553 /* MPU Region Base Address Register */ 00554 #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ 00555 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ 00556 00557 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ 00558 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ 00559 00560 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ 00561 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ 00562 00563 /* MPU Region Attribute and Size Register */ 00564 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ 00565 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ 00566 00567 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ 00568 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ 00569 00570 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ 00571 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ 00572 00573 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ 00574 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ 00575 00576 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ 00577 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ 00578 00579 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ 00580 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ 00581 00582 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ 00583 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ 00584 00585 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ 00586 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ 00587 00588 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ 00589 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ 00590 00591 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ 00592 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ 00593 00594 /*@} end of group CMSIS_MPU */ 00595 #endif 00596 00597 00598 /** \ingroup CMSIS_core_register 00599 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00600 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) 00601 are only accessible over DAP and not via processor. Therefore 00602 they are not covered by the Cortex-M0 header file. 00603 @{ 00604 */ 00605 /*@} end of group CMSIS_CoreDebug */ 00606 00607 00608 /** \ingroup CMSIS_core_register 00609 \defgroup CMSIS_core_base Core Definitions 00610 \brief Definitions for base addresses, unions, and structures. 00611 @{ 00612 */ 00613 00614 /* Memory mapping of SC000 Hardware */ 00615 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00616 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00617 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00618 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00619 00620 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ 00621 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00622 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00623 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00624 00625 #if (__MPU_PRESENT == 1) 00626 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ 00627 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ 00628 #endif 00629 00630 /*@} */ 00631 00632 00633 00634 /******************************************************************************* 00635 * Hardware Abstraction Layer 00636 Core Function Interface contains: 00637 - Core NVIC Functions 00638 - Core SysTick Functions 00639 - Core Register Access Functions 00640 ******************************************************************************/ 00641 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00642 */ 00643 00644 00645 00646 /* ########################## NVIC functions #################################### */ 00647 /** \ingroup CMSIS_Core_FunctionInterface 00648 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00649 \brief Functions that manage interrupts and exceptions via the NVIC. 00650 @{ 00651 */ 00652 00653 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00654 /* The following MACROS handle generation of the register offset and byte masks */ 00655 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00656 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00657 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00658 00659 00660 /** \brief Enable External Interrupt 00661 00662 The function enables a device-specific interrupt in the NVIC interrupt controller. 00663 00664 \param [in] IRQn External interrupt number. Value cannot be negative. 00665 */ 00666 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00667 { 00668 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00669 } 00670 00671 00672 /** \brief Disable External Interrupt 00673 00674 The function disables a device-specific interrupt in the NVIC interrupt controller. 00675 00676 \param [in] IRQn External interrupt number. Value cannot be negative. 00677 */ 00678 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00679 { 00680 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00681 } 00682 00683 00684 /** \brief Get Pending Interrupt 00685 00686 The function reads the pending register in the NVIC and returns the pending bit 00687 for the specified interrupt. 00688 00689 \param [in] IRQn Interrupt number. 00690 00691 \return 0 Interrupt status is not pending. 00692 \return 1 Interrupt status is pending. 00693 */ 00694 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00695 { 00696 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00697 } 00698 00699 00700 /** \brief Set Pending Interrupt 00701 00702 The function sets the pending bit of an external interrupt. 00703 00704 \param [in] IRQn Interrupt number. Value cannot be negative. 00705 */ 00706 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00707 { 00708 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00709 } 00710 00711 00712 /** \brief Clear Pending Interrupt 00713 00714 The function clears the pending bit of an external interrupt. 00715 00716 \param [in] IRQn External interrupt number. Value cannot be negative. 00717 */ 00718 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00719 { 00720 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00721 } 00722 00723 00724 /** \brief Set Interrupt Priority 00725 00726 The function sets the priority of an interrupt. 00727 00728 \note The priority cannot be set for every core interrupt. 00729 00730 \param [in] IRQn Interrupt number. 00731 \param [in] priority Priority to set. 00732 */ 00733 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00734 { 00735 if(IRQn < 0) { 00736 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00737 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00738 else { 00739 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00740 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00741 } 00742 00743 00744 /** \brief Get Interrupt Priority 00745 00746 The function reads the priority of an interrupt. The interrupt 00747 number can be positive to specify an external (device specific) 00748 interrupt, or negative to specify an internal (core) interrupt. 00749 00750 00751 \param [in] IRQn Interrupt number. 00752 \return Interrupt Priority. Value is aligned automatically to the implemented 00753 priority bits of the microcontroller. 00754 */ 00755 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00756 { 00757 00758 if(IRQn < 0) { 00759 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00760 else { 00761 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00762 } 00763 00764 00765 /** \brief System Reset 00766 00767 The function initiates a system reset request to reset the MCU. 00768 */ 00769 __STATIC_INLINE void NVIC_SystemReset(void) 00770 { 00771 __DSB(); /* Ensure all outstanding memory accesses included 00772 buffered write are completed before reset */ 00773 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00774 SCB_AIRCR_SYSRESETREQ_Msk); 00775 __DSB(); /* Ensure completion of memory access */ 00776 while(1); /* wait until reset */ 00777 } 00778 00779 /*@} end of CMSIS_Core_NVICFunctions */ 00780 00781 00782 00783 /* ################################## SysTick function ############################################ */ 00784 /** \ingroup CMSIS_Core_FunctionInterface 00785 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00786 \brief Functions that configure the System. 00787 @{ 00788 */ 00789 00790 #if (__Vendor_SysTickConfig == 0) 00791 00792 /** \brief System Tick Configuration 00793 00794 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00795 Counter is in free running mode to generate periodic interrupts. 00796 00797 \param [in] ticks Number of ticks between two interrupts. 00798 00799 \return 0 Function succeeded. 00800 \return 1 Function failed. 00801 00802 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00803 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00804 must contain a vendor-specific implementation of this function. 00805 00806 */ 00807 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00808 { 00809 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00810 00811 SysTick->LOAD = ticks - 1; /* set reload register */ 00812 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00813 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00814 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00815 SysTick_CTRL_TICKINT_Msk | 00816 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00817 return (0); /* Function successful */ 00818 } 00819 00820 #endif 00821 00822 /*@} end of CMSIS_Core_SysTickFunctions */ 00823 00824 00825 00826 00827 #endif /* __CORE_SC000_H_DEPENDANT */ 00828 00829 #ifdef __cplusplus 00830 } 00831 #endif 00832 00833 #endif /* __CMSIS_GENERIC */
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