V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.
Dependents: MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more
core_cmFunc.h
00001 /**************************************************************************//** 00002 * @file core_cmFunc.h 00003 * @brief CMSIS Cortex-M Core Function Access Header File 00004 * @version V3.30 00005 * @date 17. February 2014 00006 * 00007 * @note 00008 * 00009 ******************************************************************************/ 00010 /* Copyright (c) 2009 - 2014 ARM LIMITED 00011 00012 All rights reserved. 00013 Redistribution and use in source and binary forms, with or without 00014 modification, are permitted provided that the following conditions are met: 00015 - Redistributions of source code must retain the above copyright 00016 notice, this list of conditions and the following disclaimer. 00017 - Redistributions in binary form must reproduce the above copyright 00018 notice, this list of conditions and the following disclaimer in the 00019 documentation and/or other materials provided with the distribution. 00020 - Neither the name of ARM nor the names of its contributors may be used 00021 to endorse or promote products derived from this software without 00022 specific prior written permission. 00023 * 00024 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00025 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00026 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 00027 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE 00028 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 00029 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 00030 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 00031 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 00032 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 00033 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 00034 POSSIBILITY OF SUCH DAMAGE. 00035 ---------------------------------------------------------------------------*/ 00036 00037 00038 #ifndef __CORE_CMFUNC_H 00039 #define __CORE_CMFUNC_H 00040 00041 00042 /* ########################### Core Function Access ########################### */ 00043 /** \ingroup CMSIS_Core_FunctionInterface 00044 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 00045 @{ 00046 */ 00047 00048 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ 00049 /* ARM armcc specific functions */ 00050 00051 #if (__ARMCC_VERSION < 400677) 00052 #error "Please use ARM Compiler Toolchain V4.0.677 or later!" 00053 #endif 00054 00055 /* intrinsic void __enable_irq(); */ 00056 /* intrinsic void __disable_irq(); */ 00057 00058 /** \brief Get Control Register 00059 00060 This function returns the content of the Control Register. 00061 00062 \return Control Register value 00063 */ 00064 __STATIC_INLINE uint32_t __get_CONTROL(void) 00065 { 00066 register uint32_t __regControl __ASM("control"); 00067 return(__regControl); 00068 } 00069 00070 00071 /** \brief Set Control Register 00072 00073 This function writes the given value to the Control Register. 00074 00075 \param [in] control Control Register value to set 00076 */ 00077 __STATIC_INLINE void __set_CONTROL(uint32_t control) 00078 { 00079 register uint32_t __regControl __ASM("control"); 00080 __regControl = control; 00081 } 00082 00083 00084 /** \brief Get IPSR Register 00085 00086 This function returns the content of the IPSR Register. 00087 00088 \return IPSR Register value 00089 */ 00090 __STATIC_INLINE uint32_t __get_IPSR(void) 00091 { 00092 register uint32_t __regIPSR __ASM("ipsr"); 00093 return(__regIPSR); 00094 } 00095 00096 00097 /** \brief Get APSR Register 00098 00099 This function returns the content of the APSR Register. 00100 00101 \return APSR Register value 00102 */ 00103 __STATIC_INLINE uint32_t __get_APSR(void) 00104 { 00105 register uint32_t __regAPSR __ASM("apsr"); 00106 return(__regAPSR); 00107 } 00108 00109 00110 /** \brief Get xPSR Register 00111 00112 This function returns the content of the xPSR Register. 00113 00114 \return xPSR Register value 00115 */ 00116 __STATIC_INLINE uint32_t __get_xPSR(void) 00117 { 00118 register uint32_t __regXPSR __ASM("xpsr"); 00119 return(__regXPSR); 00120 } 00121 00122 00123 /** \brief Get Process Stack Pointer 00124 00125 This function returns the current value of the Process Stack Pointer (PSP). 00126 00127 \return PSP Register value 00128 */ 00129 __STATIC_INLINE uint32_t __get_PSP(void) 00130 { 00131 register uint32_t __regProcessStackPointer __ASM("psp"); 00132 return(__regProcessStackPointer); 00133 } 00134 00135 00136 /** \brief Set Process Stack Pointer 00137 00138 This function assigns the given value to the Process Stack Pointer (PSP). 00139 00140 \param [in] topOfProcStack Process Stack Pointer value to set 00141 */ 00142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 00143 { 00144 register uint32_t __regProcessStackPointer __ASM("psp"); 00145 __regProcessStackPointer = topOfProcStack; 00146 } 00147 00148 00149 /** \brief Get Main Stack Pointer 00150 00151 This function returns the current value of the Main Stack Pointer (MSP). 00152 00153 \return MSP Register value 00154 */ 00155 __STATIC_INLINE uint32_t __get_MSP(void) 00156 { 00157 register uint32_t __regMainStackPointer __ASM("msp"); 00158 return(__regMainStackPointer); 00159 } 00160 00161 00162 /** \brief Set Main Stack Pointer 00163 00164 This function assigns the given value to the Main Stack Pointer (MSP). 00165 00166 \param [in] topOfMainStack Main Stack Pointer value to set 00167 */ 00168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 00169 { 00170 register uint32_t __regMainStackPointer __ASM("msp"); 00171 __regMainStackPointer = topOfMainStack; 00172 } 00173 00174 00175 /** \brief Get Priority Mask 00176 00177 This function returns the current state of the priority mask bit from the Priority Mask Register. 00178 00179 \return Priority Mask value 00180 */ 00181 __STATIC_INLINE uint32_t __get_PRIMASK(void) 00182 { 00183 register uint32_t __regPriMask __ASM("primask"); 00184 return(__regPriMask); 00185 } 00186 00187 00188 /** \brief Set Priority Mask 00189 00190 This function assigns the given value to the Priority Mask Register. 00191 00192 \param [in] priMask Priority Mask 00193 */ 00194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 00195 { 00196 register uint32_t __regPriMask __ASM("primask"); 00197 __regPriMask = (priMask); 00198 } 00199 00200 00201 #if (__CORTEX_M >= 0x03) 00202 00203 /** \brief Enable FIQ 00204 00205 This function enables FIQ interrupts by clearing the F-bit in the CPSR. 00206 Can only be executed in Privileged modes. 00207 */ 00208 #define __enable_fault_irq __enable_fiq 00209 00210 00211 /** \brief Disable FIQ 00212 00213 This function disables FIQ interrupts by setting the F-bit in the CPSR. 00214 Can only be executed in Privileged modes. 00215 */ 00216 #define __disable_fault_irq __disable_fiq 00217 00218 00219 /** \brief Get Base Priority 00220 00221 This function returns the current value of the Base Priority register. 00222 00223 \return Base Priority register value 00224 */ 00225 __STATIC_INLINE uint32_t __get_BASEPRI(void) 00226 { 00227 register uint32_t __regBasePri __ASM("basepri"); 00228 return(__regBasePri); 00229 } 00230 00231 00232 /** \brief Set Base Priority 00233 00234 This function assigns the given value to the Base Priority register. 00235 00236 \param [in] basePri Base Priority value to set 00237 */ 00238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) 00239 { 00240 register uint32_t __regBasePri __ASM("basepri"); 00241 __regBasePri = (basePri & 0xff); 00242 } 00243 00244 00245 /** \brief Get Fault Mask 00246 00247 This function returns the current value of the Fault Mask register. 00248 00249 \return Fault Mask register value 00250 */ 00251 __STATIC_INLINE uint32_t __get_FAULTMASK(void) 00252 { 00253 register uint32_t __regFaultMask __ASM("faultmask"); 00254 return(__regFaultMask); 00255 } 00256 00257 00258 /** \brief Set Fault Mask 00259 00260 This function assigns the given value to the Fault Mask register. 00261 00262 \param [in] faultMask Fault Mask value to set 00263 */ 00264 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 00265 { 00266 register uint32_t __regFaultMask __ASM("faultmask"); 00267 __regFaultMask = (faultMask & (uint32_t)1); 00268 } 00269 00270 #endif /* (__CORTEX_M >= 0x03) */ 00271 00272 00273 #if (__CORTEX_M == 0x04) 00274 00275 /** \brief Get FPSCR 00276 00277 This function returns the current value of the Floating Point Status/Control register. 00278 00279 \return Floating Point Status/Control register value 00280 */ 00281 __STATIC_INLINE uint32_t __get_FPSCR(void) 00282 { 00283 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00284 register uint32_t __regfpscr __ASM("fpscr"); 00285 return(__regfpscr); 00286 #else 00287 return(0); 00288 #endif 00289 } 00290 00291 00292 /** \brief Set FPSCR 00293 00294 This function assigns the given value to the Floating Point Status/Control register. 00295 00296 \param [in] fpscr Floating Point Status/Control value to set 00297 */ 00298 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 00299 { 00300 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00301 register uint32_t __regfpscr __ASM("fpscr"); 00302 __regfpscr = (fpscr); 00303 #endif 00304 } 00305 00306 #endif /* (__CORTEX_M == 0x04) */ 00307 00308 00309 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ 00310 /* GNU gcc specific functions */ 00311 00312 /** \brief Enable IRQ Interrupts 00313 00314 This function enables IRQ interrupts by clearing the I-bit in the CPSR. 00315 Can only be executed in Privileged modes. 00316 */ 00317 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) 00318 { 00319 __ASM volatile ("cpsie i" : : : "memory"); 00320 } 00321 00322 00323 /** \brief Disable IRQ Interrupts 00324 00325 This function disables IRQ interrupts by setting the I-bit in the CPSR. 00326 Can only be executed in Privileged modes. 00327 */ 00328 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) 00329 { 00330 __ASM volatile ("cpsid i" : : : "memory"); 00331 } 00332 00333 00334 /** \brief Get Control Register 00335 00336 This function returns the content of the Control Register. 00337 00338 \return Control Register value 00339 */ 00340 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) 00341 { 00342 uint32_t result; 00343 00344 __ASM volatile ("MRS %0, control" : "=r" (result) ); 00345 return(result); 00346 } 00347 00348 00349 /** \brief Set Control Register 00350 00351 This function writes the given value to the Control Register. 00352 00353 \param [in] control Control Register value to set 00354 */ 00355 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) 00356 { 00357 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); 00358 } 00359 00360 00361 /** \brief Get IPSR Register 00362 00363 This function returns the content of the IPSR Register. 00364 00365 \return IPSR Register value 00366 */ 00367 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) 00368 { 00369 uint32_t result; 00370 00371 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); 00372 return(result); 00373 } 00374 00375 00376 /** \brief Get APSR Register 00377 00378 This function returns the content of the APSR Register. 00379 00380 \return APSR Register value 00381 */ 00382 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) 00383 { 00384 uint32_t result; 00385 00386 __ASM volatile ("MRS %0, apsr" : "=r" (result) ); 00387 return(result); 00388 } 00389 00390 00391 /** \brief Get xPSR Register 00392 00393 This function returns the content of the xPSR Register. 00394 00395 \return xPSR Register value 00396 */ 00397 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) 00398 { 00399 uint32_t result; 00400 00401 __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); 00402 return(result); 00403 } 00404 00405 00406 /** \brief Get Process Stack Pointer 00407 00408 This function returns the current value of the Process Stack Pointer (PSP). 00409 00410 \return PSP Register value 00411 */ 00412 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) 00413 { 00414 register uint32_t result; 00415 00416 __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); 00417 return(result); 00418 } 00419 00420 00421 /** \brief Set Process Stack Pointer 00422 00423 This function assigns the given value to the Process Stack Pointer (PSP). 00424 00425 \param [in] topOfProcStack Process Stack Pointer value to set 00426 */ 00427 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) 00428 { 00429 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); 00430 } 00431 00432 00433 /** \brief Get Main Stack Pointer 00434 00435 This function returns the current value of the Main Stack Pointer (MSP). 00436 00437 \return MSP Register value 00438 */ 00439 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) 00440 { 00441 register uint32_t result; 00442 00443 __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); 00444 return(result); 00445 } 00446 00447 00448 /** \brief Set Main Stack Pointer 00449 00450 This function assigns the given value to the Main Stack Pointer (MSP). 00451 00452 \param [in] topOfMainStack Main Stack Pointer value to set 00453 */ 00454 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) 00455 { 00456 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); 00457 } 00458 00459 00460 /** \brief Get Priority Mask 00461 00462 This function returns the current state of the priority mask bit from the Priority Mask Register. 00463 00464 \return Priority Mask value 00465 */ 00466 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) 00467 { 00468 uint32_t result; 00469 00470 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 00471 return(result); 00472 } 00473 00474 00475 /** \brief Set Priority Mask 00476 00477 This function assigns the given value to the Priority Mask Register. 00478 00479 \param [in] priMask Priority Mask 00480 */ 00481 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) 00482 { 00483 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 00484 } 00485 00486 00487 #if (__CORTEX_M >= 0x03) 00488 00489 /** \brief Enable FIQ 00490 00491 This function enables FIQ interrupts by clearing the F-bit in the CPSR. 00492 Can only be executed in Privileged modes. 00493 */ 00494 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) 00495 { 00496 __ASM volatile ("cpsie f" : : : "memory"); 00497 } 00498 00499 00500 /** \brief Disable FIQ 00501 00502 This function disables FIQ interrupts by setting the F-bit in the CPSR. 00503 Can only be executed in Privileged modes. 00504 */ 00505 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) 00506 { 00507 __ASM volatile ("cpsid f" : : : "memory"); 00508 } 00509 00510 00511 /** \brief Get Base Priority 00512 00513 This function returns the current value of the Base Priority register. 00514 00515 \return Base Priority register value 00516 */ 00517 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) 00518 { 00519 uint32_t result; 00520 00521 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); 00522 return(result); 00523 } 00524 00525 00526 /** \brief Set Base Priority 00527 00528 This function assigns the given value to the Base Priority register. 00529 00530 \param [in] basePri Base Priority value to set 00531 */ 00532 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) 00533 { 00534 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); 00535 } 00536 00537 00538 /** \brief Get Fault Mask 00539 00540 This function returns the current value of the Fault Mask register. 00541 00542 \return Fault Mask register value 00543 */ 00544 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) 00545 { 00546 uint32_t result; 00547 00548 __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); 00549 return(result); 00550 } 00551 00552 00553 /** \brief Set Fault Mask 00554 00555 This function assigns the given value to the Fault Mask register. 00556 00557 \param [in] faultMask Fault Mask value to set 00558 */ 00559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) 00560 { 00561 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); 00562 } 00563 00564 #endif /* (__CORTEX_M >= 0x03) */ 00565 00566 00567 #if (__CORTEX_M == 0x04) 00568 00569 /** \brief Get FPSCR 00570 00571 This function returns the current value of the Floating Point Status/Control register. 00572 00573 \return Floating Point Status/Control register value 00574 */ 00575 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) 00576 { 00577 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00578 uint32_t result; 00579 00580 /* Empty asm statement works as a scheduling barrier */ 00581 __ASM volatile (""); 00582 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); 00583 __ASM volatile (""); 00584 return(result); 00585 #else 00586 return(0); 00587 #endif 00588 } 00589 00590 00591 /** \brief Set FPSCR 00592 00593 This function assigns the given value to the Floating Point Status/Control register. 00594 00595 \param [in] fpscr Floating Point Status/Control value to set 00596 */ 00597 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) 00598 { 00599 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) 00600 /* Empty asm statement works as a scheduling barrier */ 00601 __ASM volatile (""); 00602 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); 00603 __ASM volatile (""); 00604 #endif 00605 } 00606 00607 #endif /* (__CORTEX_M == 0x04) */ 00608 00609 00610 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ 00611 /* IAR iccarm specific functions */ 00612 #include <cmsis_iar.h> 00613 00614 00615 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ 00616 /* TI CCS specific functions */ 00617 #include <cmsis_ccs.h> 00618 00619 00620 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ 00621 /* TASKING carm specific functions */ 00622 /* 00623 * The CMSIS functions have been implemented as intrinsics in the compiler. 00624 * Please use "carm -?i" to get an up to date list of all intrinsics, 00625 * Including the CMSIS ones. 00626 */ 00627 00628 00629 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ 00630 /* Cosmic specific functions */ 00631 #include <cmsis_csm.h> 00632 00633 #endif 00634 00635 /*@} end of CMSIS_Core_RegAccFunctions */ 00636 00637 #endif /* __CORE_CMFUNC_H */
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