V4.0.1 of the ARM CMSIS DSP libraries. Note that arm_bitreversal2.s, arm_cfft_f32.c and arm_rfft_fast_f32.c had to be removed. arm_bitreversal2.s will not assemble with the online tools. So, the fast f32 FFT functions are not yet available. All the other FFT functions are available.

Dependents:   MPU9150_Example fir_f32 fir_f32 MPU9150_nucleo_noni2cdev ... more

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core_cm3.h

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00001 /**************************************************************************//**
00002  * @file     core_cm3.h
00003  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
00004  * @version  V3.30
00005  * @date     06. May 2014
00006  *
00007  * @note
00008  *
00009  ******************************************************************************/
00010 /* Copyright (c) 2009 - 2014 ARM LIMITED
00011 
00012    All rights reserved.
00013    Redistribution and use in source and binary forms, with or without
00014    modification, are permitted provided that the following conditions are met:
00015    - Redistributions of source code must retain the above copyright
00016      notice, this list of conditions and the following disclaimer.
00017    - Redistributions in binary form must reproduce the above copyright
00018      notice, this list of conditions and the following disclaimer in the
00019      documentation and/or other materials provided with the distribution.
00020    - Neither the name of ARM nor the names of its contributors may be used
00021      to endorse or promote products derived from this software without
00022      specific prior written permission.
00023    *
00024    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00025    AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00026    IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
00027    ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
00028    LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
00029    CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
00030    SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
00031    INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
00032    CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
00033    ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
00034    POSSIBILITY OF SUCH DAMAGE.
00035    ---------------------------------------------------------------------------*/
00036 
00037 
00038 #if defined ( __ICCARM__ )
00039  #pragma system_include  /* treat file as system include file for MISRA check */
00040 #endif
00041 
00042 #ifndef __CORE_CM3_H_GENERIC
00043 #define __CORE_CM3_H_GENERIC
00044 
00045 #ifdef __cplusplus
00046  extern "C" {
00047 #endif
00048 
00049 /** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
00050   CMSIS violates the following MISRA-C:2004 rules:
00051 
00052    \li Required Rule 8.5, object/function definition in header file.<br>
00053      Function definitions in header files are used to allow 'inlining'.
00054 
00055    \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
00056      Unions are used for effective representation of core registers.
00057 
00058    \li Advisory Rule 19.7, Function-like macro defined.<br>
00059      Function-like macros are used to allow more efficient code.
00060  */
00061 
00062 
00063 /*******************************************************************************
00064  *                 CMSIS definitions
00065  ******************************************************************************/
00066 /** \ingroup Cortex_M3
00067   @{
00068  */
00069 
00070 /*  CMSIS CM3 definitions */
00071 #define __CM3_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
00072 #define __CM3_CMSIS_VERSION_SUB   (0x30)                                   /*!< [15:0]  CMSIS HAL sub version    */
00073 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | \
00074                                     __CM3_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
00075 
00076 #define __CORTEX_M                (0x03)                                   /*!< Cortex-M Core                    */
00077 
00078 
00079 #if   defined ( __CC_ARM )
00080   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
00081   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
00082   #define __STATIC_INLINE  static __inline
00083 
00084 #elif defined ( __GNUC__ )
00085   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
00086   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
00087   #define __STATIC_INLINE  static inline
00088 
00089 #elif defined ( __ICCARM__ )
00090   #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
00091   #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
00092   #define __STATIC_INLINE  static inline
00093 
00094 #elif defined ( __TMS470__ )
00095   #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
00096   #define __STATIC_INLINE  static inline
00097 
00098 #elif defined ( __TASKING__ )
00099   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
00100   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
00101   #define __STATIC_INLINE  static inline
00102 
00103 #elif defined ( __CSMC__ )  /* Cosmic */
00104   #define __packed
00105   #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
00106   #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
00107   #define __STATIC_INLINE  static inline
00108 
00109 #endif
00110 
00111 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
00112 */
00113 #define __FPU_USED       0
00114 
00115 #if defined ( __CC_ARM )
00116   #if defined __TARGET_FPU_VFP
00117     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00118   #endif
00119 
00120 #elif defined ( __GNUC__ )
00121   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
00122     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00123   #endif
00124 
00125 #elif defined ( __ICCARM__ )
00126   #if defined __ARMVFP__
00127     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00128   #endif
00129 
00130 #elif defined ( __TMS470__ )
00131   #if defined __TI__VFP_SUPPORT____
00132     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00133   #endif
00134 
00135 #elif defined ( __TASKING__ )
00136   #if defined __FPU_VFP__
00137     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00138   #endif
00139 
00140 #elif defined ( __CSMC__ )      /* Cosmic */
00141   #if ( __CSMC__ & 0x400)       // FPU present for parser
00142     #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
00143   #endif
00144 #endif
00145 
00146 #include <stdint.h>                      /* standard types definitions                      */
00147 #include <core_cmInstr.h>                /* Core Instruction Access                         */
00148 #include <core_cmFunc.h>                 /* Core Function Access                            */
00149 
00150 #endif /* __CORE_CM3_H_GENERIC */
00151 
00152 #ifndef __CMSIS_GENERIC
00153 
00154 #ifndef __CORE_CM3_H_DEPENDANT
00155 #define __CORE_CM3_H_DEPENDANT
00156 
00157 /* check device defines and use defaults */
00158 #if defined __CHECK_DEVICE_DEFINES
00159   #ifndef __CM3_REV
00160     #define __CM3_REV               0x0200
00161     #warning "__CM3_REV not defined in device header file; using default!"
00162   #endif
00163 
00164   #ifndef __MPU_PRESENT
00165     #define __MPU_PRESENT             0
00166     #warning "__MPU_PRESENT not defined in device header file; using default!"
00167   #endif
00168 
00169   #ifndef __NVIC_PRIO_BITS
00170     #define __NVIC_PRIO_BITS          4
00171     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
00172   #endif
00173 
00174   #ifndef __Vendor_SysTickConfig
00175     #define __Vendor_SysTickConfig    0
00176     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
00177   #endif
00178 #endif
00179 
00180 /* IO definitions (access restrictions to peripheral registers) */
00181 /**
00182     \defgroup CMSIS_glob_defs CMSIS Global Defines
00183 
00184     <strong>IO Type Qualifiers</strong> are used
00185     \li to specify the access to peripheral variables.
00186     \li for automatic generation of peripheral register debug information.
00187 */
00188 #ifdef __cplusplus
00189   #define   __I     volatile             /*!< Defines 'read only' permissions                 */
00190 #else
00191   #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
00192 #endif
00193 #define     __O     volatile             /*!< Defines 'write only' permissions                */
00194 #define     __IO    volatile             /*!< Defines 'read / write' permissions              */
00195 
00196 /*@} end of group Cortex_M3 */
00197 
00198 
00199 
00200 /*******************************************************************************
00201  *                 Register Abstraction
00202   Core Register contain:
00203   - Core Register
00204   - Core NVIC Register
00205   - Core SCB Register
00206   - Core SysTick Register
00207   - Core Debug Register
00208   - Core MPU Register
00209  ******************************************************************************/
00210 /** \defgroup CMSIS_core_register Defines and Type Definitions
00211     \brief Type definitions and defines for Cortex-M processor based devices.
00212 */
00213 
00214 /** \ingroup    CMSIS_core_register
00215     \defgroup   CMSIS_CORE  Status and Control Registers
00216     \brief  Core Register type definitions.
00217   @{
00218  */
00219 
00220 /** \brief  Union type to access the Application Program Status Register (APSR).
00221  */
00222 typedef union
00223 {
00224   struct
00225   {
00226 #if (__CORTEX_M != 0x04)
00227     uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
00228 #else
00229     uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
00230     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00231     uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
00232 #endif
00233     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00234     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00235     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00236     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00237     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00238   } b;                                   /*!< Structure used for bit  access                  */
00239   uint32_t w;                            /*!< Type      used for word access                  */
00240 } APSR_Type;
00241 
00242 
00243 /** \brief  Union type to access the Interrupt Program Status Register (IPSR).
00244  */
00245 typedef union
00246 {
00247   struct
00248   {
00249     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00250     uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
00251   } b;                                   /*!< Structure used for bit  access                  */
00252   uint32_t w;                            /*!< Type      used for word access                  */
00253 } IPSR_Type;
00254 
00255 
00256 /** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
00257  */
00258 typedef union
00259 {
00260   struct
00261   {
00262     uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
00263 #if (__CORTEX_M != 0x04)
00264     uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
00265 #else
00266     uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
00267     uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
00268     uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
00269 #endif
00270     uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
00271     uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
00272     uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
00273     uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
00274     uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
00275     uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
00276     uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
00277   } b;                                   /*!< Structure used for bit  access                  */
00278   uint32_t w;                            /*!< Type      used for word access                  */
00279 } xPSR_Type;
00280 
00281 
00282 /** \brief  Union type to access the Control Registers (CONTROL).
00283  */
00284 typedef union
00285 {
00286   struct
00287   {
00288     uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
00289     uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
00290     uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
00291     uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
00292   } b;                                   /*!< Structure used for bit  access                  */
00293   uint32_t w;                            /*!< Type      used for word access                  */
00294 } CONTROL_Type;
00295 
00296 /*@} end of group CMSIS_CORE */
00297 
00298 
00299 /** \ingroup    CMSIS_core_register
00300     \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
00301     \brief      Type definitions for the NVIC Registers
00302   @{
00303  */
00304 
00305 /** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
00306  */
00307 typedef struct
00308 {
00309   __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
00310        uint32_t RESERVED0[24];
00311   __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
00312        uint32_t RSERVED1[24];
00313   __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
00314        uint32_t RESERVED2[24];
00315   __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
00316        uint32_t RESERVED3[24];
00317   __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
00318        uint32_t RESERVED4[56];
00319   __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
00320        uint32_t RESERVED5[644];
00321   __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
00322 }  NVIC_Type;
00323 
00324 /* Software Triggered Interrupt Register Definitions */
00325 #define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
00326 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
00327 
00328 /*@} end of group CMSIS_NVIC */
00329 
00330 
00331 /** \ingroup  CMSIS_core_register
00332     \defgroup CMSIS_SCB     System Control Block (SCB)
00333     \brief      Type definitions for the System Control Block Registers
00334   @{
00335  */
00336 
00337 /** \brief  Structure type to access the System Control Block (SCB).
00338  */
00339 typedef struct
00340 {
00341   __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
00342   __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
00343   __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
00344   __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
00345   __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
00346   __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
00347   __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
00348   __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
00349   __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
00350   __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
00351   __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
00352   __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
00353   __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
00354   __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
00355   __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
00356   __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
00357   __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
00358   __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
00359   __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
00360        uint32_t RESERVED0[5];
00361   __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
00362 } SCB_Type;
00363 
00364 /* SCB CPUID Register Definitions */
00365 #define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
00366 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
00367 
00368 #define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
00369 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
00370 
00371 #define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
00372 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
00373 
00374 #define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
00375 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
00376 
00377 #define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
00378 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
00379 
00380 /* SCB Interrupt Control State Register Definitions */
00381 #define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
00382 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
00383 
00384 #define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
00385 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
00386 
00387 #define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
00388 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
00389 
00390 #define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
00391 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
00392 
00393 #define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
00394 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
00395 
00396 #define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
00397 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
00398 
00399 #define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
00400 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
00401 
00402 #define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
00403 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
00404 
00405 #define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
00406 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
00407 
00408 #define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
00409 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
00410 
00411 /* SCB Vector Table Offset Register Definitions */
00412 #if (__CM3_REV < 0x0201)                   /* core r2p1 */
00413 #define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
00414 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
00415 
00416 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00417 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
00418 #else
00419 #define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
00420 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
00421 #endif
00422 
00423 /* SCB Application Interrupt and Reset Control Register Definitions */
00424 #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
00425 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
00426 
00427 #define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
00428 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
00429 
00430 #define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
00431 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
00432 
00433 #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
00434 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
00435 
00436 #define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
00437 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
00438 
00439 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
00440 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
00441 
00442 #define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
00443 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
00444 
00445 /* SCB System Control Register Definitions */
00446 #define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
00447 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
00448 
00449 #define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
00450 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
00451 
00452 #define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
00453 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
00454 
00455 /* SCB Configuration Control Register Definitions */
00456 #define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
00457 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
00458 
00459 #define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
00460 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
00461 
00462 #define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
00463 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
00464 
00465 #define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
00466 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
00467 
00468 #define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
00469 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
00470 
00471 #define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
00472 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
00473 
00474 /* SCB System Handler Control and State Register Definitions */
00475 #define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
00476 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
00477 
00478 #define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
00479 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
00480 
00481 #define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
00482 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
00483 
00484 #define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
00485 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
00486 
00487 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
00488 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
00489 
00490 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
00491 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
00492 
00493 #define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
00494 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
00495 
00496 #define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
00497 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
00498 
00499 #define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
00500 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
00501 
00502 #define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
00503 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
00504 
00505 #define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
00506 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
00507 
00508 #define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
00509 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
00510 
00511 #define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
00512 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
00513 
00514 #define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
00515 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
00516 
00517 /* SCB Configurable Fault Status Registers Definitions */
00518 #define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
00519 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
00520 
00521 #define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
00522 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
00523 
00524 #define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
00525 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
00526 
00527 /* SCB Hard Fault Status Registers Definitions */
00528 #define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
00529 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
00530 
00531 #define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
00532 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
00533 
00534 #define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
00535 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
00536 
00537 /* SCB Debug Fault Status Register Definitions */
00538 #define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
00539 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
00540 
00541 #define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
00542 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
00543 
00544 #define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
00545 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
00546 
00547 #define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
00548 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
00549 
00550 #define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
00551 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
00552 
00553 /*@} end of group CMSIS_SCB */
00554 
00555 
00556 /** \ingroup  CMSIS_core_register
00557     \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
00558     \brief      Type definitions for the System Control and ID Register not in the SCB
00559   @{
00560  */
00561 
00562 /** \brief  Structure type to access the System Control and ID Register not in the SCB.
00563  */
00564 typedef struct
00565 {
00566        uint32_t RESERVED0[1];
00567   __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
00568 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
00569   __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
00570 #else
00571        uint32_t RESERVED1[1];
00572 #endif
00573 } SCnSCB_Type;
00574 
00575 /* Interrupt Controller Type Register Definitions */
00576 #define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
00577 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
00578 
00579 /* Auxiliary Control Register Definitions */
00580 
00581 #define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
00582 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
00583 
00584 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
00585 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
00586 
00587 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
00588 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
00589 
00590 /*@} end of group CMSIS_SCnotSCB */
00591 
00592 
00593 /** \ingroup  CMSIS_core_register
00594     \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
00595     \brief      Type definitions for the System Timer Registers.
00596   @{
00597  */
00598 
00599 /** \brief  Structure type to access the System Timer (SysTick).
00600  */
00601 typedef struct
00602 {
00603   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
00604   __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
00605   __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
00606   __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
00607 } SysTick_Type;
00608 
00609 /* SysTick Control / Status Register Definitions */
00610 #define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
00611 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
00612 
00613 #define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
00614 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
00615 
00616 #define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
00617 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
00618 
00619 #define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
00620 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
00621 
00622 /* SysTick Reload Register Definitions */
00623 #define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
00624 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
00625 
00626 /* SysTick Current Register Definitions */
00627 #define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
00628 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
00629 
00630 /* SysTick Calibration Register Definitions */
00631 #define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
00632 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
00633 
00634 #define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
00635 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
00636 
00637 #define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
00638 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos)        /*!< SysTick CALIB: TENMS Mask */
00639 
00640 /*@} end of group CMSIS_SysTick */
00641 
00642 
00643 /** \ingroup  CMSIS_core_register
00644     \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
00645     \brief      Type definitions for the Instrumentation Trace Macrocell (ITM)
00646   @{
00647  */
00648 
00649 /** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
00650  */
00651 typedef struct
00652 {
00653   __O  union
00654   {
00655     __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
00656     __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
00657     __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
00658   }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
00659        uint32_t RESERVED0[864];
00660   __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
00661        uint32_t RESERVED1[15];
00662   __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
00663        uint32_t RESERVED2[15];
00664   __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
00665        uint32_t RESERVED3[29];
00666   __O  uint32_t IWR;                     /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register            */
00667   __I  uint32_t IRR;                     /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register             */
00668   __IO uint32_t IMCR;                    /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register     */
00669        uint32_t RESERVED4[43];
00670   __O  uint32_t LAR;                     /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register                  */
00671   __I  uint32_t LSR;                     /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register                  */
00672        uint32_t RESERVED5[6];
00673   __I  uint32_t PID4;                    /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
00674   __I  uint32_t PID5;                    /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
00675   __I  uint32_t PID6;                    /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
00676   __I  uint32_t PID7;                    /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
00677   __I  uint32_t PID0;                    /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
00678   __I  uint32_t PID1;                    /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
00679   __I  uint32_t PID2;                    /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
00680   __I  uint32_t PID3;                    /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
00681   __I  uint32_t CID0;                    /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
00682   __I  uint32_t CID1;                    /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
00683   __I  uint32_t CID2;                    /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
00684   __I  uint32_t CID3;                    /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
00685 } ITM_Type;
00686 
00687 /* ITM Trace Privilege Register Definitions */
00688 #define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
00689 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
00690 
00691 /* ITM Trace Control Register Definitions */
00692 #define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
00693 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
00694 
00695 #define ITM_TCR_TraceBusID_Pos             16                                             /*!< ITM TCR: ATBID Position */
00696 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
00697 
00698 #define ITM_TCR_GTSFREQ_Pos                10                                             /*!< ITM TCR: Global timestamp frequency Position */
00699 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
00700 
00701 #define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
00702 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
00703 
00704 #define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
00705 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
00706 
00707 #define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
00708 #define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
00709 
00710 #define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
00711 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
00712 
00713 #define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
00714 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
00715 
00716 #define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
00717 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
00718 
00719 /* ITM Integration Write Register Definitions */
00720 #define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
00721 #define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
00722 
00723 /* ITM Integration Read Register Definitions */
00724 #define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
00725 #define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
00726 
00727 /* ITM Integration Mode Control Register Definitions */
00728 #define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
00729 #define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
00730 
00731 /* ITM Lock Status Register Definitions */
00732 #define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
00733 #define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
00734 
00735 #define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
00736 #define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
00737 
00738 #define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
00739 #define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
00740 
00741 /*@}*/ /* end of group CMSIS_ITM */
00742 
00743 
00744 /** \ingroup  CMSIS_core_register
00745     \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
00746     \brief      Type definitions for the Data Watchpoint and Trace (DWT)
00747   @{
00748  */
00749 
00750 /** \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
00751  */
00752 typedef struct
00753 {
00754   __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  Control Register                          */
00755   __IO uint32_t CYCCNT;                  /*!< Offset: 0x004 (R/W)  Cycle Count Register                      */
00756   __IO uint32_t CPICNT;                  /*!< Offset: 0x008 (R/W)  CPI Count Register                        */
00757   __IO uint32_t EXCCNT;                  /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register         */
00758   __IO uint32_t SLEEPCNT;                /*!< Offset: 0x010 (R/W)  Sleep Count Register                      */
00759   __IO uint32_t LSUCNT;                  /*!< Offset: 0x014 (R/W)  LSU Count Register                        */
00760   __IO uint32_t FOLDCNT;                 /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register         */
00761   __I  uint32_t PCSR;                    /*!< Offset: 0x01C (R/ )  Program Counter Sample Register           */
00762   __IO uint32_t COMP0;                   /*!< Offset: 0x020 (R/W)  Comparator Register 0                     */
00763   __IO uint32_t MASK0;                   /*!< Offset: 0x024 (R/W)  Mask Register 0                           */
00764   __IO uint32_t FUNCTION0;               /*!< Offset: 0x028 (R/W)  Function Register 0                       */
00765        uint32_t RESERVED0[1];
00766   __IO uint32_t COMP1;                   /*!< Offset: 0x030 (R/W)  Comparator Register 1                     */
00767   __IO uint32_t MASK1;                   /*!< Offset: 0x034 (R/W)  Mask Register 1                           */
00768   __IO uint32_t FUNCTION1;               /*!< Offset: 0x038 (R/W)  Function Register 1                       */
00769        uint32_t RESERVED1[1];
00770   __IO uint32_t COMP2;                   /*!< Offset: 0x040 (R/W)  Comparator Register 2                     */
00771   __IO uint32_t MASK2;                   /*!< Offset: 0x044 (R/W)  Mask Register 2                           */
00772   __IO uint32_t FUNCTION2;               /*!< Offset: 0x048 (R/W)  Function Register 2                       */
00773        uint32_t RESERVED2[1];
00774   __IO uint32_t COMP3;                   /*!< Offset: 0x050 (R/W)  Comparator Register 3                     */
00775   __IO uint32_t MASK3;                   /*!< Offset: 0x054 (R/W)  Mask Register 3                           */
00776   __IO uint32_t FUNCTION3;               /*!< Offset: 0x058 (R/W)  Function Register 3                       */
00777 } DWT_Type;
00778 
00779 /* DWT Control Register Definitions */
00780 #define DWT_CTRL_NUMCOMP_Pos               28                                          /*!< DWT CTRL: NUMCOMP Position */
00781 #define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
00782 
00783 #define DWT_CTRL_NOTRCPKT_Pos              27                                          /*!< DWT CTRL: NOTRCPKT Position */
00784 #define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
00785 
00786 #define DWT_CTRL_NOEXTTRIG_Pos             26                                          /*!< DWT CTRL: NOEXTTRIG Position */
00787 #define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
00788 
00789 #define DWT_CTRL_NOCYCCNT_Pos              25                                          /*!< DWT CTRL: NOCYCCNT Position */
00790 #define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
00791 
00792 #define DWT_CTRL_NOPRFCNT_Pos              24                                          /*!< DWT CTRL: NOPRFCNT Position */
00793 #define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
00794 
00795 #define DWT_CTRL_CYCEVTENA_Pos             22                                          /*!< DWT CTRL: CYCEVTENA Position */
00796 #define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
00797 
00798 #define DWT_CTRL_FOLDEVTENA_Pos            21                                          /*!< DWT CTRL: FOLDEVTENA Position */
00799 #define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
00800 
00801 #define DWT_CTRL_LSUEVTENA_Pos             20                                          /*!< DWT CTRL: LSUEVTENA Position */
00802 #define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
00803 
00804 #define DWT_CTRL_SLEEPEVTENA_Pos           19                                          /*!< DWT CTRL: SLEEPEVTENA Position */
00805 #define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
00806 
00807 #define DWT_CTRL_EXCEVTENA_Pos             18                                          /*!< DWT CTRL: EXCEVTENA Position */
00808 #define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
00809 
00810 #define DWT_CTRL_CPIEVTENA_Pos             17                                          /*!< DWT CTRL: CPIEVTENA Position */
00811 #define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
00812 
00813 #define DWT_CTRL_EXCTRCENA_Pos             16                                          /*!< DWT CTRL: EXCTRCENA Position */
00814 #define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
00815 
00816 #define DWT_CTRL_PCSAMPLENA_Pos            12                                          /*!< DWT CTRL: PCSAMPLENA Position */
00817 #define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
00818 
00819 #define DWT_CTRL_SYNCTAP_Pos               10                                          /*!< DWT CTRL: SYNCTAP Position */
00820 #define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
00821 
00822 #define DWT_CTRL_CYCTAP_Pos                 9                                          /*!< DWT CTRL: CYCTAP Position */
00823 #define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
00824 
00825 #define DWT_CTRL_POSTINIT_Pos               5                                          /*!< DWT CTRL: POSTINIT Position */
00826 #define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
00827 
00828 #define DWT_CTRL_POSTPRESET_Pos             1                                          /*!< DWT CTRL: POSTPRESET Position */
00829 #define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
00830 
00831 #define DWT_CTRL_CYCCNTENA_Pos              0                                          /*!< DWT CTRL: CYCCNTENA Position */
00832 #define DWT_CTRL_CYCCNTENA_Msk             (0x1UL << DWT_CTRL_CYCCNTENA_Pos)           /*!< DWT CTRL: CYCCNTENA Mask */
00833 
00834 /* DWT CPI Count Register Definitions */
00835 #define DWT_CPICNT_CPICNT_Pos               0                                          /*!< DWT CPICNT: CPICNT Position */
00836 #define DWT_CPICNT_CPICNT_Msk              (0xFFUL << DWT_CPICNT_CPICNT_Pos)           /*!< DWT CPICNT: CPICNT Mask */
00837 
00838 /* DWT Exception Overhead Count Register Definitions */
00839 #define DWT_EXCCNT_EXCCNT_Pos               0                                          /*!< DWT EXCCNT: EXCCNT Position */
00840 #define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)           /*!< DWT EXCCNT: EXCCNT Mask */
00841 
00842 /* DWT Sleep Count Register Definitions */
00843 #define DWT_SLEEPCNT_SLEEPCNT_Pos           0                                          /*!< DWT SLEEPCNT: SLEEPCNT Position */
00844 #define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)       /*!< DWT SLEEPCNT: SLEEPCNT Mask */
00845 
00846 /* DWT LSU Count Register Definitions */
00847 #define DWT_LSUCNT_LSUCNT_Pos               0                                          /*!< DWT LSUCNT: LSUCNT Position */
00848 #define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)           /*!< DWT LSUCNT: LSUCNT Mask */
00849 
00850 /* DWT Folded-instruction Count Register Definitions */
00851 #define DWT_FOLDCNT_FOLDCNT_Pos             0                                          /*!< DWT FOLDCNT: FOLDCNT Position */
00852 #define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)         /*!< DWT FOLDCNT: FOLDCNT Mask */
00853 
00854 /* DWT Comparator Mask Register Definitions */
00855 #define DWT_MASK_MASK_Pos                   0                                          /*!< DWT MASK: MASK Position */
00856 #define DWT_MASK_MASK_Msk                  (0x1FUL << DWT_MASK_MASK_Pos)               /*!< DWT MASK: MASK Mask */
00857 
00858 /* DWT Comparator Function Register Definitions */
00859 #define DWT_FUNCTION_MATCHED_Pos           24                                          /*!< DWT FUNCTION: MATCHED Position */
00860 #define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
00861 
00862 #define DWT_FUNCTION_DATAVADDR1_Pos        16                                          /*!< DWT FUNCTION: DATAVADDR1 Position */
00863 #define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
00864 
00865 #define DWT_FUNCTION_DATAVADDR0_Pos        12                                          /*!< DWT FUNCTION: DATAVADDR0 Position */
00866 #define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
00867 
00868 #define DWT_FUNCTION_DATAVSIZE_Pos         10                                          /*!< DWT FUNCTION: DATAVSIZE Position */
00869 #define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
00870 
00871 #define DWT_FUNCTION_LNK1ENA_Pos            9                                          /*!< DWT FUNCTION: LNK1ENA Position */
00872 #define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
00873 
00874 #define DWT_FUNCTION_DATAVMATCH_Pos         8                                          /*!< DWT FUNCTION: DATAVMATCH Position */
00875 #define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
00876 
00877 #define DWT_FUNCTION_CYCMATCH_Pos           7                                          /*!< DWT FUNCTION: CYCMATCH Position */
00878 #define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
00879 
00880 #define DWT_FUNCTION_EMITRANGE_Pos          5                                          /*!< DWT FUNCTION: EMITRANGE Position */
00881 #define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
00882 
00883 #define DWT_FUNCTION_FUNCTION_Pos           0                                          /*!< DWT FUNCTION: FUNCTION Position */
00884 #define DWT_FUNCTION_FUNCTION_Msk          (0xFUL << DWT_FUNCTION_FUNCTION_Pos)        /*!< DWT FUNCTION: FUNCTION Mask */
00885 
00886 /*@}*/ /* end of group CMSIS_DWT */
00887 
00888 
00889 /** \ingroup  CMSIS_core_register
00890     \defgroup CMSIS_TPI     Trace Port Interface (TPI)
00891     \brief      Type definitions for the Trace Port Interface (TPI)
00892   @{
00893  */
00894 
00895 /** \brief  Structure type to access the Trace Port Interface Register (TPI).
00896  */
00897 typedef struct
00898 {
00899   __IO uint32_t SSPSR;                   /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register     */
00900   __IO uint32_t CSPSR;                   /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
00901        uint32_t RESERVED0[2];
00902   __IO uint32_t ACPR;                    /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
00903        uint32_t RESERVED1[55];
00904   __IO uint32_t SPPR;                    /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
00905        uint32_t RESERVED2[131];
00906   __I  uint32_t FFSR;                    /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
00907   __IO uint32_t FFCR;                    /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
00908   __I  uint32_t FSCR;                    /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
00909        uint32_t RESERVED3[759];
00910   __I  uint32_t TRIGGER;                 /*!< Offset: 0xEE8 (R/ )  TRIGGER */
00911   __I  uint32_t FIFO0;                   /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
00912   __I  uint32_t ITATBCTR2;               /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
00913        uint32_t RESERVED4[1];
00914   __I  uint32_t ITATBCTR0;               /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
00915   __I  uint32_t FIFO1;                   /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
00916   __IO uint32_t ITCTRL;                  /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
00917        uint32_t RESERVED5[39];
00918   __IO uint32_t CLAIMSET;                /*!< Offset: 0xFA0 (R/W)  Claim tag set */
00919   __IO uint32_t CLAIMCLR;                /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
00920        uint32_t RESERVED7[8];
00921   __I  uint32_t DEVID;                   /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
00922   __I  uint32_t DEVTYPE;                 /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
00923 } TPI_Type;
00924 
00925 /* TPI Asynchronous Clock Prescaler Register Definitions */
00926 #define TPI_ACPR_PRESCALER_Pos              0                                          /*!< TPI ACPR: PRESCALER Position */
00927 #define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)        /*!< TPI ACPR: PRESCALER Mask */
00928 
00929 /* TPI Selected Pin Protocol Register Definitions */
00930 #define TPI_SPPR_TXMODE_Pos                 0                                          /*!< TPI SPPR: TXMODE Position */
00931 #define TPI_SPPR_TXMODE_Msk                (0x3UL << TPI_SPPR_TXMODE_Pos)              /*!< TPI SPPR: TXMODE Mask */
00932 
00933 /* TPI Formatter and Flush Status Register Definitions */
00934 #define TPI_FFSR_FtNonStop_Pos              3                                          /*!< TPI FFSR: FtNonStop Position */
00935 #define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
00936 
00937 #define TPI_FFSR_TCPresent_Pos              2                                          /*!< TPI FFSR: TCPresent Position */
00938 #define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
00939 
00940 #define TPI_FFSR_FtStopped_Pos              1                                          /*!< TPI FFSR: FtStopped Position */
00941 #define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
00942 
00943 #define TPI_FFSR_FlInProg_Pos               0                                          /*!< TPI FFSR: FlInProg Position */
00944 #define TPI_FFSR_FlInProg_Msk              (0x1UL << TPI_FFSR_FlInProg_Pos)            /*!< TPI FFSR: FlInProg Mask */
00945 
00946 /* TPI Formatter and Flush Control Register Definitions */
00947 #define TPI_FFCR_TrigIn_Pos                 8                                          /*!< TPI FFCR: TrigIn Position */
00948 #define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
00949 
00950 #define TPI_FFCR_EnFCont_Pos                1                                          /*!< TPI FFCR: EnFCont Position */
00951 #define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
00952 
00953 /* TPI TRIGGER Register Definitions */
00954 #define TPI_TRIGGER_TRIGGER_Pos             0                                          /*!< TPI TRIGGER: TRIGGER Position */
00955 #define TPI_TRIGGER_TRIGGER_Msk            (0x1UL << TPI_TRIGGER_TRIGGER_Pos)          /*!< TPI TRIGGER: TRIGGER Mask */
00956 
00957 /* TPI Integration ETM Data Register Definitions (FIFO0) */
00958 #define TPI_FIFO0_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO0: ITM_ATVALID Position */
00959 #define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
00960 
00961 #define TPI_FIFO0_ITM_bytecount_Pos        27                                          /*!< TPI FIFO0: ITM_bytecount Position */
00962 #define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
00963 
00964 #define TPI_FIFO0_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO0: ETM_ATVALID Position */
00965 #define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
00966 
00967 #define TPI_FIFO0_ETM_bytecount_Pos        24                                          /*!< TPI FIFO0: ETM_bytecount Position */
00968 #define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
00969 
00970 #define TPI_FIFO0_ETM2_Pos                 16                                          /*!< TPI FIFO0: ETM2 Position */
00971 #define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
00972 
00973 #define TPI_FIFO0_ETM1_Pos                  8                                          /*!< TPI FIFO0: ETM1 Position */
00974 #define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
00975 
00976 #define TPI_FIFO0_ETM0_Pos                  0                                          /*!< TPI FIFO0: ETM0 Position */
00977 #define TPI_FIFO0_ETM0_Msk                 (0xFFUL << TPI_FIFO0_ETM0_Pos)              /*!< TPI FIFO0: ETM0 Mask */
00978 
00979 /* TPI ITATBCTR2 Register Definitions */
00980 #define TPI_ITATBCTR2_ATREADY_Pos           0                                          /*!< TPI ITATBCTR2: ATREADY Position */
00981 #define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)        /*!< TPI ITATBCTR2: ATREADY Mask */
00982 
00983 /* TPI Integration ITM Data Register Definitions (FIFO1) */
00984 #define TPI_FIFO1_ITM_ATVALID_Pos          29                                          /*!< TPI FIFO1: ITM_ATVALID Position */
00985 #define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
00986 
00987 #define TPI_FIFO1_ITM_bytecount_Pos        27                                          /*!< TPI FIFO1: ITM_bytecount Position */
00988 #define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
00989 
00990 #define TPI_FIFO1_ETM_ATVALID_Pos          26                                          /*!< TPI FIFO1: ETM_ATVALID Position */
00991 #define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
00992 
00993 #define TPI_FIFO1_ETM_bytecount_Pos        24                                          /*!< TPI FIFO1: ETM_bytecount Position */
00994 #define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
00995 
00996 #define TPI_FIFO1_ITM2_Pos                 16                                          /*!< TPI FIFO1: ITM2 Position */
00997 #define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
00998 
00999 #define TPI_FIFO1_ITM1_Pos                  8                                          /*!< TPI FIFO1: ITM1 Position */
01000 #define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
01001 
01002 #define TPI_FIFO1_ITM0_Pos                  0                                          /*!< TPI FIFO1: ITM0 Position */
01003 #define TPI_FIFO1_ITM0_Msk                 (0xFFUL << TPI_FIFO1_ITM0_Pos)              /*!< TPI FIFO1: ITM0 Mask */
01004 
01005 /* TPI ITATBCTR0 Register Definitions */
01006 #define TPI_ITATBCTR0_ATREADY_Pos           0                                          /*!< TPI ITATBCTR0: ATREADY Position */
01007 #define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)        /*!< TPI ITATBCTR0: ATREADY Mask */
01008 
01009 /* TPI Integration Mode Control Register Definitions */
01010 #define TPI_ITCTRL_Mode_Pos                 0                                          /*!< TPI ITCTRL: Mode Position */
01011 #define TPI_ITCTRL_Mode_Msk                (0x1UL << TPI_ITCTRL_Mode_Pos)              /*!< TPI ITCTRL: Mode Mask */
01012 
01013 /* TPI DEVID Register Definitions */
01014 #define TPI_DEVID_NRZVALID_Pos             11                                          /*!< TPI DEVID: NRZVALID Position */
01015 #define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
01016 
01017 #define TPI_DEVID_MANCVALID_Pos            10                                          /*!< TPI DEVID: MANCVALID Position */
01018 #define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
01019 
01020 #define TPI_DEVID_PTINVALID_Pos             9                                          /*!< TPI DEVID: PTINVALID Position */
01021 #define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
01022 
01023 #define TPI_DEVID_MinBufSz_Pos              6                                          /*!< TPI DEVID: MinBufSz Position */
01024 #define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
01025 
01026 #define TPI_DEVID_AsynClkIn_Pos             5                                          /*!< TPI DEVID: AsynClkIn Position */
01027 #define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
01028 
01029 #define TPI_DEVID_NrTraceInput_Pos          0                                          /*!< TPI DEVID: NrTraceInput Position */
01030 #define TPI_DEVID_NrTraceInput_Msk         (0x1FUL << TPI_DEVID_NrTraceInput_Pos)      /*!< TPI DEVID: NrTraceInput Mask */
01031 
01032 /* TPI DEVTYPE Register Definitions */
01033 #define TPI_DEVTYPE_SubType_Pos             0                                          /*!< TPI DEVTYPE: SubType Position */
01034 #define TPI_DEVTYPE_SubType_Msk            (0xFUL << TPI_DEVTYPE_SubType_Pos)          /*!< TPI DEVTYPE: SubType Mask */
01035 
01036 #define TPI_DEVTYPE_MajorType_Pos           4                                          /*!< TPI DEVTYPE: MajorType Position */
01037 #define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
01038 
01039 /*@}*/ /* end of group CMSIS_TPI */
01040 
01041 
01042 #if (__MPU_PRESENT == 1)
01043 /** \ingroup  CMSIS_core_register
01044     \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
01045     \brief      Type definitions for the Memory Protection Unit (MPU)
01046   @{
01047  */
01048 
01049 /** \brief  Structure type to access the Memory Protection Unit (MPU).
01050  */
01051 typedef struct
01052 {
01053   __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
01054   __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
01055   __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
01056   __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
01057   __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
01058   __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
01059   __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
01060   __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
01061   __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
01062   __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
01063   __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
01064 } MPU_Type;
01065 
01066 /* MPU Type Register */
01067 #define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
01068 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
01069 
01070 #define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
01071 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
01072 
01073 #define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
01074 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
01075 
01076 /* MPU Control Register */
01077 #define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
01078 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
01079 
01080 #define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
01081 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
01082 
01083 #define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
01084 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
01085 
01086 /* MPU Region Number Register */
01087 #define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
01088 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
01089 
01090 /* MPU Region Base Address Register */
01091 #define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
01092 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
01093 
01094 #define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
01095 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
01096 
01097 #define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
01098 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
01099 
01100 /* MPU Region Attribute and Size Register */
01101 #define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
01102 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
01103 
01104 #define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
01105 #define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
01106 
01107 #define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
01108 #define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
01109 
01110 #define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
01111 #define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
01112 
01113 #define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
01114 #define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
01115 
01116 #define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
01117 #define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
01118 
01119 #define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
01120 #define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
01121 
01122 #define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
01123 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
01124 
01125 #define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
01126 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
01127 
01128 #define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
01129 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
01130 
01131 /*@} end of group CMSIS_MPU */
01132 #endif
01133 
01134 
01135 /** \ingroup  CMSIS_core_register
01136     \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
01137     \brief      Type definitions for the Core Debug Registers
01138   @{
01139  */
01140 
01141 /** \brief  Structure type to access the Core Debug Register (CoreDebug).
01142  */
01143 typedef struct
01144 {
01145   __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
01146   __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
01147   __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
01148   __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
01149 } CoreDebug_Type;
01150 
01151 /* Debug Halting Control and Status Register */
01152 #define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
01153 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
01154 
01155 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
01156 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
01157 
01158 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
01159 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
01160 
01161 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
01162 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
01163 
01164 #define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
01165 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
01166 
01167 #define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
01168 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
01169 
01170 #define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
01171 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
01172 
01173 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
01174 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
01175 
01176 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
01177 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
01178 
01179 #define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
01180 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
01181 
01182 #define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
01183 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
01184 
01185 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
01186 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
01187 
01188 /* Debug Core Register Selector Register */
01189 #define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
01190 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
01191 
01192 #define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
01193 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
01194 
01195 /* Debug Exception and Monitor Control Register */
01196 #define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
01197 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
01198 
01199 #define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
01200 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
01201 
01202 #define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
01203 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
01204 
01205 #define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
01206 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
01207 
01208 #define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
01209 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
01210 
01211 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
01212 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
01213 
01214 #define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
01215 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
01216 
01217 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
01218 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
01219 
01220 #define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
01221 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
01222 
01223 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
01224 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
01225 
01226 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
01227 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
01228 
01229 #define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
01230 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
01231 
01232 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
01233 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
01234 
01235 /*@} end of group CMSIS_CoreDebug */
01236 
01237 
01238 /** \ingroup    CMSIS_core_register
01239     \defgroup   CMSIS_core_base     Core Definitions
01240     \brief      Definitions for base addresses, unions, and structures.
01241   @{
01242  */
01243 
01244 /* Memory mapping of Cortex-M3 Hardware */
01245 #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
01246 #define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
01247 #define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address                   */
01248 #define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address                   */
01249 #define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
01250 #define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
01251 #define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
01252 #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
01253 
01254 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
01255 #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
01256 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
01257 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
01258 #define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
01259 #define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct           */
01260 #define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct           */
01261 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
01262 
01263 #if (__MPU_PRESENT == 1)
01264   #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
01265   #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
01266 #endif
01267 
01268 /*@} */
01269 
01270 
01271 
01272 /*******************************************************************************
01273  *                Hardware Abstraction Layer
01274   Core Function Interface contains:
01275   - Core NVIC Functions
01276   - Core SysTick Functions
01277   - Core Debug Functions
01278   - Core Register Access Functions
01279  ******************************************************************************/
01280 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
01281 */
01282 
01283 
01284 
01285 /* ##########################   NVIC functions  #################################### */
01286 /** \ingroup  CMSIS_Core_FunctionInterface
01287     \defgroup CMSIS_Core_NVICFunctions NVIC Functions
01288     \brief      Functions that manage interrupts and exceptions via the NVIC.
01289     @{
01290  */
01291 
01292 /** \brief  Set Priority Grouping
01293 
01294   The function sets the priority grouping field using the required unlock sequence.
01295   The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
01296   Only values from 0..7 are used.
01297   In case of a conflict between priority grouping and available
01298   priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01299 
01300     \param [in]      PriorityGroup  Priority grouping field.
01301  */
01302 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
01303 {
01304   uint32_t reg_value;
01305   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
01306 
01307   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
01308   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
01309   reg_value  =  (reg_value                                 |
01310                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
01311                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
01312   SCB->AIRCR =  reg_value;
01313 }
01314 
01315 
01316 /** \brief  Get Priority Grouping
01317 
01318   The function reads the priority grouping field from the NVIC Interrupt Controller.
01319 
01320     \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
01321  */
01322 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
01323 {
01324   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
01325 }
01326 
01327 
01328 /** \brief  Enable External Interrupt
01329 
01330     The function enables a device-specific interrupt in the NVIC interrupt controller.
01331 
01332     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01333  */
01334 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
01335 {
01336   NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
01337 }
01338 
01339 
01340 /** \brief  Disable External Interrupt
01341 
01342     The function disables a device-specific interrupt in the NVIC interrupt controller.
01343 
01344     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01345  */
01346 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
01347 {
01348   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
01349 }
01350 
01351 
01352 /** \brief  Get Pending Interrupt
01353 
01354     The function reads the pending register in the NVIC and returns the pending bit
01355     for the specified interrupt.
01356 
01357     \param [in]      IRQn  Interrupt number.
01358 
01359     \return             0  Interrupt status is not pending.
01360     \return             1  Interrupt status is pending.
01361  */
01362 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
01363 {
01364   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
01365 }
01366 
01367 
01368 /** \brief  Set Pending Interrupt
01369 
01370     The function sets the pending bit of an external interrupt.
01371 
01372     \param [in]      IRQn  Interrupt number. Value cannot be negative.
01373  */
01374 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
01375 {
01376   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
01377 }
01378 
01379 
01380 /** \brief  Clear Pending Interrupt
01381 
01382     The function clears the pending bit of an external interrupt.
01383 
01384     \param [in]      IRQn  External interrupt number. Value cannot be negative.
01385  */
01386 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
01387 {
01388   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
01389 }
01390 
01391 
01392 /** \brief  Get Active Interrupt
01393 
01394     The function reads the active register in NVIC and returns the active bit.
01395 
01396     \param [in]      IRQn  Interrupt number.
01397 
01398     \return             0  Interrupt status is not active.
01399     \return             1  Interrupt status is active.
01400  */
01401 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
01402 {
01403   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
01404 }
01405 
01406 
01407 /** \brief  Set Interrupt Priority
01408 
01409     The function sets the priority of an interrupt.
01410 
01411     \note The priority cannot be set for every core interrupt.
01412 
01413     \param [in]      IRQn  Interrupt number.
01414     \param [in]  priority  Priority to set.
01415  */
01416 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
01417 {
01418   if(IRQn < 0) {
01419     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
01420   else {
01421     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
01422 }
01423 
01424 
01425 /** \brief  Get Interrupt Priority
01426 
01427     The function reads the priority of an interrupt. The interrupt
01428     number can be positive to specify an external (device specific)
01429     interrupt, or negative to specify an internal (core) interrupt.
01430 
01431 
01432     \param [in]   IRQn  Interrupt number.
01433     \return             Interrupt Priority. Value is aligned automatically to the implemented
01434                         priority bits of the microcontroller.
01435  */
01436 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
01437 {
01438 
01439   if(IRQn < 0) {
01440     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
01441   else {
01442     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
01443 }
01444 
01445 
01446 /** \brief  Encode Priority
01447 
01448     The function encodes the priority for an interrupt with the given priority group,
01449     preemptive priority value, and subpriority value.
01450     In case of a conflict between priority grouping and available
01451     priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
01452 
01453     \param [in]     PriorityGroup  Used priority group.
01454     \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
01455     \param [in]       SubPriority  Subpriority value (starting from 0).
01456     \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
01457  */
01458 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
01459 {
01460   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01461   uint32_t PreemptPriorityBits;
01462   uint32_t SubPriorityBits;
01463 
01464   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01465   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01466 
01467   return (
01468            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
01469            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
01470          );
01471 }
01472 
01473 
01474 /** \brief  Decode Priority
01475 
01476     The function decodes an interrupt priority value with a given priority group to
01477     preemptive priority value and subpriority value.
01478     In case of a conflict between priority grouping and available
01479     priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
01480 
01481     \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
01482     \param [in]     PriorityGroup  Used priority group.
01483     \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
01484     \param [out]     pSubPriority  Subpriority value (starting from 0).
01485  */
01486 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
01487 {
01488   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
01489   uint32_t PreemptPriorityBits;
01490   uint32_t SubPriorityBits;
01491 
01492   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
01493   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
01494 
01495   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
01496   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
01497 }
01498 
01499 
01500 /** \brief  System Reset
01501 
01502     The function initiates a system reset request to reset the MCU.
01503  */
01504 __STATIC_INLINE void NVIC_SystemReset(void)
01505 {
01506   __DSB();                                                     /* Ensure all outstanding memory accesses included
01507                                                                   buffered write are completed before reset */
01508   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
01509                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
01510                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
01511   __DSB();                                                     /* Ensure completion of memory access */
01512   while(1);                                                    /* wait until reset */
01513 }
01514 
01515 /*@} end of CMSIS_Core_NVICFunctions */
01516 
01517 
01518 
01519 /* ##################################    SysTick function  ############################################ */
01520 /** \ingroup  CMSIS_Core_FunctionInterface
01521     \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
01522     \brief      Functions that configure the System.
01523   @{
01524  */
01525 
01526 #if (__Vendor_SysTickConfig == 0)
01527 
01528 /** \brief  System Tick Configuration
01529 
01530     The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
01531     Counter is in free running mode to generate periodic interrupts.
01532 
01533     \param [in]  ticks  Number of ticks between two interrupts.
01534 
01535     \return          0  Function succeeded.
01536     \return          1  Function failed.
01537 
01538     \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
01539     function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
01540     must contain a vendor-specific implementation of this function.
01541 
01542  */
01543 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
01544 {
01545   if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk)  return (1);      /* Reload value impossible */
01546 
01547   SysTick->LOAD  = ticks - 1;                                  /* set reload register */
01548   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Systick Interrupt */
01549   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
01550   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
01551                    SysTick_CTRL_TICKINT_Msk   |
01552                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
01553   return (0);                                                  /* Function successful */
01554 }
01555 
01556 #endif
01557 
01558 /*@} end of CMSIS_Core_SysTickFunctions */
01559 
01560 
01561 
01562 /* ##################################### Debug In/Output function ########################################### */
01563 /** \ingroup  CMSIS_Core_FunctionInterface
01564     \defgroup CMSIS_core_DebugFunctions ITM Functions
01565     \brief   Functions that access the ITM debug interface.
01566   @{
01567  */
01568 
01569 extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters.                         */
01570 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
01571 
01572 
01573 /** \brief  ITM Send Character
01574 
01575     The function transmits a character via the ITM channel 0, and
01576     \li Just returns when no debugger is connected that has booked the output.
01577     \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
01578 
01579     \param [in]     ch  Character to transmit.
01580 
01581     \returns            Character to transmit.
01582  */
01583 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
01584 {
01585   if ((ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
01586       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
01587   {
01588     while (ITM->PORT[0].u32 == 0);
01589     ITM->PORT[0].u8 = (uint8_t) ch;
01590   }
01591   return (ch);
01592 }
01593 
01594 
01595 /** \brief  ITM Receive Character
01596 
01597     The function inputs a character via the external variable \ref ITM_RxBuffer.
01598 
01599     \return             Received character.
01600     \return         -1  No character pending.
01601  */
01602 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
01603   int32_t ch = -1;                           /* no character available */
01604 
01605   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
01606     ch = ITM_RxBuffer;
01607     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
01608   }
01609 
01610   return (ch);
01611 }
01612 
01613 
01614 /** \brief  ITM Check Character
01615 
01616     The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
01617 
01618     \return          0  No character available.
01619     \return          1  Character available.
01620  */
01621 __STATIC_INLINE int32_t ITM_CheckChar (void) {
01622 
01623   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
01624     return (0);                                 /* no character available */
01625   } else {
01626     return (1);                                 /*    character available */
01627   }
01628 }
01629 
01630 /*@} end of CMSIS_core_DebugFunctions */
01631 
01632 #endif /* __CORE_CM3_H_DEPENDANT */
01633 
01634 #ifdef __cplusplus
01635 }
01636 #endif
01637 
01638 #endif /* __CMSIS_GENERIC */